Toshiba TMPR7901, User Manual

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Chapter 3: Configuration
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
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C790
High performance MIPS RISC processor core with 128-bit internal system bus interface.
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MAC
Dual 10/100Mbps Ethernet MAC with scatter-gather DMA bus master capability.
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PCI Bridge
32-bit PCI bus interface compliance with PCI Local Bus Specification Rev. 2.1. PCI0 is
66 MHz/32-bit PCI. PCI1 is 33 MHz/32-bit PCI.
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SDRAMC
SDRAM memory controller
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DMAC
8-channel DMA controller
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INTC
22 internal and external sources of interrupts, and interrupt controller for these interrupt
sources.
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Timers
3-channel 24-bit up counters work as the interval timer, pulse generator, and watchdog
timer.
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UART
2-channel serial I/Os, NS 16550 software compatible
Channel 0 has full function. Channel 1 has two pins (SW, SOUT) only, and is used for
the debug monitor.
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SPI
Serial Peripheral Interface connects the serial Boot ROM and Real-time clock
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64-Bit G-Bus Bridge
A bridge between the 128-bit internal system bus and the 64-bit G-Bus
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PLL
Phase-Locked-Loop to generate the TX7901’s internal clocks from an external oscillator
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Test Logic
Supports Scan and JTAG.