Toshiba TMPR7901, User Manual

Page: 115 / 309

Chapter 7: C790 Bus/G-Bus Bridge
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
7-17
7.6.18 NMI Status Register (NRSTAT)
The NMI Status Register reports the status of the Non-Maskable interrupt requests. An
interrupt is generated if a bit in the register is set to “1.” The NMI handler analyzes the cause
of the NMI and serves the request. After service is finished, the handler must reset the
cause of the NMI. Then, the handler returns from the NMI, if possible.
63 32
0
32
31 3 2 1 0
0
NMI
EXT
NMI
WDOG
NMI
ECC
29 1 1 1
Table 7-20 NMI Status Register
Bit(s) Field R/W Description Initial Value
63:3 – R/O
Reserved. Must be written as zeroes, and
returns zeroes when read.
0
2 NMI EXT R/O External NMI input 1
1 NMI WDOG R/O Timer Watchdog at Time2 1
0 NMI ECC R/O ECC uncorrectable Error 1
7.6.19 G-Bus Master Latency Timer
The latency timer specifies the maximum period in which the master can hold the G-Bus
when other masters are requesting the G-Bus. The counter is decremented at every G-Bus
clock cycle. When the counter counts down to zero and there is a pending G-Bus request,
the gbsgRelB signal is asserted to request the current master to release the G-Bus.
63 32
0
32
31 16 15 0
0 GBMLT
16 16
Table 7-21 G-Bus Master Latency Timer
Bits Field R/W Description Initial Value
63:16 – R/O
Reserved. Must be written as zeroes, and
returns zeroes when read.
0
15:0 GBMLT R/W
Latency Timer. Is counted down by the G-Bus
clock
0xFFFF