Toshiba TMPR7901, User Manual

Page: 272 / 309

Chapter 14: UARTS WITH FIFOS
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
14-12
Priority 4) Reading the Modem Status Register
When multiple interrupts are pending, the interrupt line pulses Low after each service.
After reset, D0 = “1”, D1 – D7 = “0”.
14.4.7.1 Receive Timeout Interrupt
ID2 = “1” indicates an RX FIFO Character Timeout.
A RX FIFO Character Timeout occurs if all of the following apply:
1. There is at least one character in the FIFO.
2. The most recent character was received longer than four character periods ago
(inclusive of all start, parity, and stop bits).
3. The most recent G-Bus read of the FIFO was longer than four character periods ago.
The Character Timeout is dependent on the RX clock.
The Timeout Interrupt is cleared by a G-Bus read from the RX FIFO.
The Timeout timer is restarted on receipt of a new byte from the RX Shift Register, or on a
G-Bus read from the RX FIFO.
14.4.7.2 TX FIFO Interrupt
The TX Holding Register Interrupt occurs when the TX FIFO is empty. It is cleared by writing
to the TX Holding Register or by reading from the IIR.
The TX FIFO Empty interrupt will be delayed one character period minus the last stop bit
period whenever THRE = 1 and are not at least two bytes in the TX FIFO at the same time.
If the TX interrupt is enabled, setting bit 0 of the FCR will generate an immediate interrupt.
14.4.7.3 FIFO Polled Operation
If the FIFOs are enabled and at least one of the active bits in the IER is disabled, the UART
will operate in the FIFO Polled mode. Since the Transmit and Receive paths are controlled
separately, either one or both can be in the Polled mode. The application software should
check Transmit and Receive status using the LSR.