Toshiba TMPR7901, User Manual

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Chapter 14: UARTS WITH FIFOS
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
14-7
14.4.4.2 STB – Number of stop bits
When set (“1”), two STOP bits are added after each character is sent, unless the character
length is 5 when 1½ STOP bits are added. When cleared (“0”), one STOP bit is always
added.
Note: Only the Transmit STOP bits are programmable. The Receive stage only expects one STOP bit,
irrespective of the value of STB.
14.4.4.3 PEN – Parity Enabled
When set (“1”), the parity is transmitted and checked. The Parity bit is added after the data
field and before the STOP bits.
When cleared (“0”), the parity is neither transmitted nor checked.
14.4.4.4 EPS – Even Parity Select
When EPS = “1” and PEN = “1”, an even number of ones is sent and checked. When EPS =
“0” and PEN = “1”, an odd number of ones is sent and checked.
14.4.4.5 SP – Stick Parity
When set (“1”), the Parity bit is forced into a defined state, dependent upon the values of
EPS and PEN:
If EPS = “1” & PEN = “1”, the Parity bit is transmitted and checked as “0”.
If EPS = “0” & PEN = “1”, the Parity bit is transmitted and checked as “1”.
14.4.4.6 SB – Set Break
When set (“1”), a break condition is transmitted to the receiving UART, and the serial output
(SOUT) is forced to “0.”
14.4.4.7 DLAB – Divisor Latch Address Bit
Controls access to alternate registers at addresses 0 and 1.
When cleared (“0”), the RX and TX registers, and the IER register are read/written to.
When set (“1”), LS and MS of the Divisor Latch are read/written to.