12.5.2.1 SPI Configuration Control Register (SPICCR) (Offset = 0h) [reset = 0h]
SPICCR controls the setup of the SPI for operation.
Figure 12-13. SPI Configuration Control Register (SPICCR)
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
SPISWRESET CLKPOLARITY
RESERVED
SPILBK
SPICHAR
R/W-0h
R/W-0h
R-0h
R/W-0h
R/W-0h
Table 12-9. SPI Configuration Control Register (SPICCR) Field Descriptions
Bit
Field
Type
Reset
Description
15-8
RESERVED
R
0h
Reserved
7
SPISWRESET
R/W
0h
SPI Software Reset
When changing configuration, you should clear this bit before the
changes and set this bit before resuming operation.
Reset type: SYSRSn
0h (R/W) = Initializes the SPI operating flags to the reset condition.
Specifically, the RECEIVER OVERRUN Flag bit (SPISTS.7), the
SPI INT FLAG bit (SPISTS.6), and the TXBUF FULL Flag bit
(SPISTS.5) are cleared. SPISTE will become inactive. SPICLK will
be immediately driven to 0 regardless of the clock polarity. The SPI
configuration remains unchanged.
1h (R/W) = SPI is ready to transmit or receive the next character.
When the SPI SW RESET bit is a 0, a character written to the
transmitter will not be shifted out when this bit is set. A new character
must be written to the serial data register. SPICLK will be returned to
its inactive state one SPICLK cycle after this bit is set.
Serial Peripheral Interface (SPI)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
781
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Summary of Contents for TMS320 2806 Series
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