1.3.2.4.1.2 PLL Status Register (PLLSTS)
Figure 1-26. PLL Status Register (PLLSTS)
15
14
9
8
NORMRDYE
Reserved
DIVSEL
R/W-0
R-0
R/W-0
7
6
5
4
3
2
1
0
DIVSEL
MCLKOFF
OSCOFF
MCLKCLR
MCLKSTS
PLLOFF
Reserved
PLLLOCKS
R/W-0
R/W-0
R/W-0
W-0
R-0
R/W-0
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-25. PLL Status Register (PLLSTS) Field Descriptions
Bits
Field
Value
Description
15
NORMRDYE
NORMRDY Enable Bit: This bit selects if NORMRDY signal from VREG gates the PLL from turning
on when the VREG is out of regulation. It may be required to keep the PLL off while coming in and
out of HALT mode and this signal can be used for that purpose:
0
NORMRDY signal from VREG does not gate PLL (PLL ignores NORMRDY)
1
NORMRDY signal from VREG will gate PLL (PLL off when NORMRDY low)
The NORMRDY signal from the VREG is low when the VREG is out of regulation and this signal
will go high if the VREG is within regulation.
14-9
Reserved
Any writes to these bits must always have a value of 0.
8:7
DIVSEL
Divide Select: This bit selects between /4, /2, and /1 for CLKIN to the CPU.
The configuration of the DIVSEL bit is as follows:
00, 01
Select Divide By 4 for CLKIN
10
Select Divide By 2 for CLKIN
11
Select Divide By 1 for CLKIN
6
MCLKOFF
Missing clock-detect off bit
0
Main oscillator fail-detect logic is enabled. (default)
1
Main oscillator fail-detect logic is disabled and the PLL will not issue a limp-mode clock. Use this
mode when code must not be affected by the detection circuit. For example, if external clocks are
turned off.
5
OSCOFF
Oscillator Clock Off Bit
0
The OSCCLK signal from X1/X2 or XCLKIN is fed to the PLL block. (default)
1
The OSCCLK signal from X1/X2 or XCLKIN is not fed to the PLL block. This does not shut down
the internal oscillator. The OSCOFF bit is used for testing the missing clock detection logic.
When the OSCOFF bit is set, do not enter HALT or STANDBY modes or write to PLLCR as these
operations can result in unpredictable behavior.
When the OSCOFF bit is set, the behavior of the watchdog is different depending on which input
clock source (X1, X1/X2 or XCLKIN) is being used:
•
X1/X2: The watchdog is not functional.
•
XCLKIN: The watchdog is functional and should be disabled before setting OSCOFF.
4
MCLKCLR
Missing Clock Clear Bit.
0
Writing a 0 has no effect. This bit always reads 0.
1
Forces the missing clock detection circuits to be cleared and reset. If OSCCLK is still missing,
the detection circuit will again generate a reset to the system, set the missing clock status bit
(MCLKSTS), and the CPU will be clocked by the PLL operating at a limp mode frequency.
System Control and Interrupts
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
79
Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
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