14.4 Interrupt Requests Generated by the I2C Module
Each I2C module can generate two CPU interrupts.
1. Basic I2C interrupt: Possible basic I2C interrupt sources that can trigger this interrupt are described in
2. I2C FIFO interrupt: Possible I2C FIFO interrupt sources that can trigger this interrupt are described in
14.4.1 Basic I2C Interrupt Requests
The I2C module generates the interrupt requests described in
, all requests
are multiplexed through an arbiter to a single I2C interrupt request to the CPU. Each interrupt request has a flag
bit in the status register (I2CSTR) and an enable bit in the interrupt enable register (I2CIER). When one of the
specified events occurs, its flag bit is set. If the corresponding enable bit is 0, the interrupt request is blocked. If
the enable bit is 1, the request is forwarded to the CPU as an I2C interrupt.
The I2C interrupt is one of the maskable interrupts of the CPU. As with any maskable interrupt request, if it is
properly enabled in the CPU, the CPU executes the corresponding interrupt service routine (I2CINT1A_ISR).
The I2CINT1A_ISR for the I2C interrupt can determine the interrupt source by reading the interrupt source
register, I2CISRC. Then the I2CINT1A_ISR can branch to the appropriate subroutine.
After the CPU reads I2CISRC, the following events occur:
1. The flag for the source interrupt is cleared in I2CSTR. Exception: The ARDY, RRDY, and XRDY bits in
I2CSTR are not cleared when I2CISRC is read. To clear one of these bits, write a 1 to it.
2. The arbiter determines which of the remaining interrupt requests has the highest priority, writes the code for
that interrupt to I2CISRC, and forwards the interrupt request to the CPU.
Table 14-6. Descriptions of the Basic I2C Interrupt Requests
I2C Interrupt Request
Interrupt Source
XRDYINT
Transmit ready condition: The data transmit register (I2CDXR) is ready to accept new data because the previous
data has been copied from I2CDXR to the transmit shift register (I2CXSR).
As an alternative to using XRDYINT, the CPU can poll the XRDY bit of the status register, I2CSTR. XRDYINT
should not be used when in FIFO mode. Use the FIFO interrupts instead.
RRDYINT
Receive ready condition: The data receive register (I2CDRR) is ready to be read because data has been copied
from the receive shift register (I2CRSR) to I2CDRR.
As an alternative to using RRDYINT, the CPU can poll the RRDY bit of I2CSTR. RRDYINT should not be used
when in FIFO mode. Use the FIFO interrupts instead.
ARDYINT
Register-access ready condition: The I2C module registers are ready to be accessed because the previously
programmed address, data, and command values have been used.
The specific events that generate ARDYINT are the same events that set the ARDY bit of I2CSTR.
As an alternative to using ARDYINT, the CPU can poll the ARDY bit.
NACKINT
No-acknowledgment condition: The I2C module is configured as a master-transmitter and did not received
acknowledgment from the slave-receiver.
As an alternative to using NACKINT, the CPU can poll the NACK bit of I2CSTR.
ARBLINT
Arbitration-lost condition: The I2C module has lost an arbitration contest with another master-transmitter.
As an alternative to using ARBLINT, the CPU can poll the ARBL bit of I2CSTR.
SCDINT
Stop condition detected: A STOP condition was detected on the I2C bus.
As an alternative to using SCDINT, the CPU can poll the SCD bit of the status register, I2CSTR.
AASINT
Addressed as slave condition: The I2C has been addressed as a slave device by another master on the I2C bus.
As an alternative to using AASINT, the CPU can poll the AAS bit of the status register, I2CSTR.
Inter-Integrated Circuit Module (I2C)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
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Summary of Contents for TMS320 2806 Series
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