5.3.3 HRCAP Interrupts
Rising edge capture (RISE), falling edge capture (FALL), and HCCOUNTER overflow (OVF) events can
generate interrupts to the PIE from the HRCAP module. Additionally, if the rising edge capture flag is set
(HCIFR[RISE]) when another rising edge capture event occurs, a rising edge overflow (RISEOVF) interrupt can
also generate an interrupt to the PIE. The HRCAP interrupt logic is shown in
RISE/RISEOVF, FALL, and OVF events will only generate an interrupt if the corresponding interrupt enable bits
in the HCCTL register are set to 1. Interrupt events can be cleared by writing a 1 to the corresponding bits in the
HCICLR register. For testing purposes, interrupt events can be forced by writing a 1 to the corresponding bits in
the HCIFRC register.
For proper operation, RISE and FALL interrupts should not be enabled at the same time. Capture registers
should be read during rising edge interrupt events only, or during falling edge interrupt events only, and not
during both interrupt events simultaneously. If RISEOVF interrupts are enabled, the RISE flag must always be
acknowledged after a RISE event, otherwise a rise overflow condition will occur.
Latch
set
clear
Generate
Interrupt
Pulse
When
Input = 1
0
0
1
HRCAPxINTn
HCICLR[INT]
HCIFR[INT]
RISE Capture
Interrupt Event
Latch
set
clear
HCICLR[RISE]
HCIFR[RISE]
Latch
set
clear
HCICLR[FALL]
HCIFR[FALL]
HCCTL[FALLINTE]
HCCTL[RISEINTE]
Counter Overflow
Event
Latch
set
clear
HCICLR[OVF]
HCIFR[OVF]
HCCTL[OVFINTE]
HCIFRC[RISE]
FALL Capture
Interrupt Event
HCIFRC[FALL]
HCIFRC[OVF]
Set RISOVF Flag To "1"
If RISE Flag Is "1" On
A New RISE Event
HCIFR[RISEOVF]
HCICLR[RISEOVF]
Figure 5-9. Interrupts in HRCAP Module
High-Resolution Capture (HRCAP) Module
412
TMS320x2806x Microcontrollers
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
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