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• Case 2: Normal serial port transmission. Transmission continues normally because the frame-synchronization

pulse is not unexpected. There are two possible reasons why a transmit operations might

not

be in progress

when the pulse occurs:

This FSX pulse is the first after the transmitter is enabled (XRST = 1).

The serial port is in the interpacket intervals. The programmed data delay for transmission (programmed with
the XDATDLY bits of XCR2) may start during these interpacket intervals before the first bit of the previous
word is transmitted. Thus, at maximum packet frequency, frame synchronization can still be received 0 to 2
clock cycles before the first bit of the synchronized frame.

• Case 3: Unexpected transmit frame synchronization with XFIG = 0 (frame-synchronization pulses not

ignored). Unexpected frame-synchronization pulses can originate from an external source or from the internal
sample rate generator.

If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
transmitted, this pulse is treated as an unexpected frame-synchronization pulse, and the transmitter sets
the transmit frame-synchronization error bit (XSYNCERR) in SPCR2. XSYNCERR can be cleared only by a
transmitter reset or by a write of 0 to this bit.

If you want the McBSP to notify the CPU of frame-synchronization errors, you can set a special transmit
interrupt mode with the XINTM bits of SPCR2. When XINTM = 11b, the McBSP sends a transmit interrupt
(XINT) request to the CPU each time that XSYNCERR is set.

15.4.5.2 Example of Unexpected Transmit Frame-Synchronization Pulse

shows an unexpected transmit frame-synchronization pulse during normal operation of the serial

port with intervals between the data packets. When the unexpected frame-synchronization pulse occurs, the
XSYNCERR bit is set and the transmission of data B is restarted because no new data has been passed to
XSR1 yet. In addition, if XINTM = 11b, the McBSP sends a transmit interrupt (XINT) request to the CPU.

Á

Á

Á

B0

B1

B2

B3

B4

B5

B6

B7

B4

B5

B6

B7

A0

A1

XSYNCERR

XRDY

DX

FSX

CLKX

Á

Á

Á

Á

Á

Á

Write to DXR1(D)

DXR1 to XSR1 (C)

Write to DXR1(C)

DXR1 to XSR1 copy(B)

Unexpected frame synchronization

Figure 15-30. An Unexpected Frame-Synchronization Pulse During a McBSP Transmission

15.4.5.3 Preventing Unexpected Transmit Frame-Synchronization Pulses

Each frame transfer can be delayed by 0, 1, or 2 CLKX cycles, depending on the value in the XDATDLY bits of
XCR2. For each possible data delay,

shows when a new frame-synchronization pulse on FSX can

safely occur relative to the last bit of the current frame.

Multichannel Buffered Serial Port (McBSP)

SPRUH18I – JANUARY 2011 – REVISED JUNE 2022

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Summary of Contents for TMS320 2806 Series

Page 1: ...TMS320x2806x Microcontrollers Technical Reference Manual Literature Number SPRUH18I JANUARY 2011 REVISED JUNE 2022...

Page 2: ......

Page 3: ...GPIO 107 1 4 1 GPIO Module Overview 107 1 4 2 Configuration Overview 113 1 4 3 Digital General Purpose I O Control 115 1 4 4 Input Qualification 116 1 4 5 GPIO and Peripheral Multiplexing MUX 120 1 4...

Page 4: ...Submodule Overview 242 3 1 3 Register Mapping 247 3 2 ePWM Submodules 249 3 2 1 Overview 249 3 2 2 Time Base TB Submodule 251 3 2 3 Counter Compare CC Submodule 260 3 2 4 Action Qualifier AQ Submodul...

Page 5: ...2 HRCAP Modes of Operation 408 5 3 3 HRCAP Interrupts 412 5 4 HRCAP Calibration Library 413 5 4 1 HRCAP Calibration Library Functions 414 5 4 2 HRCAP Calibration Library Software Usage 419 5 5 HRCAP R...

Page 6: ...compare Unit 476 7 6 eQEP Edge Capture Unit 478 7 7 eQEP Watchdog 482 7 8 eQEP Unit Timer Base 482 7 9 eQEP Interrupt Structure 483 7 10 eQEP Registers 483 7 10 1 eQEP Base Addresses 483 7 10 2 EQEP_...

Page 7: ...HDW Register 568 9 7 9 Ramp Generator Status RAMPSTS Register 568 10 Control Law Accelerator CLA 569 10 1 Introduction 570 10 1 1 Features 570 10 1 2 CLA Related Collateral 570 10 1 3 Block Diagram 57...

Page 8: ...sfer Step Size Register DST_TRANSFER_STEP EALLOW Protected 754 11 9 16 Source Destination Wrap Size Register SRC DST_WRAP_SIZE EALLOW protected 755 11 9 17 Source Destination Wrap Count Register SCR D...

Page 9: ...n Communication Modes 809 13 11 SCI Port Interrupts 810 13 12 SCI Baud Rate Calculations 810 13 13 SCI Enhanced Features 811 13 13 1 SCI FIFO Description 811 13 13 2 SCI Auto Baud 813 13 13 3 Autobaud...

Page 10: ...odes 909 15 6 SPI Operation Using the Clock Stop Mode 912 15 6 1 SPI Protocol 912 15 6 2 Clock Stop Mode 912 15 6 3 Bits Used to Enable and Configure the Clock Stop Mode 913 15 6 4 Clock Stop Mode Tim...

Page 11: ...54 15 10 Data Packing Examples 956 15 10 1 Data Packing Using Frame Length and Word Length 956 15 10 2 Data Packing Using Word Length and the Frame Synchronization Ignore Function 958 15 11 McBSP_REGS...

Page 12: ...e Register USBTEST offset 0x00F 1084 17 5 12 USB FIFO Endpoint n Register USBFIFO 0 USBFIFO 3 1086 17 5 13 USB Device Control Register USBDEVCTL offset 0x060 1087 17 5 14 USB Transmit Dynamic FIFO Siz...

Page 13: ...Select Register USBDMASEL offset 0x450 1137 18 Revision History 1139 List of Figures Figure 1 1 Flash Power Mode State Diagram 42 Figure 1 2 Flash Pipeline 44 Figure 1 3 Flash Configuration Access Fl...

Page 14: ...l GPACTRL Register 135 Figure 1 71 GPIO Port B Qualification Control GPBCTRL Register 136 Figure 1 72 GPIO A Control Register 2 Register GPACTRL2 137 Figure 1 73 GPIO Port A Qualification Select 1 GPA...

Page 15: ...ata Function 229 Figure 2 23 EEPROM Device at Address 0x50 230 Figure 2 24 Overview of I2C_Boot Function 231 Figure 2 25 Random Read 232 Figure 2 26 Sequential Read 232 Figure 2 27 Overview of eCAN A...

Page 16: ...ring 299 Figure 3 48 DCBEVT1 Event Triggering 300 Figure 3 49 DCBEVT2 Event Triggering 300 Figure 3 50 Event Filtering 301 Figure 3 51 Blanking Window Timing Diagram 302 Figure 3 52 Simplified ePWM Mo...

Page 17: ...70 Figure 3 110 Digital Compare Filter Control DCFCTL Register 371 Figure 3 111 Digital Compare Capture Control DCCAPCTL Register 372 Figure 3 112 Digital Compare Filter Offset DCFOFFSET Register 373...

Page 18: ...With Rising and Falling Edge Detect 443 Figure 6 14 Capture Sequence for Delta Mode Time stamp and Rising Edge Detect 444 Figure 6 15 Capture Sequence for Delta Mode Time stamp With Rising and Fallin...

Page 19: ...se 530 Figure 8 12 Timing Example for NONOVERLAP Mode 531 Figure 8 13 Temperature Sensor Transfer Function 532 Figure 8 14 ADC Control Register 1 ADCCTL1 535 Figure 8 15 ADC Control Register 2 ADCCTL2...

Page 20: ...Input Diagram 730 Figure 11 3 4 Stage Pipeline DMA Transfer 732 Figure 11 4 4 Stage Pipeline With One Read Stall McBSP as source 732 Figure 11 5 DMA State Diagram 738 Figure 11 6 Overrun Detection Lo...

Page 21: ...Communications Mode 809 Figure 13 10 SCI FIFO Interrupt Flags and Enable Logic 812 Figure 13 11 SCI Communications Control Register SCICCR 816 Figure 13 12 SCI Control Register 1 SCICTL1 818 Figure 13...

Page 22: ...17 Conceptual Block Diagram of the Sample Rate Generator 890 Figure 15 18 Possible Inputs to the Sample Rate Generator and the Polarity Bits 892 Figure 15 19 CLKG Synchronization and FSG Generation Wh...

Page 23: ...Data Words Transferred at Maximum Packet Frequency 958 Figure 15 64 Configuring the Data Stream of Figure 15 63 as a Continuous 32 Bit Word 958 Figure 15 65 DRR2 Register 961 Figure 15 66 DRR1 Registe...

Page 24: ...egister With DBO 1 CANMDL 1053 Figure 16 42 Message Data High Register With DBO 1 CANMDH 1053 Figure 17 1 USB Block Diagram 1056 Figure 17 2 USB Scheme 1057 Figure 17 3 Function Address Register USBFA...

Page 25: ...INTERVAL n 1124 Figure 17 55 USB Request Packet Count in Block Transfer Endpoint n Registers USBRQPKTCOUNT n 1125 Figure 17 56 USB Receive Double Packet Buffer Disable Register USBRXDPKTBUFDIS 1126 Fi...

Page 26: ...105 Table 1 51 TIMERxPRDH Register Field Descriptions 105 Table 1 52 TIMERxTCR Register Field Descriptions 106 Table 1 53 TIMERxTPR Register Field Descriptions 107 Table 1 54 TIMERxTPRH Register Field...

Page 27: ...e 162 Table 1 110 EALLOW Protected ePWM1 ePWM 7 Registers 162 Table 1 111 Device Emulation Registers 163 Table 1 112 DEVICECNF Register Field Descriptions 163 Table 1 113 PARTID Register Field Descrip...

Page 28: ...ble 3 28 Time Base Period High Resolution Mirror Register TBPRDHRM Field Descriptions 334 Table 3 29 Time Base Period Mirror Register TBPRDM Field Descriptions 335 Table 3 30 Counter Compare Control C...

Page 29: ...Descriptions 424 Table 5 5 HRCAP Interrupt Force Register HCIFRC Field Descriptions 425 Table 5 6 HRCAP Counter Register HCCOUNTER Field Descriptions 426 Table 5 7 HRCAP Capture Counter On Rising Edge...

Page 30: ...CFLG1 Field Descriptions 550 Table 8 17 ADC SOC Force 1 Register ADCSOCFRC1 Field Descriptions 551 Table 8 18 ADC SOC Overflow 1 Register ADCSOCOVF1 Field Descriptions 552 Table 8 19 ADC SOC Overflow...

Page 31: ...ield Descriptions 744 Table 11 7 Priority Status Register PRIORITYSTAT Field Descriptions 745 Table 11 8 Mode Register MODE Field Descriptions 746 Table 11 9 Control Register CONTROL Field Description...

Page 32: ...l SCIFFCT Register Field Descriptions 831 Table 13 20 SCI Priority Control SCIPRI Register Field Descriptions 832 Table 14 1 Dependency of Delay d on the Divide Down Value IPSC 838 Table 14 2 Operatin...

Page 33: ...de the Receive Frame Synchronization Signal and the Effect on the FSR Pin 931 Table 15 38 Register Bit Used to Set Receive Frame Synchronization Polarity 932 Table 15 39 Register Bits Used to Set the...

Page 34: ...H Register Field Descriptions 995 Table 15 102 XCERG Register Field Descriptions 996 Table 15 103 XCERH Register Field Descriptions 997 Table 15 104 MFFINT Register Field Descriptions 998 Table 16 1 M...

Page 35: ...eceive Dynamic FIFO Sizing Register USBRXFIFOSZ Field Descriptions 1090 Table 17 23 USB Transmit FIFO Start Address Register USBTXFIFOADDR Field Descriptions 1091 Table 17 24 USB Receive FIFO Start Ad...

Page 36: ...fer Endpoint n Registers USBRQPKTCOUNT n Field Descriptions 1125 Table 17 59 USB Receive Double Packet Buffer Disable Register USBRXDPKTBUFDIS Field Descriptions 1126 Table 17 60 USB Transmit Double P...

Page 37: ...one of multiple meanings Not implemented on the device Reserved for future device expansion Reserved for TI testing Reserved configurations of the device that are not supported Writing nondefault valu...

Page 38: ...are the property of their respective owners Read This First www ti com 38 TMS320x2806x Microcontrollers SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedback Copyright 2022 Texas Instrument...

Page 39: ...Interrupt sources both external and the peripheral interrupt expansion PIE block that multiplexes numerous interrupt sources into a smaller set of interrupt inputs For more information on the Viterbi...

Page 40: ...ccess to the flash by unauthorized persons See Section 1 2 for information on using the Code Security Module Low power modes To save power when the flash is not in use two levels of low power modes ar...

Page 41: ...Module CSM password locations located in the flash This read is performed to unlock a new or erased device that has no password stored in it so that flash programming or loading of code into CSM prote...

Page 42: ...forms 32 bit instruction fetch 16 bit or 32 bit data space read 16 bit program space read Once flash is in the active power state then a read or fetch access to the bank memory map area can be classif...

Page 43: ...resses makes up the majority of the application code and is referred to as linear code To improve the performance of linear code execution a flash pipeline mode has been implemented The flash pipeline...

Page 44: ...lize the pre fetch buffer capability and thus bypass the pre fetch buffer For example instructions such as MAC DMAC and PREAD read a data value from program memory When this read happens the pre fetch...

Page 45: ...ne before the return from function call is made Write instructions to FOPT FBANKWAIT etc The function that changes the configuration cannot execute from the Flash or OTP Branch or call is required to...

Page 46: ...default state Note The Flash configuration registers should not be written to by code that is running from OTP or Flash memory or while an access to Flash or OTP may be in progress All register access...

Page 47: ...e CSM See Section 1 2 for more information 3 When writing to this register follow the procedure described in Section 1 1 3 4 Figure 1 5 Flash Power Register FPWR 15 2 1 0 Reserved PWR R 0 R W 0 LEGEND...

Page 48: ...e Wait Counter Status Bit This bit indicates whether the respective wait counter is timing out an access 0 The counter is not counting 1 The counter is counting 2 STDBYWAITS Bank and Pump Sleep To Sta...

Page 49: ...ash Standby to Active Wait Counter Register FACTIVEWAIT 7 9 8 0 Reserved ACTIVEWAIT R 0 R W 0x1FF LEGEND R W Read Write R Read only n value after reset Table 1 6 Flash Standby to Active Wait Counter R...

Page 50: ...s to these bits must always have a value of 0 3 0 RANDWAIT Flash Random Read Wait States These register bits specify the number of wait states for a random read operation in CPU clock cycles 1 15 SYSC...

Page 51: ...an OTP access 00000 Illegal value OTPWAIT must be set to 1 or greater 00001 One wait state will be used each OTP access for a total of two SYSCLKOUT cycles per access 00010 Two wait states will be use...

Page 52: ...is run from nonsecure memory Security is protected by a password of 128 bits of data eight 16 bit words that is used to secure or unsecure the device This password is stored at the end of flash in 8...

Page 53: ...d that is secured the debug probe takes some time to take control of the CPU During this time the CPU will start running and may execute an instruction that performs an access to a protected ECSL area...

Page 54: ...ABOVE TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE IN NO EVENT SHAL...

Page 55: ...M Address Block 0x00 0000 0x00 03FF M0 SARAM 1K x 16 0x00 0400 0x00 07FF M1 SARAM 1K x16 0x00 0800 0x00 0CFF Peripheral Frame 0 2K x 16 0x00 0D00 0x00 0FFF PIE Vector RAM 256 x 16 0x00 6000 0x00 6FFF...

Page 56: ...ogic in new devices without any authorization since new devices come with an erased flash However reprogramming devices that already contain a custom password require the password to be supplied to th...

Page 57: ...manently secured CPU access is limited Device cannot be debugged or reprogrammed Do dummy read of PWL 0x3F 7FF8 0x3F 7FFF KEY registers all ones Correct password Are PWL all Fs Are PWL all zeros Devic...

Page 58: ...Hence the dummy reads to password location can be done only from RAM secure unsecure or Flash 2 Write the password into the KEY registers locations 0x00 0AE0 0x00 0AE7 in memory 3 If the password is c...

Page 59: ...es that stored in the PWL then the CSM will become unsecure If it does not match then the device will remain secure An example password of 0x11112222333344445555666677778888 is used asm EALLOW Key reg...

Page 60: ...eave either zeros or an unknown value in the password locations If the password locations are all zero during a reset the device will always be secure regardless of the contents of the KEY register Do...

Page 61: ...bit password 0x3F 7FFD PWL5 User defined Sixth word of the 128 bit password 0x3F 7FFE PWL6 User defined Seventh word of the 128 bit password 0x3F 7FFF PWL7 User defined High word of the 128 bit passwo...

Page 62: ...ePWM3 ePWM4 ePWM5 ePWM6 ePWM7 ePWM8 PF3 Peripheral Registers I2C A PF2 Peripheral Registers HRCAP1 HRCAP2 HRCAP3 HRCAP4 PF1 ADC Registers 12 Bit ADC 16 Ch PF2 PF0 COMP Registers COMP1 2 3 PF3 6 Analog...

Page 63: ...0x00 7034 1 PLL2 Lock Status Register SYSCLK2CNTR 0x00 7036 1 SYSCLK2 Clock Counter Register EPWMCFG 0x00 703A 1 ePWM DMA CLA Configuration Register 1 3 1 1 Enabling Disabling Clocks to the Periphera...

Page 64: ...le is clocked 3 ADCENCLK ADC clock enable 0 The ADC is not clocked default 1 1 The ADC module is clocked 2 TBCLKSYNC ePWM Module Time Base Clock TBCLK Sync Allows the user to globally synchronize all...

Page 65: ...lock SYSCLKOUT 9 ECAP2ENCLK eCAP2 clock enable 0 The eCAP2 module is not clocked default 2 1 The eCAP2 module is clocked by the system clock SYSCLKOUT 8 ECAP1ENCLK eCAP1 clock enable 0 The eCAP1 modul...

Page 66: ...M1 clock enable 3 0 The ePWM1 module is not clocked default 2 1 The ePWM1 module is clocked by the system clock SYSCLKOUT 1 This register is EALLOW protected See Section 1 5 2 for more information 2 I...

Page 67: ...The HRCAP4 module is clocked 10 HRCAP3ENCLK 0 The HRCAP3 module is not clocked default 1 1 The HRCAP3 module is clocked 9 HRCAP2ENCLK 0 The HRCAP2 module is not clocked default 1 1 The HRCAP2 module...

Page 68: ...MA module clock enable 0 DMA is not clocked 1 DMA is clocked 10 CPUTIMER2ENCLK CPU Timer 2 Clock Enable 0 The CPU Timer 2 is not clocked 1 The CPU Timer 2 is clocked 9 CPUTIMER1ENCLK CPU Timer 1 Clock...

Page 69: ...ed no external components It also has an on chip PLL based clock module Figure 1 19 shows the different options that are available to clock the device Following are the input clock options available I...

Page 70: ...LK 0 1 CLKCTL WDCLKSRCSEL OSC1CLK on reset XRS CLKCTL OSCCLKSRCSEL SYSCLKOUT CLKCTL TMR2CLKSRCSEL OSCCLKSRC2 11 Prescale 1 2 4 8 16 CLKCTL TRM2CLKPRESCALE DEVICECNF SYSCLK2DIV2DIS 00 01 10 11 CPUTMR2C...

Page 71: ...ot time the boot ROM copies this value to the above registers 1 3 2 1 2 Device_Cal The device calibration routine Device_cal is programmed into TI reserved memory by the factory The boot ROM automatic...

Page 72: ...escription 1 15 7 Reserved Any writes to these bits must always have a value of 0 6 XCLKINSEL XCLKIN Source Select Bit This bit selects the source 0 GPIO38 is XCLKIN input source this is also the JTAG...

Page 73: ...ster description for more details XTALOSCOFF must be set to 1 if XCLKIN is used 12 WDHALTI Watchdog HALT Mode Ignore bit This bit selects if the watchdog is automatically turned off by the HALT mode o...

Page 74: ...CSEL CPU Timer 2 Clock Source Select bit This bit selects the source for CPU Timer 2 00 SYSCLKOUT selected default on reset pre scaler is bypassed 01 External oscillator selected at XOR output 10 Inte...

Page 75: ...C2 is selected as the clock source and a missing clock is detected the missing clock detect circuit will automatically switch to Internal Oscillator 1 OSCCLKSRC1 and generate a CLOCKFAIL signal In add...

Page 76: ...locks to a new frequency after the PLLCR register has been modified In this mode the PLL itself is bypassed but the PLL is not turned off 0 1 2 3 OSCCLK 4 OSCCLK 2 OSCCLK 1 PLL Enabled Achieved by wri...

Page 77: ...Is PLLSTS PLLLOCKS 1 Continue to wait for PLL to lock This is important for time critical software Set PLLSTS MCLKOFF 1 to disable failed oscillator detect logic No Yes PLLSTS DIVSEL 2 or 3 No Set PL...

Page 78: ...CLK 6 2 OSCCLK 6 1 00111 OSCCLK 7 4 OSCCLK 7 2 OSCCLK 7 1 01000 OSCCLK 8 4 OSCCLK 8 2 OSCCLK 8 1 01001 OSCCLK 9 4 OSCCLK 9 2 OSCCLK 9 1 01010 OSCCLK 10 4 OSCCLK 10 2 OSCCLK 10 1 01011 OSCCLK 11 4 OSCC...

Page 79: ...fail detect logic is enabled default 1 Main oscillator fail detect logic is disabled and the PLL will not issue a limp mode clock Use this mode when code must not be affected by the detection circuit...

Page 80: ...the PLL This is useful for system noise testing This mode must only be used when the PLLCR register is set to 0x0000 0 PLL On default 1 PLL Off While the PLLOFF bit is set the PLL module will be kept...

Page 81: ...time can be programmed by user The user needs to compute the number of OSCCLK cycles based on the OSCCLK value used in the design and update this register PLL Lock Period FFFFh 65535 OSCLK Cycles def...

Page 82: ...e as decided by the PLL2CLKSRCSEL bit 1 PLL2 is enabled and clock to SYSCLK2 will depend on the DEVICECNF SYSCLK2DIV2DIS bit 1 0 PLL2CLKSRCSEL PLL2 Clock Source Select Bits These bit select the source...

Page 83: ...on 1 3 2 4 1 4 3 PLL2 Lock Status PLL2STS Register Note PLL2STS is affected by XRSn signal only Figure 1 31 PLL2 Lock Status PLL2STS Register 15 1 0 Reserved PLL2LOCKS R 0 R 0x0 LEGEND R W Read Write...

Page 84: ...ble to the DMA bus 1 The EPWM blocks are connected to the DMA bus and are inaccessible to the CLA bus 1 3 2 5 Input Clock Fail Detection It is possible for the clock source of the device to fail When...

Page 85: ...e CLKIN DIVSEL 4 on reset MCLKOFF turn off when 1 Low Power Modes Block WAKEOSC HALT STANDBY WAKEINT LPMINT WD Block WDINT WDRST WDHALT OSCCLK 0 1 PIE VREG VREGHALT NMI WD NMIRS NMI CLOCKFAIL WAKEOSC...

Page 86: ...n case A reset is inevitable and cannot be delayed In case B the software can Choose to clear the flags to prevent a reset Perform a graceful shutdown of the system Switch to OSCCLKSRC2 if need be Cas...

Page 87: ...ALT low power mode when the device is operating in limp mode If you try to enter HALT mode when the device is already operating in limp mode then the device may not properly enter HALT The device may...

Page 88: ...itch to an alternate clock source if applicable If this is not done the NMIWDCTR overflows and generates an NMI reset NMIRS after a preprogrammed number of SYSCLKOUT cycles NMIRS is fed to MCLKRS to g...

Page 89: ...1 0 Reserved CLOCKFAIL Reserved R 0 R W 0 R 0 LEGEND R Read only W Write only n value after reset Table 1 33 NMI Configuration NMICFG Register Bit Definitions EALLOW Bits Name Type Description 15 2 R...

Page 90: ...s flag 1 The NMIFLG register is only reset by the XRS signal not SYSRS 1 3 2 7 1 3 NMI Flag Clear NMIFLGCLR Register Figure 1 38 NMI Flag Clear NMIFLGCLR Register 15 2 1 0 Reserved CLOCKFAIL NMIINT R...

Page 91: ...er Bit Definitions Bits Name Type Description 15 0 NMIWDCNT NMI Watchdog Counter This 16 bit incremental counter will start incrementing whenever any one of the enabled FAIL flags are set If the count...

Page 92: ...n from 0 After the overflow once the COUNTER value equals the new PERIOD value an NMIRS is forced which resets the watchdog counter 1 3 2 7 2 NMI Watchdog Emulation Considerations The NMI watchdog mod...

Page 93: ...operating range 1 3 3 Low Power Modes Block Table 1 39 summarizes the various modes The various low power modes operate as shown in Table 1 40 Refer to the device data sheet for exact timing for enter...

Page 94: ...pt in the PIE module PIEIER1 8 1 This interrupt is connected to both the watchdog and the Low Power Mode module interrupt Specify one of the GPIO port A signals to wake the device in the GPIOLPMSEL re...

Page 95: ...00 Set the low power mode to IDLE default 01 Set the low power mode to STANDBY 10 Set the low power mode to HALT 11 Set the low power mode to HALT 1 The low power mode bits LPM only take effect when...

Page 96: ...the watchdog counter Figure 1 44 shows the various functional blocks within the watchdog module A The WDRST and XRS signals are driven low for 512 OSCCLK cycles when a watchdog reset occurs Likewise i...

Page 97: ...er enabled to be reset and the 0xAA in step 12 now has no effect If the watchdog is configured to reset the device then a WDCR overflow or writing the incorrect value to the WDCR WDCHK bits will reset...

Page 98: ...WDINT signal will be held low for 512 OSCCLK cycles when the watchdog interrupt is generated You can determine the current state of WDINT by reading the watchdog interrupt status bit WDINTS bit in th...

Page 99: ...e default state on reset XRS When the watchdog interrupt occurs the WDRST signal will stay low for 512 OSCCLK cycles If the WDENINT bit is cleared while WDINT is low a reset will immediately occur The...

Page 100: ...rved WDKEY R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 45 Watchdog Reset Key Register WDKEY Field Descriptions Bits Field Value Description 1 15 8 Reserved Any writes to th...

Page 101: ...hen watchdog module is disabled Do not write to WDCHK bits when the watchdog module is disabled These bits can be used to generate a software reset of the device These three bits always read back as z...

Page 102: ...INT 16 bit timer divide down TDDRH TDDR 32 bit timer period PRDH PRD 32 bit counter TIMH TIM 16 bit prescale counter PSCH PSC Borrow Figure 1 49 CPU Timers INT1 to INT12 INT14 28x CPU TINT2 TINT0 PIE...

Page 103: ...1 CPU Timer 0 Prescale Register High Figure 1 57 TIMER1TIM 0x0C08 1 CPU Timer 1 Counter Register Figure 1 51 TIMER1TIMH 0x0C09 1 CPU Timer 1 Counter Register High Figure 1 52 TIMER1PRD 0x0C0A 1 CPU T...

Page 104: ...ycles where TDDRH TDDR is the timer prescale divide down value When the TIMH TIM decrements to zero the TIMH TIM register is reloaded with the period value contained in the PRDH PRD registers The time...

Page 105: ...contents are also loaded into the TIMH TIM when you set the timer reload bit TRB in the Timer Control Register TCR Figure 1 54 TIMERxPRDH Register x 0 1 2 15 0 PRDH R W 0 LEGEND R W Read Write R Read...

Page 106: ...cremented to zero FREE SOFT CPU Timer Emulation Mode 0 0 Stop after the next decrement of the TIMH TIM hard stop 0 1 Stop after the TIMH TIM decrements to 0 soft stop 1 0 Free run 1 1 Free run In the...

Page 107: ...ds the PSCH PSC whenever the timer reload bit TRB is set by software Figure 1 57 TIMERxTPRH Register x 0 1 2 15 8 7 0 PSCH TDDRH R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1...

Page 108: ...T default on reset 3 samples 6 samples 00 00 XRS default on reset 01 11 10 00 01 11 10 00 0 input 1 output GPIO XINT1SEL GPIO XINT2SEL GPIO XINT3SEL External interrupt MUX PIE GPADAT read GPIOLPMSEL L...

Page 109: ...S Default at Reset GPBDAT read 01 Perpheral 1 output 11 10 Peripheral 2 output Peripheral 3 output 00 01 11 10 Peripheral 2 output enable Peripheral 3 output enable 00 SDAA SCLA I2C output enable SDAA...

Page 110: ...nction Any circuitry connected to these pins should not prevent the debug probe from driving or being driven by the JTAG pins for successful debug TRST 1 0 C28x Core TCK GPIO38 TCK XCLKIN GPIO38_in GP...

Page 111: ...Read only n value after reset Table 1 55 JTAGDEBUG Register Field Descriptions Bits Field Value Description 15 1 Reserved Any writes to these bits must always have a value of 0 0 JTAGDIS JTAG Port Di...

Page 112: ...CLKOUT Logic implemented in GPIO MUX block AIODAT Reg Read AIODAT Reg Latch AIOSET AIOCLEAR AIOTOGGLE Regs AIOMUX1 Reg 1 0 AIOxDIR 1 Input 0 Output 0 Input 1 Output AIODIR Reg Latch 0 A The ADC Compar...

Page 113: ...O15 Figure 1 69 AIODIR 0x6FBA 2 Analog I O Direction Register AIO0 AIO15 Figure 1 79 1 The registers in this table are EALLOW protected See Section 1 5 2 for more information Table 1 57 GPIO Interrupt...

Page 114: ...lue to the GPxCLEAR GPxSET or GPxTOGGLE or AIOCLEAR AIOSET or AIOTOGGLE registers Once the output latch is loaded change the pin direction from input to output via the GPxDIR registers The output latc...

Page 115: ...ed value be driven onto the pin When using the GPxDAT register to change the level of an output pin you should be cautious not to accidentally change the level of another pin For example if you mean t...

Page 116: ...the output pin is driven low then writing a 1 to the corresponding bit in the toggle register will pull the pin high Likewise if the output pin is high then writing a 1 to the corresponding bit in th...

Page 117: ...ime duration between samples or how often the signal will be sampled relative to the CPU clock SYSCLKOUT The sampling period is specified by the qualification period QUALPRDn bits in the GPxCTRL regis...

Page 118: ...indow can be determined For the input qualifier to detect a change in the input the level of the signal must be stable for the duration of the sampling window width or longer The number of sampling pe...

Page 119: ...re 1 64 the glitch A is shorter then the qualification window and will be ignored by the input qualifier GPIO Signal 1 Sampling Window Output From Qualifier 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 S...

Page 120: ...s have different multiplexing schemes If a peripheral is not available on a particular device that MUX selection is reserved on that device and should not be used Note If you should select a reserved...

Page 121: ...in master out 1 SPISOMIA SPISOMIB SPI A Slave out master in 1 SCIRXDA SCIRXDB SCI A SCI B receive 1 CANRXA eCAN A receive 1 SDAA I2C data 1 SCLA1 I2C clock 1 1 This value will be assigned to the peri...

Page 122: ...served TZ2 I 3 2 GPIO17 SPISOMIA I O Reserved TZ3 I 5 4 GPIO18 SPICLKA I O SCITXDB 3 O XCLKOUT O 7 6 GPIO19 XCLKIN SPISTEA I O SCIRXDB 3 I ECAP1 I O 9 8 GPIO20 EQEP1A I MDXA O COMP1OUT O 11 10 GPIO21...

Page 123: ...eserved Reserved Reserved Reserved 3 2 Reserved Reserved Reserved Reserved 5 4 GPIO50 3 EQEP1A I MDXA O TZ1 I 7 6 GPIO51 3 EQEP1B I MDRA I TZ2 I 9 8 GPIO52 3 EQEP1S I O MCLKXA I O TZ3 I 11 10 GPIO53 3...

Page 124: ...1 20 19 18 17 16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 G...

Page 125: ...WM6 output A O 10 Reserved 11 ADCSOCBO ADC Start of conversion B O 19 18 GPIO9 Configure the GPIO9 pin as 00 GPIO9 General purpose I O 9 default I O 01 EPWM5B ePWM5 output B 10 SCITXDB O 11 ECAP3 I O...

Page 126: ...ator 2 output 5 4 GPIO2 Configure the GPIO2 pin as 00 GPIO2 I O General purpose I O 2 default I O 01 EPWM2A ePWM2 output A O 10 Reserved 11 Reserved 3 2 GPIO1 Configure the GPIO1 pin as 00 GPIO1 Gener...

Page 127: ...t I O 01 CANRXA eCAN A receive I 10 EQEP2I I O 11 EPWM7A O 27 26 GPIO29 Configure the GPIO29 pin as 00 GPIO29 I O General purpose I O 29 default I O 01 SCITXDA SCI A transmit O 10 SCLA I2C clock open...

Page 128: ...PIO21 General purpose I O 21 default I O 01 EQEP1B eQEP1 input B I 10 MDRA I 11 COMP2OUT O Comparator 2 output 9 8 GPIO20 Configure the GPIO20 pin as 00 GPIO20 General purpose I O 20 default I O 01 EQ...

Page 129: ...the GPIO16 pin as 00 GPIO16 General purpose I O 16 default I O 01 SPISIMOA SPI A slave in master out I O 10 Reserved 11 TZ2 Trip zone 2 I www ti com System Control and Interrupts SPRUH18I JANUARY 201...

Page 130: ...O 23 22 GPIO43 Configure this pin as 00 GPIO43 general purpose I O 43 default 01 EPWM8B O 10 TZ2 I 11 COMP2OUT O Comparator 2 output 21 20 GPIO42 Configure this pin as 00 GPIO42 general purpose I O 4...

Page 131: ...e this pin as 00 GPIO35 general purpose I O 35 default If TRST 1 JTAG TDI function is chosen for this pin 01 Reserved 10 or 11 Reserved 5 4 GPIO34 Configure this pin as 00 GPIO34 general purpose I O 3...

Page 132: ...WM7A O 19 18 GPIO57 Configure this pin as 00 GPIO57 general purpose I O 57 default 01 SPISTEA I O 10 EQEP2S I O 11 HRCAP4 I 17 16 GPIO56 Configure this pin as 00 GPIO56 general purpose I O 56 default...

Page 133: ...pin as 00 GPIO51 general purpose I O 51 default 01 EQEP1B I 10 MDRA I 11 TZ2 I 5 4 GPIO50 Configure this pin as 00 GPIO50 general purpose I O 50 default 01 EQEP1A I 10 MDXA O 11 TZ1 I 3 0 Reserved An...

Page 134: ...25 24 AIO12 00 or 01 AIO12 enabled 10 or 11 AIO12 disabled default 23 22 Reserved Any writes to these bits must always have a value of 0 21 20 AIO10 00 or 01 AIO10 enabled 10 or 11 AIO10 disabled def...

Page 135: ...riod 2 TSYSCLKOUT 0x02 Sampling Period 4 TSYSCLKOUT 0xFF Sampling Period 510 TSYSCLKOUT 23 16 QUALPRD2 Specifies the sampling period for pins GPIO16 to GPIO23 0x00 Sampling Period TSYSCLKOUT 1 0x01 Sa...

Page 136: ...iod TSYSCLKOUT 1 0x01 Sampling Period 2 TSYSCLKOUT 0x02 Sampling Period 4 TSYSCLKOUT 0xFF Sampling Period 510 TSYSCLKOUT 15 8 QUALPRD1 Specifies the sampling period for pins GPIO40 to GPIO44 0xFF Samp...

Page 137: ...ption 31 1 Reserved Any writes to these bits must always have a value of 0 0 USBIOEN USB I O Enable Bit 0 USB0DP and USB0DM pins are controlled by GPIO Mux register settings USBPHY is powered down 1 U...

Page 138: ...controlled by two bits as shown in Figure 1 73 00 Synchronize to SYSCLKOUT only Valid for both peripheral and GPIO pins 01 Qualification using 3 samples Valid for pins configured as GPIO or a periphe...

Page 139: ...put is controlled by two bits as shown in Figure 1 74 00 Synchronize to SYSCLKOUT only Valid for both peripheral and GPIO pins 01 Qualification using 3 samples Valid for pins configured as GPIO or a p...

Page 140: ...n of each GPIO input is controlled by two bits as shown in Figure 1 75 00 Synchronize to SYSCLKOUT only Valid for both peripheral and GPIO pins 01 Qualification using 3 samples Valid for pins configur...

Page 141: ...trolled by two bits as shown in Figure 1 76 00 Synchronize to SYSCLKOUT only Valid for both peripheral and GPIO pins 01 Qualification using 3 samples Valid for pins configured as GPIO or a peripheral...

Page 142: ...GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 79 GPIO Port A Direction GPADIR Register Field...

Page 143: ...ion 31 27 Reserved Any writes to these bits must always have a value of 0 26 18 GPIO58 GPIO50 Controls direction of GPIO pin when GPIO mode is selected Reading the register returns the current value o...

Page 144: ...AIODIR Register Field Descriptions Bit Field Value Description 31 15 Reserved Any writes to these bits must always have a value of 0 14 0 AIOn Controls direction of the available AIO pin when AIO mode...

Page 145: ...18 17 16 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 R W 0 R W 0...

Page 146: ...O pin corresponds to one bit in this register 0 Enable the internal pullup on the specified pin default for GPIO58 GPIO50 1 Disable the internal pullup on the specified pin 17 13 Reserved Any writes t...

Page 147: ...R W x R W x R W x R W x R W x R W x R W x R W x 7 6 5 4 3 2 1 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R W x R W x R W x R W x R W x R W x R W x R W x LEGEND R W Read Write R Read only n val...

Page 148: ...he pin 1 Reading a 1 indicates that the state of the pin is currently high irrespective of the mode the pin is configured for Writing a 1 will force an output of 1 if the pin is configured as a GPIO o...

Page 149: ...0 indicates that the state of the pin is currently low irrespective of the mode the pin is configured for Writing a 0 will force an output of 0 if the pin is configured as a AIO output in the appropr...

Page 150: ...er as shown in Figure 1 85 0 Writes of 0 are ignored This register always reads back a 0 1 Writing a 1 forces the respective output data latch to high If the pin is configured as a GPIO output then it...

Page 151: ...iting a 1 forces the respective output data latch to toggle from its current state If the pin is configured as a GPIO output then it will be driven in the opposite direction of its current state If th...

Page 152: ...egister as shown in Figure 1 86 0 Writes of 0 are ignored This register always reads back a 0 1 Writing a 1 forces the respective output data latch to high If the pin is configured as a GPIO output th...

Page 153: ...tions Bits Field Value Description 31 27 Reserved Any writes to these bits must always have a value of 0 26 18 GPIO58 GPIO50 Each GPIO port B pin GPIO58 GPIO50 corresponds to one bit in this register...

Page 154: ...rites to these bits must always have a value of 0 14 0 AIOn Each AIO pin corresponds to one bit in this register 0 Writes of 0 are ignored This register always reads back a 0 1 Writing a 1 forces the...

Page 155: ...use XINT2 as ADC start of conversion enable it in the desired ADCSOCxCTL register The ADCSOC signal is always rising edge sensitive 00000 Select the GPIO0 pin as the XINTn interrupt source default 000...

Page 156: ...GEND R W Read Write R Read only n value after reset Table 1 98 GPIO Low Power Mode Wakeup Select GPIOLPMSEL Register Field Descriptions Bits Field Value Description 31 0 GPIO31 GPIO0 Low Power Mode Wa...

Page 157: ...gisters 3 0x00 0A80 0x00 0ADF 96 Yes Code Security Module Registers 0x00 0AE0 0x00 0AEF 16 Yes ADC registers 0 wait read only 0x00 0B00 0x00 0B0F 16 No CPU TIMER0 1 2 Registers 0x00 0C00 0x00 0C3F 64...

Page 158: ...registers 0x00 6F80 0x00 6FFF 128 3 1 Back to back write operations to Peripheral Frame 1 registers will incur a 1 cycle stall 1 cycle delay 2 Peripheral Frame 1 allows 16 bit and 32 bit accesses All...

Page 159: ...After modifying registers they can once again be protected by executing the EDI instruction to clear the EALLOW bit The following registers are EALLOW protected Device Emulation Registers Flash Regis...

Page 160: ...ter INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register PCLKCR2 0x00 7019 1 Peripheral Clock Control Register 2 LOSPCP 0x00 701B 1 L...

Page 161: ...ister AIOMUX1 0x6FB6 2 Analog I O MUX 1 register AIODIR 0x6FBA 2 Analog IO Direction Register GPIOXINT1SEL 0x6FE0 1 XINT1 Source Select Register GPIO0 GPIO31 GPIOXINT2SEL 0x6FE1 1 XINT2 Source Select...

Page 162: ...rupt Vectors Group 2 Interrupt Vectors to Group 11 Interrupt Vectors INT12 1 INT12 8 0x0DF0 0x0DFE 2 2 Group 12 Interrupt Vectors Table 1 110 EALLOW Protected ePWM1 ePWM 7 Registers TZSEL TZCTL TZEINT...

Page 163: ...rites to these bits must always have a value of 0 30 SYSCLK2DIV2DIS SYSCLK2 Clock Divide by 2 Disable Bit 0 PLL2 Output 2 1 PLL2 Output 1 29 28 Reserved 27 TRST Read status of TRST signal Reading this...

Page 164: ...FP PN 0x9C TMS320F28069UPFP PN 0x9D TMS320F28068PZP PZ 0x8E TMS320F28068UPZP PZ 0x8F TMS320F28068PFP PN 0x8C TMS320F28068UPFP PN 0x8D TMS320F28067PZP PZ 0x8A TMS320F28067UPZP PZ 0x8B TMS320F28067PFP P...

Page 165: ...Write R Read only n value after reset Table 1 115 REVID Register Field Descriptions Bits Field Value Description 15 0 REVID 1 These 16 bits specify the silicon revision number for the particular part...

Page 166: ...location and then the next instruction performs a read from Register 2 REG2 location On the processor memory bus with block protection disabled the read operation is issued before the write as shown M...

Page 167: ...ts at the peripheral level Because the CPU does not have sufficient capacity to handle all peripheral interrupt requests at the CPU level a centralized peripheral interrupt expansion PIE controller is...

Page 168: ...gister PIEIFRx and enable PIEIERx register x PIE group 1 PIE group 12 Each bit referred to as y corresponds to one of the 8 MUXed interrupts within the group Thus PIEIFRx y and PIEIERx y correspond to...

Page 169: ...led then the highest priority interrupt within the group INTx 1 where x is the PIE group is used See Section 1 6 3 3 for details Figure 1 94 Typical PIE CPU Interrupt Response INTx y As shown in Table...

Page 170: ...served for TI testing only ENPIE ENPIE is found in the PIECTRL Register bit 0 The default value of this bit on reset is set to 0 PIE disabled The state of this bit can be modified after reset by writi...

Page 171: ...for reset are fetched from M0 vector map Vectors Used for test purposes only No PIE vector table PIEIERx registers VMAP 1 MOM1MAP 1 except for reset are fetched from BROM vector map A The compatibilit...

Page 172: ...t Control XINT3 XINT3CR 15 0 System Control See the System Control section INT14 INT13 GPIO0 int GPIO31 int DMA clear DMA PIE Up to 96 Interrupts DMA DMA TOUT1 CPU TIMER 2 CPU TIMER 0 TINT0 CPU TIMER...

Page 173: ...ISR will only perform a return from interrupt IRET operation 3 Enable the interrupt so that the interrupt will be serviced by the temporary ISR 4 After the temporary interrupt routine is serviced the...

Page 174: ...group This is a safe operation on the CPU IFR register 5 Clear the PIEACKx bit for the peripheral group 6 Enable global interrupts INTM 0 Method 2 Use the PIEIERx register to disable the interrupt an...

Page 175: ...request is sent to the CPU and the acknowledge bit is again set PIEACKx 1 The PIEACKx bit will remain set until you clear it to indicate that additional interrupts from the group can be sent from the...

Page 176: ...interrupt processing When the PIE is enabled a TRAP 1 through TRAP 12 or an INTR INT1 to INTR INT12 instruction transfers program control to the interrupt service routine corresponding to the first ve...

Page 177: ...SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA McBSP A McBSP A SPI B SPI B SPI A SPI A 0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90 INT7 y Reserved Reserved DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1...

Page 178: ...me OS Interrupt 4 EMUINT 17 0x0000 0D22 2 CPU Emulation Interrupt 2 NMI 18 0x0000 0D24 2 External Non Maskable Interrupt 3 ILLEGAL 19 0x0000 0D26 2 Illegal Operation USER1 20 0x0000 0D28 2 User Define...

Page 179: ...0x0000 0D72 2 ECAP2_INT ECAP2 8 2 INT4 3 58 0x0000 0D74 2 ECAP3_INT ECAP3 8 3 INT4 4 59 0x0000 0D76 2 Reserved 8 4 INT4 5 60 0x0000 0D78 2 Reserved 8 5 INT4 6 61 0x0000 0D7A 2 Reserved 8 6 INT4 7 62...

Page 180: ...SCI B 13 3 INT9 4 99 0x0000 0DC6 2 SCITXINTB SCI B 13 4 INT9 5 100 0x0000 0DC8 2 ECANAINT0 CAN A 13 5 INT9 6 101 0x0000 0DCA 2 ECANAINT1 CAN A 13 6 INT9 7 102 0x0000 0DCC 2 Reserved 13 7 INT9 8 103 0...

Page 181: ...2 0x0000 0CE5 1 PIE INT2 Group Flag Register PIEIER3 0x0000 0CE6 1 PIE INT3 Group Enable Register PIEIFR3 0x0000 0CE7 1 PIE INT3 Group Flag Register PIEIER4 0x0000 0CE8 1 PIE INT4 Group Enable Registe...

Page 182: ...or reset are fetched from the PIE vector table The reset vector is always fetched from the boot ROM Figure 1 99 PIE Interrupt Acknowledge Register PIEACK Register Address 0xCE1 15 12 11 0 Reserved PIE...

Page 183: ...8 These register bits indicate whether an interrupt is currently active They behave very much like the CPU interrupt flag register When an interrupt is active the respective register bit is set The b...

Page 184: ...only n value after reset Table 1 125 PIEIERx Register x 1 to 12 Field Descriptions Bits Field Description 15 8 Reserved Reserved 7 INTx 8 These register bits individually enable an interrupt within a...

Page 185: ...write a zero to it not a one 2 When a maskable interrupt is acknowledged only the IFR bit is cleared automatically The flag bit in the corresponding peripheral control register is not cleared If an ap...

Page 186: ...this bit to clear it to 0 and clear the interrupt request 9 INT10 Interrupt 10 flag INT10 is the flag for interrupts connected to CPU interrupt level INT10 0 No INT10 interrupt is pending 1 At least o...

Page 187: ...0 to this bit to clear it to 0 and clear the interrupt request 1 INT2 Interrupt 2 flag INT2 is the flag for interrupts connected to CPU interrupt level INT2 0 No INT2 interrupt is pending 1 At least o...

Page 188: ...interrupt service routine At reset all the IER bits are cleared to 0 disabling all maskable CPU level interrupts The IER register is shown in Figure 1 103 and descriptions of the bits follow the figur...

Page 189: ...enabled 5 INT6 Interrupt 6 enable INT6 enables or disables CPU interrupt level INT6 0 Level INT6 is disabled 1 Level INT6 is enabled 4 INT5 Interrupt 5 enable INT5 enables or disables CPU interrupt le...

Page 190: ...0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 128 Debug Interrupt Enable Register DBGIER CPU Register Field Descriptions Bits Field Value Description 15 RTOSINT Real time...

Page 191: ...abled 4 INT5 Interrupt 5 enable INT5 enables or disables CPU interrupt level INT5 0 Level INT5 is disabled 1 Level INT5 is enabled 3 INT4 Interrupt 4 enable INT4 enables or disables CPU interrupt leve...

Page 192: ...R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 130 External Interrupt n Control Register XINTnCR Field Descriptions Bits Field Value Description 15 4 Reserved Reads return ze...

Page 193: ...p Voltage Regulator VREG An on chip voltage regulator facilitates the powering of the device without adding the cost or board space of a second external regulator This linear regulator generates the c...

Page 194: ...he various trip points as well as the delay time from the removal of the fault condition to enable the BOR function to the release of the XRS pin A bit is provided in the BORCFG register address 0x985...

Page 195: ...ne This chapter descibes the purpose and features of the bootloader as well as other contents of the device on chip boot ROM and identifies where all of the information is located within that memory T...

Page 196: ...Flash API library Figure 2 1 and Figure 2 2 show the memory map of the on chip boot ROM This will vary between F2806x parts and F2806xF and F2806M parts The memory block is 32Kx16 in size and is locat...

Page 197: ...Vector Table 0x3F FFFF 0x3F FFC0 0x3FFFBA 0x3FFEB9 0x3F F7D2 0x3F E780 0x3F E80C 0x3F F3B0 0x3F DC30 0x3F D590 0x3F 8000 Section Start Address FAST SPIN libraries 0x3F E8B6 Figure 2 2 F2806xM 2806xF M...

Page 198: ...gle precision Floating point Table size 20 words Contents 32 bit coefficients for calculating exp X using a Taylor series Example 2 1 Linker Command File to Access FPU Tables MEMORY PAGE 0 FPUTABLES o...

Page 199: ...nverse Table IQ Math Table Table size 528 words Q format Q29 Contents 32 bit normalized inverse samples plus saturation limits This table is used as an initial estimate in the Newton Raphson inverse a...

Page 200: ...th Library documentation for more information 2 1 3 On Chip Flash API The boot ROM contains the API to program and erase the flash This flash API can be accessed using the boot ROM flash API symbol li...

Page 201: ...tions to catch any vectors fetched from boot ROM This is not required for normal device operation Table 2 1 Vector Locations Vector Location in Boot ROM Contents points to Vector Location in Boot ROM...

Page 202: ...debugger is connected Debugger Boot Debugger is connected and TRST 1 In debugger boot the boot ROM checks two SARAM locations called EMU_KEY and EMU_BMODE for a boot mode If the contents of either loc...

Page 203: ...lly therefore at reset M0M1MAP is always configured for C28x mode 2 2 3 PLL Multiplier and DIVSEL Selection The Boot ROM changes the PLL multiplier PLLCR and divider PLLSTS DIVSEL bits as follows All...

Page 204: ...IE Configuration The boot modes do not enable the PIE It is left in its default state which is disabled The boot ROM does however use the first six locations within the PIE vector table for emulation...

Page 205: ...in the OTP as shown in Table 2 6 In addition if these locations are used by an application then GetMode will jump to flash as long as OTP_KEY 0x005A and or OTP_BMODE is not a valid value This device...

Page 206: ...Y and OTP_BMODE to determine what Boot Mode is desired No Call Boot Loader Yes Call Boot Loader SCI SPI I2C CAN or Parallel I O Read EntryPoint and load the data EntryPoint determined directly by the...

Page 207: ...boot mode table Following are two examples of an emulation boot Example 2 3 Debug an application that loads through the SCI at boot To debug an application that loads through the SCI at boot follow th...

Page 208: ...tate of the boot mode pins if a debug probe is not connected Wait This devices does not support the hardware wait in reset mode that is available on other C2000 parts The wait boot mode can be used to...

Page 209: ...y module CSM password locations You are required to have previously programmed a branch instruction at location 0x3F 7FF6 that will redirect code execution to either a custom boot loader or the applic...

Page 210: ...le 2 7 Emulation Boot Modes TRST 1 TRST GPIO37 TDO GPIO34 EMU KEY EMU BMODE OTP KEY OTP BMODE Boot Mode Selected 1 EMU KEY EMU BMODE Read from 0x0D00 Read from 0x0D01 Read from 0x3D7BFB Read from 0x3D...

Page 211: ...tion data During normal operation this process occurs automatically and no action is required by the user If the boot ROM is bypassed by the Code Composer Studio IDE during the development process the...

Page 212: ...SPI and I2C and parallel bootloaders use these words to initialize registers The tenth and eleventh words comprise the 22 bit entry point address This address is used to initialize the PC after the b...

Page 213: ...ram Otherwise another section follows 13 Destination address of first block Address 31 16 14 Destination address of first block Address 15 0 15 First word of the first block in the source being loaded...

Page 214: ...ndicates end of data stream After load has completed the following memory values will have been initialized as follows Location Value 0x3F9010 0x0001 0x3F9011 0x0002 0x3F9012 0x0003 0x3F9013 0x0004 0x...

Page 215: ...on address first block Addr 7 0 MSB LSW destination address first block Addr 15 8 29 30 LSB First word of the first block being loaded MSB First word of the first block being loaded LSB Last word of t...

Page 216: ...0002 2nd block consists of 2 16 bit words 3F 00 00 80 0x003F8000 2nd block will be loaded starting at 0x3F8000 00 77 Data loaded 0x7700 0x7625 25 76 00 00 0x0000 Size of 0 indicates end of data stream...

Page 217: ...rd W1 W1 0x10AA No 16 bit data size Yes Read EntryPoint address Read second word W2 and discard upper 8 bits 0x08AA W2 W1 Yes No 8 bit DataSize Data format error Return flash entry point Read BlockSiz...

Page 218: ...CSM password locations Call SelectBootMode Call ExitBoot Figure 2 8 Overview of InitBoot Assembly Function 2 2 14 SelectBootMode Function To determine the desired boot mode the SelectBootMode function...

Page 219: ...dog Return EntryAddr A Boot Mode OTP Yes No EntryAddr OTP Entry Point 0x3D 7800 Boot Mode RAM Yes No EntryAddr SARAM Entry Point 0x00 0000 Boot Mode SCI Yes No EntryAddr SCI_Boot Boot Mode SPI Yes No...

Page 220: ...r to a GetWordData function that is initialized by each of the loaders to properly read data from that port For example when the SPI loader is evoked the GetWordData function pointer is initialized to...

Page 221: ...Overview of SCI Bootloader Operation The SCI A loader uses following pins SCIRXDA on GPIO28 SCITXDA on GPIO29 The 28x device communicates with the external host device by communication through the SC...

Page 222: ...baud rate register to the desired high baud rate SCI_Boot Enable the SCI A clock set the LSPCLK to 4 functionality and pullups on Enable the SCIA TX and RX pin Setup SCI A for 1 stop 8 bit character...

Page 223: ...esistor required The 28x communicates with the external host device by polling and driving the AIO12 and AIO6 lines An external pull up resistor is required for AIO12 because AIO pins lack internal pu...

Page 224: ...ed n 2 n 3 00 00 Block size of 0000h indicates end of the source program The 28x device first signals the host that it is ready to begin data transfer by pulling the AIO6 pin low The host load then in...

Page 225: ...ot critical in this mode as the host will wait for the 28x and the 28x will in turn wait for the host In this manner the protocol will work with both a host running faster and a host running slower th...

Page 226: ...e passed back to the calling routine AIO6 0 Signal host that 28x is ready Parallel_GetWordData 8 bit AIO12 0 Data ready Yes from GPIO 31 30 5 0 Read word of data AIO6 1 28x ack read complete AIO12 1 a...

Page 227: ...M Immediately after entering the SPI_Boot function the pin functions for the SPI pins are set to primary and the SPI is initialized The initialization is done at the slowest speed possible Once the SP...

Page 228: ...not match then the load is aborted and the device will branch to the flash entry point address 6 The next 2 bytes fetched can be used to change the value of the low speed peripheral clock register LO...

Page 229: ...mp to Flash Read LOSPCP value Change LOSPCP Change SPIBRR Read SPIBRR value Read and discard 7 reserved words address Read EntryPoint Call CopyData EntryPoint Return pullups on those pins Figure 2 21...

Page 230: ...GPIO 28 SCLA on GPIO 29 If the download is to be performed from a device other than an EEPROM then that device must be set up to operate in the slave mode and mimic the I2C EEPROM Immediately after en...

Page 231: ...rom the EEPROM This allows the communication to be increased up to a 400 kHz bit rate fast I2C mode during the remaining data reads Arbitration bus busy and slave signals are not checked Therefore no...

Page 232: ...f the source The I2C EEPROM protocol required by the I2C bootloader is shown in Figure 2 25 and Figure 2 26 The first communication which sets the EEPROM address pointer to 0x0000 and reads the KeyVal...

Page 233: ...cy as shown in Table 2 14 Table 2 14 Bit Rate Value for Internal Oscillators OSCCLK SYSCLKOUT Bit Rate 10 MHz 10 MHz 100 kbps The SYSCLKOUT values shown are the reset values with the default PLL setti...

Page 234: ...ddr 15 0 Addr 0xAABBCCDD 29 30 BB AA First word of the first block in the source being loaded 0xAABB Data for this section BB AA Last word of the first block of the source being loaded 0xAABB NN MM Bl...

Page 235: ...all SelectBootMode Call Boot Loader Deallocate stack SP 0x400 Branch to EntryPoint Begin execution at EntryPoint Figure 2 28 ExitBoot Procedure Flow The following CPU registers are restored to their d...

Page 236: ...t address block length and terminating value The contents of the boot table vary slightly depending on the boot mode and the options selected when running the hex conversion utility The actual file fo...

Page 237: ...e LOSPCP register This value is used only for the spi8 boot table format and ignored for all other formats If the value is greater than 0x7F the value is truncated to 0x7F spibrr value Specify the ini...

Page 238: ...rder for the code to execute properly In this case the codestart ramfuncs cinit myreset and text sections need to be loaded The other sections are uninitialized and will not be included in the loading...

Page 239: ...art section 00 00 00 00 Load block starting at 0x000000 7F 00 9A A0 Data block 0x007F 0xA09A 16 00 Load 0x0016 words ramfuncs section 00 00 02 00 Load block starting at 0x000002 22 76 1F 76 2A 00 00 1...

Page 240: ...sed The next four memory locations contain a checksum value for the boot ROM Taking a 64 bit summation of all addresses within the ROM except for the checksum locations generates this checksum Table 2...

Page 241: ...ng enhancements in addition to the Type 0 module Increased Dead Band Resolution The dead band clocking has been enhanced to allow half cycle clocking to double resolution Enhanced Interrupt and SOC Ge...

Page 242: ...system Using the Enhanced Pulse Width Modulator ePWM Module Application Report Expert Materials C2000 real time microcontrollers Reference designs See TI designs related to specific end applications...

Page 243: ...th CPU interrupts and ADC start of conversion SOC Programmable event prescaling minimizes CPU overhead on interrupts PWM chopping by high frequency carrier signal useful for pulse transformer gate dri...

Page 244: ...EPWM1B C28x CPU System Control eQEP1 TZ1 TZ3 to TZ1 TZ3 to EPWM1SYNCO EPWM2B eCAPI EPWMxB EQEP1ERR H R P W M EPWMxA EPWM2A EPWM1A G P I O M U X ADCSOCBO ADCSOCAO Peripheral Bus Pulse Stretch 32 SYSCL...

Page 245: ...to the EMUSTOP output from the CPU This allows you to configure a trip action when the clock fails or the CPU halts Time base synchronization input EPWMxSYNCI and output EPWMxSYNCO signals The synchro...

Page 246: ...T1 force A DCAEVT2 force A DCBEVT1 force A DCBEVT2 force A CTR CMPA 16 CTR CMPB 16 CMPB Active 16 CMPB Shadow 16 CTR PRD or ZERO DCAEVT1 inter DCBEVT1 inter DCAEVT2 inter DCBEVT2 inter EPWMxSYNCI TBCT...

Page 247: ...00D 1 Action Qualifier Software Force Register AQCSFRC 0x000E 1 Yes Action Qualifier Continuous S W Force Register Set Dead Band Generator Submodule Registers DBCTL 0x000F 1 Dead Band Generator Contro...

Page 248: ...herwise these locations are reserved These registers are also described in Chapter 4 See your device specific data sheet to determine which instances include the HRPWM 3 EALLOW protected registers as...

Page 249: ...base counter equal to zero Time base counter equal to counter compare B CMPB No output synchronization signal generated Counter compare CC Specify the PWM duty cycle for output EPWMxA and or output E...

Page 250: ...rrupt Enable ePWM events that will trigger an ADC start of conversion event Specify the rate at which events cause triggers every occurrence or every second or third occurrence Poll set or clear event...

Page 251: ...P1 Digital Compare Signals Figure 3 4 Time Base Submodule Block Diagram 3 2 2 1 Purpose of the Time Base Submodule You can configure the time base submodule for the following Specify the ePWM time bas...

Page 252: ...n ePWM modules that do not include the HRPWM this location is reserved This register is also described in Chapter 4 See your device specific data sheet to determine which ePWM instances include this f...

Page 253: ...Time base counter equal max value TBCTR 0xFFFF Generated event when the TBCTR value reaches its maximum value This signal is only used only as a status bit TBCLK Time base clock This is a prescaled v...

Page 254: ...nt is transferred to the active register This prevents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the shadow period register i...

Page 255: ...Synchronization A time base synchronization scheme connects all of the ePWM modules on a device Each ePWM module has a synchronization input EPWMxSYNCI and a synchronization output EPWMxSYNCO The inpu...

Page 256: ...f the direction prior to the synchronization event The PHSDIR bit is ignored in count up or count down modes See Figure 3 8 through Figure 3 11 for examples Clearing the TBCTL PHSEN bit configures the...

Page 257: ...trate the operation of the first three modes the following timing diagrams show when events are generated and how the time base responds to an EPWMxSYNCI signal 0000 EPWMxSYNCI TBCTR 15 0 CTR_dir CTR...

Page 258: ...WN UP DOWN UP TBPHS value TBPRD value EPWMxSYNCI CTR_dir CTR zero CNT_max CTR PRD Figure 3 10 Time Base Up Down Count Waveforms TBCTL PHSDIR 0 Count Down On Synchronization Event Enhanced Pulse Width...

Page 259: ...max CTR PRD Figure 3 11 Time Base Up Down Count Waveforms TBCTL PHSDIR 1 Count Up On Synchronization Event www ti com Enhanced Pulse Width Modulator ePWM Module SPRUH18I JANUARY 2011 REVISED JUNE 2022...

Page 260: ...mpare Signals COMP COMPxOUT CPU SYSCTRL EQEP1 Digital Compare Signals Figure 3 12 Counter Compare Submodule TBCTR 15 0 Time Base TB Module 16 CMPA 15 0 16 16 16 CMPA Compare A Active Reg CTR CMPA CTR...

Page 261: ...0x0009 Yes Counter Compare A Register Section 3 4 2 3 CMPB 0x000A Yes Counter Compare B Register Section 3 4 2 4 CMPAHRM 0x002C Writes HRPWM counter compare A Extension Mirror Register 1 Section 3 4...

Page 262: ...vely The behavior of the two load modes is Shadow Mode The shadow mode for the CMPA is enabled by clearing the CMPCTL SHDWAMODE bit and the shadow register for CMPB is enabled by clearing the CMPCTL S...

Page 263: ...dered normal operation and must be taken into account Figure 3 14 Counter Compare Event Waveforms in Up Count Mode TBCTR 15 0 0x0000 0xFFFF CTR CMPA CMPA value CMPB value TBPHS value TBPRD value CTR C...

Page 264: ...t 0x0000 0xFFFF TBCTR 15 0 CMPA value CMPB value TBPHS value TBPRD value CTR CMPA CTR CMPB EPWMxSYNCI Figure 3 17 Counter Compare Events In Up Down Count Mode TBCTL PHSDIR 1 Count Up On Synchronizatio...

Page 265: ...LOCKFAIL EQEP1ERR Digital Compare Signals COMP COMPxOUT CPU SYSCTRL EQEP1 Digital Compare Signals Figure 3 18 Action Qualifier Submodule 3 2 4 1 Purpose of the Action Qualifier Submodule The action qu...

Page 266: ...e AQCSFRC 3 0 shadow continuous S W force AQCSFRC 3 0 active continuous S W force Figure 3 19 Action Qualifier Submodule Inputs and Outputs For convenience the possible input events are summarized aga...

Page 267: ...TR CMPB can operate on output EPWMxA All qualifier actions are configured via the control registers found at the end of this section For clarity the drawings in this document use a set of symbolic act...

Page 268: ...case the counter direction is always defined as up and thus down count events will never be taken Table 3 10 Action Qualifier Event Priority for Up Count Mode Priority Level Event 1 Highest Software...

Page 269: ...his means there will always be a pulse of at least one TBCLK cycle in a PWM period which when very short tend to be ignored by the system Use up down count mode to generate an asymmetric PWM To achiev...

Page 270: ...1 Up Down Count Mode Symmetrical Waveform The PWM waveforms in Figure 3 22 through Figure 3 27 show some common action qualifier configurations The C code samples in Example 3 1 through Example 3 6 sh...

Page 271: ...MPA half CMPA 350 Compare A 350 TBCLK counts EPwm1Regs CMPB 200 Compare B 200 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE T...

Page 272: ...set by CMPB and is active low that is the low time duty is proportional to CMPB D Actions at zero and period although appearing to occur concurrently are actually separated by one TBCLK period TBCTR...

Page 273: ...LK SYSCLKOUT EPwm1Regs TBCTL bit CLKDIV TB_DIV1 EPwm1Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm1Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm1Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on TBCTR Zero EPwm1Reg...

Page 274: ...egs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE TB_COUNT_UP EPwm1Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwm1Regs TBCTL bit PRDLD...

Page 275: ...pare B 500 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetric xEPwm1Regs TBCTL bit PHSEN TB_DISABLE Phas...

Page 276: ...Pwm1Regs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwm1Regs CMPB 400 Compare B 400 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit...

Page 277: ...CMPA half CMPA 250 Compare A 250 TBCLK counts EPwm1Regs CMPB 450 Compare B 450 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE...

Page 278: ...en the dead band submodule described here should be used The key functions of the dead band module are Generating appropriate signal pairs EPWMxA and EPWMxB with dead band relationship from a single E...

Page 279: ...ing edge delayed signal is to be inverted before being sent out of the dead band submodule 0 1 S2 1 0 S1 RED Out In Rising edge delay 10 bit counter 10 bit counter delay Falling edge In Out FED 1 0 S3...

Page 280: ...The dead band submodule supports independent values for rising edge RED and falling edge FED delays The amount of delay is programmed using the DBRED and DBFED registers These are 10 bit registers an...

Page 281: ...tary ALC Active High AH Active Low AL RED FED Period Figure 3 30 Dead Band Waveforms for Typical Cases 0 Duty 100 www ti com Enhanced Pulse Width Modulator ePWM Module SPRUH18I JANUARY 2011 REVISED JU...

Page 282: ...Programmable pulse width of first pulse Programmable duty cycle of second and subsequent pulses Can be fully bypassed if not required 3 2 6 2 Controlling the PWM Chopper Submodule The PWM chopper subm...

Page 283: ...rms Figure 3 33 shows simplified waveforms of the chopping action only one shot and duty cycle control are not shown Details of the one shot and duty cycle control are discussed in the following secti...

Page 284: ...idth values for a SYSCLKOUT 90 MHz PSCLK OSHT EPWMxA in EPWMxA out Prog pulse width OSHTWTH Start OSHT pulse Sustaining pulses Figure 3 34 PWM Chopper Submodule Waveforms Showing the First Pulse and S...

Page 285: ...ammable duty cycle allows a design to be tuned or optimized via software control Figure 3 35 shows the duty cycle control that is possible by programming the CHPDUTY bits One of seven possible duty ra...

Page 286: ...COMPxOUT CPU SYSCTRL EQEP1 Digital Compare Signals Figure 3 36 Trip Zone Submodule 3 2 7 1 Purpose of the Trip Zone Submodule The key functions of the Trip Zone submodule are Trip inputs TZ1 to TZ6 c...

Page 287: ...atches The asynchronous trip makes sure that if clocks are missing for any reason the outputs can still be tripped by a valid event present on TZn inputs The GPIOs or peripherals must be appropriately...

Page 288: ...e event occurs the action specified in the TZCTL DCAEVT1 2 and TZCTL DCBEVT1 2 bits is carried out immediately on the EPWMxA and or EPWMxB output Table 3 18 lists the possible actions In addition the...

Page 289: ...on TZ5 pulls both EPWM1A EPWM1B low A one shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state Configure the ePWM1 registers as follows TZSEL CBC5 1 enables TZ5 as a one shot event source...

Page 290: ...ce DCBEVT2 force COMPxOUT TZ1 TZ2 TZ3 DCAEVT2 force DCBEVT2 force TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 DCAEVT1 force DCBEVT1 force Async Trip Set Clear TZCLR CBC TZFLG CBC Sync CBC Latch Set Clear Trip Async Trip...

Page 291: ...2 Clear Latch Set TZCLR DCBEVT1 DCBEVT1 inter TZEINT DCBEVT1 TZFLG DCBEVT1 Clear Latch Set TZCLR DCBEVT2 DCBEVT2 inter TZEINT DCBEVT2 TZFLG DCBEVT2 Generate Interrupt Pulse When Input 1 Clear Latch Se...

Page 292: ...se Signals Dead Band DB Counter Compare CC Action Qualifier AQ EPWMxA EPWMxB CTR CMPB CTR 0 EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxA EPWMxB TZ1 TZ3 to CTR CMPA Time Base TB CTR PRD CTR 0 CTR_Dir EPWMxSYNCI...

Page 293: ...r prescaling logic can issue Interrupt requests and ADC start of conversion at Every event Every second event Every third event PIE Event Trigger Module Logic CTR Zero CTR PRD CTR CMPA EPWMxINTn CTR C...

Page 294: ...ection ETSEL INTSEL bits The event can be one of the following Time base counter equal to zero TBCTR 0x0000 Time base counter equal to period TBCTR TBPRD Time base counter equal to zero or period TBCT...

Page 295: ...ent the event counter INTCNT The counter will behave as described above when INTCNT INTPRD When INTPRD 0 the counter is disabled and hence no events will be detected and the ETFRC INT bit is also igno...

Page 296: ...T ETPS SOCAPRD ETCLR SOCA SOCA ETFRC SOCA ETSEL SOCA 000 001 010 011 100 101 111 110 DCAEVT1 soc A ETFLG SOCA CTRU CMPA CTRD CMPA CTRU CMPB CTRD CMPB ETSEL SOCASEL CTR Zero CTR PRD A The DCAEVT1 soc s...

Page 297: ...Base submodule Trip Zone submodule Event Trigger submodule DCAEVT1 force DCAEVT2 force DCBEVT1 force DCBEVT2 force COMP COMP GPIO MUX Figure 3 45 Digital Compare Submodule High Level Block Diagram 3 2...

Page 298: ...erate the Digital Compare A High and Low DCAH L and Digital Compare B High and Low DCBH L signals Then the configuration of the TZDCSEL register qualifies the actions on the selected DCAH L and DCBH L...

Page 299: ...input signal and the TBCTL SWFSYNC signal to generate a synchronization pulse to the time base counter Figure 3 46 and Figure 3 47 show how the DCAEVT1 DCAEVT2 and DCEVTFILT signals are processed to...

Page 300: ...sync DCBCTL EVT1SYNCE async DCEVTFILT DCBCTL EVT1FRCSYNCSEL DCBCTL EVT1SRCSEL Figure 3 48 DCBEVT1 Event Triggering Sync DCBEVT2 force 1 0 TBCLK DCBEVT2 1 0 TZFRC DCBEVT2 Latch set clear TZCLR DCBEVT2...

Page 301: ...vents DCAEVT1 DCAEVT2 DCBEVT1 DCBEVT2 is selected for filtering The blanking window which filters out all event occurrences on the signal while it is active will be aligned to either a CTR PRD pulse o...

Page 302: ...cribed the operation of a single module To facilitate the understanding of multiple modules working together in a system the ePWM module described in reference is represented by the more simplified bl...

Page 303: ...Master mode provides a sync at any programmable point in time SyncOut connected to CTR CMPB Module is in standalone mode and provides No sync to other modules SyncOut connected to X disabled For each...

Page 304: ...ote that only three waveforms are shown although there are four stages CTR zero CTR CMPB X En SyncOut Phase reg Ext SyncIn optional EPWM1A EPWM1B SyncOut Phase reg CTR CMPB CTR zero X En EPWM2B EPWM2A...

Page 305: ...interrupt CB A I P I P I P I Indicates this event triggers an ADC start of conversion Figure 3 55 Buck Waveforms for Figure 3 54 Note Only three bucks shown here www ti com Enhanced Pulse Width Modula...

Page 306: ...HDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit...

Page 307: ...enerated by the configuration CTR zero CTR CMPB X En 0 SyncOut Phase reg Ext SyncIn optional EPWM1A EPWM1B SyncOut Phase reg CTR CMPB CTR zero X X En EPWM2B EPWM2A Slave Master Buck 1 Vout1 Vin1 EPWM1...

Page 308: ...CB CB CB CB CA CA CA CA CB CB CB CB Figure 3 57 Buck Waveforms for Figure 3 56 Note FPWM2 FPWM1 Enhanced Pulse Width Modulator ePWM Module www ti com 308 TMS320x2806x Microcontrollers SPRUH18I JANUAR...

Page 309: ...se register to zero EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SY...

Page 310: ...3 58 Module 2 slave is configured for Sync flow through if required this configuration allows for a third Half H bridge to be controlled by PWM module 3 and also most importantly to remain in synchron...

Page 311: ...B CA Z A CB CA Z A CB Z CA A CB Z CA RED delay RED delay RED Delay RED Delay Figure 3 59 Half H Bridge Waveforms for Figure 3 58 Note Here FPWM2 FPWM1 www ti com Enhanced Pulse Width Modulator ePWM Mo...

Page 312: ...s AQCTLA bit ZRO AQ_SET set actions for EPWM1A EPwm2Regs AQCTLA bit CAU AQ_CLEAR EPwm2Regs AQCTLB bit ZRO AQ_CLEAR set actions for EPWM1B EPwm2Regs AQCTLB bit CAD AQ_SET EPwm2Regs DBCTL bit OUT_MODE 2...

Page 313: ...e SyncOut X En EPWM3B EPWM3A Phase reg CTR CMPB CTR zero 4 Slave SyncOut X EPWM4A EPWM4B En SyncOut CTR zero CTR CMPB Phase reg Phase reg CTR CMPB CTR zero Slave 6 5 Slave X En SyncIn EPWM6B EPWM6A Sy...

Page 314: ...CA Z I A P CA CA CA CA CA CA CA CA CA CA Figure 3 61 3 Phase Inverter Waveforms for Figure 3 60 Only One Inverter Shown Enhanced Pulse Width Modulator ePWM Module www ti com 314 TMS320x2806x Microcon...

Page 315: ...2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCTLA bit CAD AQ_CLEAR EPwm2Regs DBCTL bit OUT_MODE DB_FULL_ENABLE enable Dead...

Page 316: ...onfigured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCTR register To illustrate this concept Figure 3 62 shows a master and slave module with a phase relationship of 1...

Page 317: ...e base is always leading the master s time base by 120 0000 FFFFh TBPRD TBCTR 0 15 time CTR PRD SycnOut Master Module 2 Phase 120 0000 FFFFh TBPRD TBCTR 0 15 time SyncIn Slave Module TBPHS 600 600 600...

Page 318: ...wing formula gives the TBPHS values for N phases TBPHS N M TBPRD N x 1 Where N number of phases M PWM module number For example for the 3 phase case N 3 TBPRD 600 TBPHS 3 2 600 3 x 2 1 200 that is Pha...

Page 319: ...Z I Z I Z I Z I Z I A P CA CA A P CA CA A P CA CA Figure 3 65 3 Phase Interleaved DC DC Converter Waveforms for Figure 3 64 www ti com Enhanced Pulse Width Modulator ePWM Module SPRUH18I JANUARY 2011...

Page 320: ...egs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCTLA bit CAD AQ_CLEAR EPwm2Regs DBCTL bit OUT_MODE DB_FULL_ENABLE enable dead b...

Page 321: ...ol a single power stage which in turn requires control of four switching elements Figure 3 67 shows a master slave module combination synchronized together to control a full H bridge In this case both...

Page 322: ...sition ZVS transition Z CA Z I Z I Z I Z CB A CA CB A Z Z CB A CA Z Z CB A CA Figure 3 67 ZVS Full H Bridge Waveforms Enhanced Pulse Width Modulator ePWM Module www ti com 322 TMS320x2806x Microcontro...

Page 323: ...ter to zero initially EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UP Asymmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYN...

Page 324: ...ely an external reference could be connected at this input The comparator output is an input to the digital compare submodule The ePWM module is configured in such a way so as to trip the ePWM1A outpu...

Page 325: ...s TZDCSEL bit DCAEVT2 TZ_DCAH_HI DCAEVT2 DCAH high will become active as Comparator output goes high EPwm1Regs DCACTL bit EVT2SRCSEL DC_EVT2 DCAEVT2 DCAEVT2 not filtered EPwm1Regs DCACTL bit EVT2FRCSY...

Page 326: ...TBCLK it is up to the user to update it in real time to enhance the efficiency by adjusting enough time delay for soft switching VDC_bus VOUT EPWM1A EPWM1B Cr Integrated Magnetcis LLC Resonant Transf...

Page 327: ...EPwm1Regs AQCTLB bit CAU AQ_SET Set PWM1B on event A up count EPwm1Regs AQCTLB bit PRD AQ_CLEAR Clear PWM1B on PRD EPwm1Regs DBCTL bit IN_MODE DBA_ALL EPWMxA is the source for both delays EPwm1Regs D...

Page 328: ...TBPRD Down count mode stop when the time base counter 0x0000 TBCTR 0x0000 Up down count mode stop when the time base counter 0x0000 TBCTR 0x0000 1x Free run 13 PHSDIR Phase Direction Bit This bit is...

Page 329: ...om its shadow register when the time base counter TBCTR is equal to zero A write or read to the TBPRD register accesses the shadow register 1 Load the TBPRD register immediately without using a shadow...

Page 330: ...ear the latched event 1 SYNCI Input Synchronization Latched Status Bit 0 Writing a 0 will have no effect Reading a 0 indicates no external synchronization event has occurred 1 Reading a 1 on this bit...

Page 331: ...ter TBPHS Field Descriptions Bits Name Value Description 15 0 TBPHS 0000 FFFF These bits set time base counter phase of the selected ePWM relative to the time base that is supplying the synchronizatio...

Page 332: ...r TBPRD Field Descriptions Bit Field Value Description 15 0 TBPRD 0000 FFFFh These bits determine the period of the time base counter This sets the PWM frequency Shadowing of this register is enabled...

Page 333: ...ion portion of the period value The TBPRDHR register is not affected by the TBCTL PRDLD bit Reads from this register always reflect the shadow register Likewise writes are also to the shadow register...

Page 334: ...ed memory address location of the TBPRD legacy register a 32 bit write is not possible with TBPRD and TBPRDHR The TBPRDHRM register is not affected by the TBCTL PRDLD bit Writes to both the TBPRDHR an...

Page 335: ...By default writes to this register are shadowed Unlike the TBPRD register reads of TBPRDM always return the active register value Shadowing is enabled and disabled by the TBCTL PRDLD bit If TBCTL PRDL...

Page 336: ...A shadow FIFO not full yet 1 Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value 7 Reserved Reserved 6 SHDWBMODE Counter compare B CMPB Register Operating Mode 0...

Page 337: ...ion CMPAHR Register 15 8 CMPAHR R W 0 7 0 Reserved R 0 LEGEND R W Read Write R Read only n value after reset Table 3 31 Compare A High Resolution CMPAHR Register Field Descriptions Bit Field Value Des...

Page 338: ...xA and or EPWMxB signal low Set Pull the EPWMxA and or EPWMxB signal high Toggle the EPWMxA and or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL SHDWAMODE bit By defau...

Page 339: ...and or EPWMxB signal low Set Pull the EPWMxA and or EPWMxB signal high Toggle the EPWMxA and or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL SHDWBMODE bit By default...

Page 340: ...RM locations access the high resolution least significant 8 bit portion of the Counter Compare A value The only difference is that unlike CMPAHR reads from the mirror register CMPAHRM are indeterminat...

Page 341: ...nd disabled by the CMPCTL SHDWAMODE bit If CMPCTL SHDWAMODE 0 then the shadow is enabled and any write will automatically go to the shadow register All reads will reflect the active register value In...

Page 342: ...A output low output signal will be forced high and a high signal will be forced low 7 6 CAD Action when the counter equals the active CMPA register and the counter is decrementing 00 Do nothing action...

Page 343: ...10 CBD Action when the counter equals the active CMPB register and the counter is decrementing 00 Do nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle...

Page 344: ...0 or counting down 00 Do nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle EPWMxB output low output signal will be forced high and a high signal will b...

Page 345: ...register is complete that is a forced event is initiated This is a one shot forced event It can be overridden by another subsequent event on output B 1 Initiates a single s w forced event 4 3 ACTSFB A...

Page 346: ...To configure shadow mode use AQSFRC RLDCSF 00 Software forcing is disabled and has no effect 01 Forces a continuous low on output B 10 Forces a continuous high on output B 11 Software forcing is disab...

Page 347: ...fier is the source for rising edge delayed signal EPWMxA In from the action qualifier is the source for falling edge delayed signal 10 EPWMxA In from the action qualifier is the source for rising edge...

Page 348: ...action qualifier is passed straight through to the EPWMxA input of the PWM chopper submodule The falling edge delayed signal is seen on output EPWMxB The input signal for the delay is determined by DB...

Page 349: ...r 3 4 4 3 Dead Band Generator Falling Edge Delay DBFED Register Figure 3 93 Dead Band Generator Falling Edge Delay DBFED Register 15 10 9 8 Reserved DEL R 0 R W 0 7 0 DEL R W 0 LEGEND R W Read Write R...

Page 350: ...or this ePWM module 14 DCAEVT1 Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one shot trip source for this ePWM module 1 Enable DCAEVT1 as one shot trip source for this ePWM module 13 O...

Page 351: ...Enable TZ5 as a CBC trip source for this ePWM module 3 CBC4 Trip zone 4 TZ4 Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module 2 CBC3...

Page 352: ...BH don t care 101 DCBL high DCBH low 110 reserved 111 reserved 5 3 DCAEVT2 Digital Compare Output A Event 2 Selection 000 Event disabled 001 DCAH low DCAL don t care 010 DCAH high DCAL don t care 011...

Page 353: ...1 Do Nothing trip action is disabled 7 6 DCAEVT2 Digital Compare Output A Event 2 Action On EPWMxA 00 High impedance EPWMxA High impedance state 01 Force EPWMxA to a high state 10 Force EPWMxA to a lo...

Page 354: ...s Bits Name Value Description 15 3 Reserved Reserved 6 DCBEVT2 Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled 5 DCBEVT1 Digital Comparator Output B Event 1 Interrupt Enable...

Page 355: ...icates a trip event has occurred for the event defined for DCAEVT1 2 OST Latched Status Flag for A One Shot Trip Event 0 No one shot trip event has occurred 1 Indicates a trip event has occurred on a...

Page 356: ...nterrupts will be generated until this flag is cleared If the interrupt flag is cleared when either CBC or OST is set then another interrupt pulse will be generated Clearing all flag bits will prevent...

Page 357: ...1 clears the DCAEVT2 event trip condition 3 DCAEVT1 Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect This bit always reads back 0 1 Writing 1 clears the DCAEVT1 event trip co...

Page 358: ...s the TZFLG DCBEVT1 bit 4 DCAEVT2 Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect This bit always reads back 0 1 Writing 1 forces the DCAEVT2 event trip condition and sets th...

Page 359: ...t time base counter equal to CMPA when the timer is decrementing 110 Enable event time base counter equal to CMPB when the timer is incrementing 111 Enable event time base counter equal to CMPB when t...

Page 360: ...ite R Read only n value after reset Table 3 51 Event Trigger Prescale Register ETPS Field Descriptions Bits Name Description 15 14 SOCBCNT ePWM ADC Start of Conversion B Event EPWMxSOCB Counter Regist...

Page 361: ...NT 1 the counter will stop counting events when it reaches the period value ETPS INTCNT ETPS INTPRD 00 No events have occurred 01 1 event has occurred 10 2 events have occurred 11 3 events have occurr...

Page 362: ...ETFLG INT flag the EPWMxSOCA output will continue to pulse even if the flag bit is set 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCA The EPWMxSO...

Page 363: ...g a 0 has no effect Always reads back a 0 1 Clears the ETFLG SOCB flag bit 2 SOCA ePWM ADC Start of Conversion A EPWMxSOCA Flag Clear Bit 0 Writing a 0 has no effect Always reads back a 0 1 Clears the...

Page 364: ...s 2 SOCA SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register The ETFLG SOCA flag bit will be set regardless 0 Writing 0 to this bit will be ignored Alway...

Page 365: ...ty 2 8 25 0 010 Duty 3 8 37 5 011 Duty 4 8 50 0 100 Duty 5 8 62 5 101 Duty 6 8 75 0 110 Duty 7 8 87 5 111 Reserved 7 5 CHPFREQ Chopping Clock Frequency 000 Divide by 1 no prescale 11 25 MHz at 90 MHz...

Page 366: ...S at 90 MHz SYSCLKOUT 1000 9 x SYSCLKOUT 8 wide 800 nS at 90 MHz SYSCLKOUT 1001 10 x SYSCLKOUT 8 wide 888 9 nS at 90 MHz SYSCLKOUT 1010 11 x SYSCLKOUT 8 wide 977 8 nS at 90 MHz SYSCLKOUT 1011 12 x SYS...

Page 367: ...ve high or active low 0000 TZ1 input 0001 TZ2 input 0010 TZ3 input 1000 COMP1OUT input 1001 COMP2OUT input 1010 COMP3OUT input Values not shown are reserved If a device does not have a particular comp...

Page 368: ...have a particular comparator then that option is reserved 3 0 DCAHCOMPSEL Digital Compare A High Input Select Defines the source for the DCAH input The TZ signals when used as trip signals are treated...

Page 369: ...Asynchronous Signal 8 EVT2SRCSEL DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal 7 4 Reserved Reserved 3 EVT1SYNCE DCAEVT1 SYNC Enable Disable 0 SYNC Generation D...

Page 370: ...Asynchronous Signal 8 EVT2SRCSEL DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal 7 4 Reserved Reserved 3 EVT1SYNCE DCBEVT1 SYNC Enable Disable 0 SYNC Generation D...

Page 371: ...PULSESEL Pulse Select For Blanking Capture Alignment 00 Time base counter equal to period TBCTR TBPRD 01 Time base counter equal to zero TBCTR 0x0000 10 Reserved 11 Reserved 3 BLANKINV Blanking Window...

Page 372: ...ctive register is copied to shadow register on a TBCTR TBPRD or TBCTR zero event as defined by the DCFCTL PULSESEL bit CPU reads of the DCCAP register will return the shadow register contents 1 Active...

Page 373: ...the blanking window is currently active then the blanking window counter is restarted 3 4 8 7 Digital Compare Filter Offset Counter DCFOFFSETCNT Register Figure 3 113 Digital Compare Filter Offset Cou...

Page 374: ...arted The blanking window can cross a PWM period boundary 3 4 8 9 Digital Compare Filter Window Counter DCFWINDOWCNT Register Figure 3 115 Digital Compare Filter Window Counter DCFWINDOWCNT Register 1...

Page 375: ...w register on the TBCTR TBPRD or TBCTR zero as defined by the DCFCTL PULSESEL bit CPU reads of this register will return the shadow register value If DCCAPCTL SHDWMODE 1 then the shadow register is di...

Page 376: ...dth Modulator ePWM Module www ti com 376 TMS320x2806x Microcontrollers SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated This page intentio...

Page 377: ...is on the EPWMxA output Self check diagnostics software mode to check if the micro edge positioner MEP logic is running optimally Enables high resolution output on B signal path of PWM via PWM A and B...

Page 378: ...typical and maximum performance specifications for the MEP Table 4 1 Resolution for PWM and HRPWM PWM Frequency Regular Resolution PWM High Resolution HRPWM 90 MHz SYSCLKOUT kHz Bits Bits 20 12 1 0 0...

Page 379: ...iven frequency and polarity The HRPWM works together with the TBM CCM and AQM registers to extend edge resolution and should be configured accordingly Although many programming combinations are possib...

Page 380: ...A These registers are mirrored and can be written to at two different memory locations mirrored registers have an M suffix that is CMPA mirror CMPAM Reads of the high resolution mirror registers will...

Page 381: ...WMB PWM Chopper PC Trip Zone TZ EPWMxA EPWMxB CTR ZERO EPWMxTZINT TZ1 TZ3 to EMUSTOP CLOCKFAIL DCAEVT1 force A DCAEVT2 force A DCBEVT1 force A DCBEVT2 force A CTR CMPA 16 CMPAHR 8 CTR CMPB 16 CMPB Act...

Page 382: ...MEP Calibration Module HRMSTEP HRCNFG EPWMxAO EPWMxBO 1 From ePWM time base TB submodule 2 From ePWM counter compare CC submodule Figure 4 5 HRPWM Block Diagram High Resolution Pulse Width Modulator...

Page 383: ...lution B Signal Control The B signal path of an ePWM channel can generate a high resolution output by either swapping the A and B outputs the high resolution signal will appear on ePWMxB instead of eP...

Page 384: ...r example switch modes digital motor control DMC uninterruptible power supply UPS a digital controller PID 2pole 2zero lag lead and so on issues a duty command usually expressed in a per unit or perce...

Page 385: ...his section describes the mapping from a per unit duty cycle only The method for mapping from a per unit period is described in Section 4 2 3 4 To do this first examine the scaling or mapping steps in...

Page 386: ...ns TI provides an MEP scale factor optimizing SFO software C function which uses the built in diagnostics in each HRPWM and returns the best scale factor for a given operating point The scale factor v...

Page 387: ...bilities are not available regular PWM duty control is still fully operational down to 0 duty In most applications this should not be an issue as the controller regulation point is usually not designe...

Page 388: ...no longer an issue However there will be a maximum duty limitation with same percent numbers as given in Table 4 5 Tpwm EPWM1A 0 TBPRD 3 SYSCLKOUT Figure 4 8 High Duty Cycle Range Limitation Example...

Page 389: ...MxB output will have 1 TBCLK cycle jitter in up count mode and 2 TBCLK cycle jitter in up down count mode The scaling procedure described for duty cycle in Section 4 2 3 2 applies for high resolution...

Page 390: ...down count mode 257 TBPRD period value 2 TBPRD register value 0101h Step 2 Fractional value conversion for TBPRDHR register TBPRDHR register value frac PWMperiod MEP_ScaleFactor 0 5 shift is to move t...

Page 391: ...rol HRPCTL HRPE 1 7 Enable TBCLKSYNC 8 TBCTL SWFSYNC 1 9 HRMSTEP must contain an accurate MEP scale factor of MEP steps per SYSCLKOUT coarse step because auto conversion is enabled The MEP scale facto...

Page 392: ...mines the optimum MEP_ScaleFactor As such MEP Control and Diagnostics registers are reserved for TI use A detailed description of the SFO library SFO_TI_Build_V6 lib software can be found in Section 4...

Page 393: ...cept that the appropriate MEP options need to be enabled selected EPWM1A Vin1 Vout1 Buck Figure 4 11 Simple Buck Controlled Converter Using a Single PWM Z CA Z CA Z Tpwrr EPWM1A Figure 4 12 PWM Wavefo...

Page 394: ...tected and act only on ChA EPwm1Regs HRCNFG all 0x0 clear all bits first EPwm1Regs HRCNFG bit EDGMODE HR_FEP Control Falling Edge Position EPwm1Regs HRCNFG bit CTLMODE HR_CMP CMPAHR controls the MEP E...

Page 395: ...propriate MEP options need to be enabled selected EPWM1A VOUT1 LPF Figure 4 13 Simple Reconstruction Filter for a PWM Based DAC EPWM1A CA TPWM 2 5 s Z CA Z Z Figure 4 14 PWM Waveform Generated for the...

Page 396: ...st EPwm1Regs HRCNFG bit EDGMODE HR_FEP Control falling edge position EPwm1Regs HRCNFG bit CTLMODE HR_CMP CMPAHR controls the MEP EPwm1Regs HRCNFG bit HRLOAD HR_CTR_ZERO Shadow load on CTR Zero EDIS ME...

Page 397: ...ed to all ePWM channels running in HRPWM mode because the function makes use of the diagnostics logic in the MEP calibration module which runs independently of ePWM channels This routine returns a 1 w...

Page 398: ...above TBPRD 3 This would avoid any unexpected transitions on the PWM signal 4 3 2 Software Usage The software library function SFO calculates the MEP scale factor for the HRPWM supported ePWM modules...

Page 399: ...p 4 Application Code While the application is running fluctuations in both device temperature and supply voltage may be expected To be sure that optimal Scale Factors are used for each ePWM module the...

Page 400: ...the application should write MEP_Scalefactor in the HRMSTEP register as shown in Example 4 10 Example 4 10 Manually Updating the HRMSTEP Register if Using SFO_TI_Build_V6b lib main int status status S...

Page 401: ...000A 1 Yes Counter Compare B Register Section 3 4 2 4 HRPWM Registers HRCNFG 0x0020 1 HRPWM Configuration Register Section 4 4 1 HRMSTEP 0x0026 1 HRPWM MEP Step Register Section 4 4 2 High Resolution...

Page 402: ...rmal 1 ePWMxB output is inverted version of ePWMxA signal 4 3 HRLOAD Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register 00 Load on CTR Zero Time base co...

Page 403: ...used by the hardware to automatically convert the value in the CMPAHR TBPHSHR or TBPRDHR register to a scaled micro edge delay on the high resolution ePWM output The value in this register is written...

Page 404: ...to enable this bit also if they want to control phase in conjunction with the high resolution period feature This bit and the TBCTL PHSEN bit must be set to 1 when high resolution period is enabled f...

Page 405: ...th an HRCAP module of the same type to determine the differences between types and for a list of device specific differences within a type 5 1 Introduction 406 5 2 Description 406 5 3 Operational Deta...

Page 406: ...libration block which connects internally to an HRPWM channel during calibration See the device specific data manual to determine which HRPWM channel output the HRCAP module is internally tied to duri...

Page 407: ...the system clock the 16 bit counter HCCOUNTER and edge detection logic used for capturing high resolution pulses is clocked by HCCAPCLK HCCAPCLK must fall within the frequency range specified in the E...

Page 408: ...HRCAP Counter Both modes of operation utilize HCCOUNTER which resets to 0 and starts counting HCCAPCLK cycles again under the following conditions SOFTRESET Detection of rising edge Detection of falli...

Page 409: ...ured registers as shown in Figure 5 5 Previous RISE interrupt HCCAPCNTFALL1 Service RISE interrupt Previous FALL interrupt Service FALL interrupt HCCAPCNTRISE1 HCCAPCNTRISE0 HCCAPCNTRISE1 HCCAPCNTRISE...

Page 410: ...RISE 1 or a fall event HCIFR FALL 1 occurs the application code reads the HCCAPCNTRISE0 1 and HCCAPCNTFALL0 1 registers and does not require the HCCal HRCAP calibration library The resolution of the...

Page 411: ...ibration once prior to using the HRCAP in high resolution capture mode and periodically in a slow loop to account for changes in the HRCAP step size due to voltage and temperature changes while the ap...

Page 412: ...nabled at the same time Capture registers should be read during rising edge interrupt events only or during falling edge interrupt events only and not during both interrupt events simultaneously If RI...

Page 413: ...e the HRCAP step size to a fraction of the HCCAPCLK cycle while the HRCAP is in high resolution mode To utilize the HCCal capabilities effectively during HRCAP operation the HRCAP calibration logic us...

Page 414: ...is in progress without encountering errors 1 If HCCal has exited with errors User should check that PLL is configured such that the HCCAPCLK frequency falls within the frequency limits designated by t...

Page 415: ...y of the HRCAP modules not used for calibration to convert the HCCAPCNTRISE0 and HRCAP calibration results into a fixed point Q16 integer fractional high resolution low pulse width in HCCAPCLK cycles...

Page 416: ...ber of HCCAPCLK cycles Description These functions can be called for any of the HRCAP modules not used for calibration They use the calibration logic to convert the HCCAPCNTFALL0 1 register value and...

Page 417: ...HCCAPCNTFALL1 as Q16 fixed point value in number of HCCAPCLK cycles Description This function can be called for any of the HRCAP modules not used for calibration It uses the calibration logic to conve...

Page 418: ...P modules not used for calibration It uses the calibration logic to convert the HCCAPCNTFALL0 and HCCAPCNTRISE0 register values and HCCal calibration results into a fixed point Q16 integer fractional...

Page 419: ...an array of pointers to HRCAP_REGS structures which includes all available HRCAP modules on the device Position 0 includes a 0 value which is not used by the HRCAP_Cal function Example 2 A Sample of H...

Page 420: ...ppropriate frequency range if status HCCAL_ERROR ESTOP0 Step 5 Application Code Pulse Width Measurement While the application is running when a RISE or FALL event occurs pulse and period widths can be...

Page 421: ...NTER 0x04 HRCAP 16 bit Counter Register Section 5 5 5 HCCAPCNTRISE0 0x10 HRCAP Capture Counter On Rising Edge 0 Register Section 5 5 6 HCCAPCNTFALL0 0x12 HRCAP Capture Counter On Falling Edge 0 Regist...

Page 422: ...the device specific data manual 0 HCCAPCLK SYSCLKOUT 1 HCCAPCLK PLL2CLK 7 4 Reserved Reserved 3 OVFINTE Counter overflow interrupt enable bit 0 Disable counter overflow interrupt 1 Enable counter over...

Page 423: ...o the corresponding bit in the HCIFRC register 2 FALL Falling edge capture interrupt flag 0 No falling edge interrupt has occurred This bit is cleared to 0 by writing to the corresponding bit in the H...

Page 424: ...UNTEROVF flag bit has priority over the software clear if both happen on the same cycle 2 FALL Falling edge capture interrupt clear bit 0 Writes of 0 are ignored This bit always reads 0 1 Writes of 1...

Page 425: ...over the hardware trying to set the bit in the same cycle 2 FALL Falling edge interrupt force bits 0 Writes of 0 are ignored This bit always reads 0 1 Writes of 1 to this bit will force the correspon...

Page 426: ...PCLK cycle When the counter reaches 0xFFFF it will overflow to 0x0000 on the next cycle and generate a COUNTEROVF interrupt event The counter is reset to 0x0000 on every rising and falling edge event...

Page 427: ...5 5 7 HRCAP Capture Counter On Falling Edge 0 Register HCCAPCNTFALL0 The HRCAP capture counter on falling edge 0 register HCCAPCNTFALL0 is shown and described in the figure and table below Figure 5 1...

Page 428: ...5 5 9 HRCAP Capture Counter On Falling Edge 1 Register HCCAPCNTFALL1 The HRCAP capture counter on falling edge 1 register HCCAPCNTFALL1 is shown and described in the figure and table below Figure 5 21...

Page 429: ...e the differences between the types and for a list of device specific differences within a type 6 1 Introduction 430 6 2 Description 430 6 3 Capture and APWM Operating Mode 432 6 4 Capture Mode Descri...

Page 430: ...tion Capture HRCAP for Single Wire Data Transfer Application Report 6 2 Description The eCAP module represents one complete capture channel that can be instantiated multiple times depending on the tar...

Page 431: ...T SyncOut SyncIn module APWMx ECAPx ECAPxINT ECAP1 GPIO MUX ECAP2 ECAPx Figure 6 1 Multiple eCAP Modules In A C28x System www ti com Enhanced Capture eCAP SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submi...

Page 432: ...P2 reg CAP4 reg CAP3 reg Interrupt I F ECAPxINT Sequencing Edge detection Edge polarity Prescale ECAPx pin Note Same pin depends on operating mode Counter timer SyncIn 32 Capture mode APWM mode Period...

Page 433: ...POLSEL set clear Period Register PRD 0 31 Compare Register CMP 0 31 clear clear CTR 0 31 set set Figure 6 3 Counter Compare and PRD Effects on the eCAP Output in APWM Mode www ti com Enhanced Capture...

Page 434: ...alifier Polarity select Polarity select Polarity select Polarity select CTR PRD CTR_OVF 4 PWM compare logic CTR 0 31 PRD 0 31 CMP 0 31 CTR CMP CTR PRD CTR_OVF OVF APWM mode Delta mode SYNC 4 Capture e...

Page 435: ...scale value of 1 is chosen ECCTL1 13 9 0 0 0 0 0 the input capture signal bypasses the prescale logic completely B The first Rise edge after Prescale configuration change is not passed to Capture logi...

Page 436: ...WRAP value is reached and re arm REARM has not occurred The continuous one shot block controls the start stop and reset zero functions of the Mod4 counter via a mono shot type of action that can be tr...

Page 437: ...ter 32b RST OVF SYSCLK Delta mode CTR OVF CTR 31 0 Figure 6 8 Details of the Counter and Synchronization Block 6 4 5 CAP1 CAP4 Registers These 32 bit registers are fed by the 32 bit counter timer bus...

Page 438: ...g register ECFLG indicates if any interrupt event has been latched and contains the global interrupt flag bit INT An interrupt pulse is generated to the PIE only if any of the interrupt events are ena...

Page 439: ...xINT ECFLG Figure 6 9 Interrupts in eCAP Module 6 4 7 DMA Interrupt On Type 0 eCAP modules the CPU was required to begin data transfers using DMA New to the Type 1 eCAP a separate DMA Trigger ECAP_DMA...

Page 440: ...shadow register contents are transferred over to CAP1 2 registers either immediately upon a write or on a CTR PRD trigger In APWM mode writing to CAP1 CAP2 active registers will also write the same v...

Page 441: ...as follows CMP 0x00000000 output high for duration of period 0 duty CMP 0x00000001 output low 1 cycle CMP 0x00000002 output low 2 cycles CMP PERIOD output low except for 1 cycle 100 duty CMP PERIOD 1...

Page 442: ...ccurs the CTROVF counter overflow flag is set and an interrupt if enabled occurs CTROVF counter overflow Flag is set and an Interrupt if enabled occurs Captured Time stamps are valid at the point indi...

Page 443: ...and so on Duty Cycle1 off time t3 t2 Period1 x 100 and so on CEVT1 CEVT2 CEVT3 CEVT4 CEVT1 FFFFFFFF CTR 0 31 00000000 CAPx pin t MOD4 CTR CAP1 CAP2 CAP3 CAP4 Capture registers 1 4 CEVT2 CEVT1 CEVT3 CE...

Page 444: ...r overflow Flag is set and an Interrupt if enabled occurs The advantage of Delta time Mode is that the CAPx contents directly give timing data without the need for CPU calculations that is Period1 T1...

Page 445: ...and compare This action will automatically copy the init values into the shadow values For subsequent compare updates during run time the shadow registers must be used CEVT1 CEVT2 CEVT5 FFFFFFFF CTR 0...

Page 446: ...1 Example 1 Simple PWM Generation Independent Channel s APRD TSCTR FFFFFFFF ACMP 0000000C APWMx o p pin On time Off time Period 1000h 500h 300h Figure 6 16 PWM Waveform Details of APWM Mode Operation...

Page 447: ...access types are encoded to fit into small table cells Table 6 3 shows the codes that are used for access types in this section Table 6 3 ECAP_REGS Access Type Codes Access Type Code Description Read...

Page 448: ...6 5 Return to the Summary Table Counter Phase Offset Value Register Figure 6 18 CTRPHS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTRPHS R W 0h Tabl...

Page 449: ...mode Reset type SYSRSn 6 7 2 4 CAP2 Register Offset 6h reset 0h CAP2 is shown in Figure 6 20 and described in Table 6 7 Return to the Summary Table Capture 2 Register Figure 6 20 CAP2 Register 31 30 2...

Page 450: ...type SYSRSn 6 7 2 6 CAP4 Register Offset Ah reset 0h CAP4 is shown in Figure 6 22 and described in Table 6 9 Return to the Summary Table Capture 4 Register Figure 6 22 CAP4 Register 31 30 29 28 27 26...

Page 451: ...o prescale by pass the prescaler 1h R W Divide by 2 2h R W Divide by 4 3h R W Divide by 6 4h R W Divide by 8 5h R W Divide by 10 1Eh R W Divide by 60 1Fh R W Divide by 62 8 CAPLDEN R W 0h Enable Loadi...

Page 452: ...counter after Event 2 time stamp has been captured used in difference mode operation 2 CAP2POL R W 0h Capture Event 2 Polarity select Reset type SYSRSn 0h R W Capture Event 2 triggered on a rising edg...

Page 453: ...sters Permits user to enable CAP1 4 register load CAPx APWMx pin operates as a capture input 1h R W ECAP module operates in APWM mode This mode forces the following configuration Resets TSCTR on CTR P...

Page 454: ...number between 1 4 of captures allowed to occur before the CAP 1 4 registers are frozen that is capture sequence is stopped Wrap value for continuous mode This is the number between 1 4 of the capture...

Page 455: ...Bit Field Type Reset Description 15 8 RESERVED R 0h Reserved 7 CTR_EQ_CMP R W 0h Counter Equal Compare Interrupt Enable Reset type SYSRSn 0h R W Disable Compare Equal as an Interrupt source 1h R W Ena...

Page 456: ...ble Capture Event 2 as an Interrupt source 1 CEVT1 R W 0h Capture Event 1 Interrupt Enable Reset type SYSRSn 0h R W Disable Capture Event 1 as an Interrupt source 1h R W Enable Capture Event 1 as an I...

Page 457: ...Status Flag This flag is active in CAP and APWM mode Reset type SYSRSn 0h R W Indicates no event occurred 1h R W Indicates the counter TSCTR has made the transition from FFFFFFFF 00000000 4 CEVT4 R 0h...

Page 458: ...l Interrupt Status Flag Reset type SYSRSn 0h R W Indicates no event occurred 1h R W Indicates that an interrupt was generated Enhanced Capture eCAP www ti com 458 TMS320x2806x Microcontrollers SPRUH18...

Page 459: ...ys reads back a 0 1h R W Writing a 1 clears the CTROVF flag 4 CEVT4 R 0 W1C 0h Capture Event 4 Status Clear Reset type SYSRSn 0h R W Writing a 0 has no effect Always reads back a 0 1h R W Writing a 1...

Page 460: ...the CTR PRD flag 5 CTROVF R 0 W1S 0h Force Counter Overflow Reset type SYSRSn 0h R W No effect Always reads back a 0 1h R W Writing a 1 to this bit sets the CTROVF flag 4 CEVT4 R 0 W1S 0h Force Captur...

Page 461: ...and speed information from a rotating machine for use in a high performance motion and position control system 7 1 Introduction 462 7 2 Configuring Device Pins 464 7 3 Description 465 7 4 Quadrature D...

Page 462: ...gnals that are shifted 90 out of phase from each other These are commonly called the quadrature QEPA and QEPB signals The clockwise direction for most encoders is defined as the QEPA channel going pos...

Page 463: ...wn axle These axles are connected to optical shaft encoders that effectively tell the computer how fast and in what direction the mouse is moving General Issues Estimating velocity from a digital posi...

Page 464: ...or speed by measuring the elapsed time between successive quadrature pulse edges However this method suffers from the opposite limitation as does Equation 1 A combination of relatively large motor spe...

Page 465: ...puts to generate quadrature clock and direction signals Direction count Mode In direction count mode direction and clock signals are provided directly from the external source Some position encoders h...

Page 466: ...QEPSTS QEPCTL Registers used by multiple units QCLK QDIR QI QS PHE PCSOUT Quadrature decoder QDU QDECCTL 16 Position counter control unit PCCU QPOSLAT QPOSSLAT 32 QPOSILAT EQEPxAIN EQEPxBIN EQEPxIIN...

Page 467: ...x0000 eQEP Watchdog Period Register QDECCTL 0x14 1 0 0x0000 eQEP Decoder Control Register QEPCTL 0x15 1 0 0x0000 eQEP Control Register QCAPCTL 0x16 1 0 0x0000 eQEP Capture Control Register QPOSCTL 0x1...

Page 468: ...EQEPxIOE EQEPxSOE EQEPxIOUT EQEPxSOUT EQEPxSIN EQEPxIIN EQEPxBIN EQEPxAIN QDECCTL SWAP QEPSTS QDF EQEPA EQEPB Figure 7 5 Functional Block Diagram of Decoder Unit 7 4 1 Position Counter Input Modes Cl...

Page 469: ...7 7 shows the direction decoding and clock generation from the eQEP input signals Table 7 2 Quadrature Decoder Truth Table Previous Edge Present Edge QDIR QPOSCNT QA QB UP Increment QB DOWN Decrement...

Page 470: ...input clocks QEPA and QEPB as shown in Figure 7 7 Reverse Count In normal quadrature count operation QEPA input is fed to the QA input of the quadrature decoder and the QEPB input is fed to the QB inp...

Page 471: ...in 7 5 Position Counter and Control Unit PCCU The position counter and control unit provides two configuration registers QEPCTL and QPOSCTL for setting up position counter operational modes position c...

Page 472: ...to the QPOSILAT register and direction information is recorded in the QEPSTS QDLF bit on every index event marker The position counter error flag QEPSTS PCEF and error interrupt flag QFLG PCE are set...

Page 473: ...2 3 4 0 1 0 4 3 Figure 7 9 Position Counter Underflow Overflow QPOSMAX 4 7 5 1 3 Position Counter Reset on the First Index Event QEPCTL PCRM 10 If the index event occurs during forward movement then...

Page 474: ...mple the 1000 line encoder must count 4000 times when moving in the same direction between the index events The index event latch interrupt flag QFLG IEL is set when the position counter is latched to...

Page 475: ...d on the falling edge of the strobe input for reverse direction as shown in Figure 7 11 The strobe event latch interrupt flag QFLG SEL is set when the position counter is latched to the QPOSSLAT regis...

Page 476: ...writing a 1 to the QEPCTL SWI bit This bit is not automatically cleared While the bit is still set if a 1 is written to it again the position counter will be re initialized 7 5 4 eQEP Position compar...

Page 477: ...it fields POSCMP 2 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 eQEP counter PCEVNT PCSOUT active HIGH PCSOUT active LOW PCSPW Figure 7 13 eQEP Position compare Event Generation Points The pulse stretcher logic...

Page 478: ...s have occurred between unit position events No direction change between unit position events If the QEP capture timer overflows between unit position events then it sets the QEP capture overflow flag...

Page 479: ...7 15 eQEP Edge Capture Unit Note The QCAPCTL UPPS prescaler should not be modified dynamically such as switching the unit event prescaler from QCLK 4 to QCLK 8 Doing so may result in undefined behavi...

Page 480: ...asurement QCAPCTL UPPS 0010 X x k 1 T t k t k 1 T QEPA QEPB QCLK QPOSCNT UPEVNT QCTMR UTOUT x k Figure 7 17 eQEP Edge Capture Unit Timing Details Enhanced Quadrature Encoder Pulse eQEP www ti com 480...

Page 481: ...X are configured using the QUPRD and QCAPCTL UPPS registers Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT registers Parameter Relevant Register to C...

Page 482: ...heral includes a 32 bit timer QUTMR that is clocked by SYSCLKOUT to generate periodic interrupts for velocity calculations see Figure 7 19 Whenever the unit timer QUTMR matches the unit period registe...

Page 483: ...is set and 3 Global interrupt status flag bit QFLG INT had been cleared for previously generated interrupt event The interrupt service routine will need to clear the global interrupt flag bit and the...

Page 484: ...Unit Timer Go 10h QUPRD QEP Unit Period Go 12h QWDTMR QEP Watchdog Timer Go 13h QWDPRD QEP Watchdog Period Go 14h QDECCTL Quadrature Decoder Control Go 15h QEPCTL QEP Control Go 16h QCAPCTL Qaudrature...

Page 485: ...l m n When these variables are used in a register name an offset or an address they refer to the value of a register array where the register is part of a group of repeating registers The register gr...

Page 486: ...of QEPCTL is zero Once the position counter is enabled QPEN bit is one writing to the eQEP position counter register QPOSCNT may cause unexpected results Reset type SYSRSn 7 10 2 2 QPOSINIT Register O...

Page 487: ...riptions Bit Field Type Reset Description 31 0 QPOSCMP R W 0h Position Compare The position compare value in this register is compared with the position counter QPOSCNT to generate sync output and or...

Page 488: ...Register Field Descriptions Bit Field Type Reset Description 31 0 QPOSLAT R 0h Position Latch The position counter value is latched into this register on a unit time out event Reset type SYSRSn 7 10...

Page 489: ...et type SYSRSn 7 10 2 10 QWDTMR Register Offset 12h reset 0h QEP Watchdog Timer Figure 7 30 QWDTMR Register 15 14 13 12 11 10 9 8 QWDTMR R W 0h 7 6 5 4 3 2 1 0 QWDTMR R W 0h Table 7 15 QWDTMR Register...

Page 490: ...15 0 QWDPRD R W 0h QEP Watchdog Period This register contains the time out count for the eQEP peripheral watch dog timer When the watchdog timer value matches the watchdog period value a watchdog time...

Page 491: ...utput 12 SPSEL R W 0h Sync output pin selection Reset type SYSRSn 0h R W Index pin is used for sync output 1h R W Strobe pin is used for sync output 11 XCR R W 0h External Clock Rate Reset type SYSRSn...

Page 492: ...effect 1h R W Negates QEPI input 5 QSP R W 0h QEPS input polarity Reset type SYSRSn 0h R W No effect 1h R W Negates QEPS input 4 0 RESERVED R 0h Reserved Enhanced Quadrature Encoder Pulse eQEP www ti...

Page 493: ...counts until WD period match roll over 1h R W QUTMR behavior Unit timer counts until period rollover 1h R W QCTMR behavior Capture Timer counts until next unit period event 2h R W QPOSCNT behavior Pos...

Page 494: ...t is not cleared automatically 6 SEL R W 0h Strobe event latch of position counter Reset type SYSRSn 0h R W The position counter is latched on the rising edge of QEPS strobe QPOSSLAT POSCCNT Latching...

Page 495: ...n position counter read by CPU Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register 1h R W Latch on unit time out Position count...

Page 496: ...T 2 2h R W CAPCLK SYSCLKOUT 4 3h R W CAPCLK SYSCLKOUT 8 4h R W CAPCLK SYSCLKOUT 16 5h R W CAPCLK SYSCLKOUT 32 6h R W CAPCLK SYSCLKOUT 64 7h R W CAPCLK SYSCLKOUT 128 3 0 UPPS R W 0h Unit position event...

Page 497: ...SRSn 0h R W Load on QPOSCNT 0 1h R W Load when QPOSCNT QPOSCMP 13 PCPOL R W 0h Polarity of sync output Reset type SYSRSn 0h R W Active HIGH pulse output 1h R W Active LOW pulse output 12 PCE R W 0h Po...

Page 498: ...W 0h Position compare match interrupt enable Reset type SYSRSn 0h R W Interrupt is disabled 1h R W Interrupt is enabled 7 PCR R W 0h Position compare ready interrupt enable Reset type SYSRSn 0h R W I...

Page 499: ...abled 1h R W Interrupt is enabled 1 PCE R W 0h Position counter error interrupt enable Reset type SYSRSn 0h R W Interrupt is disabled 1h R W Interrupt is enabled 0 RESERVED R 0h Reserved www ti com En...

Page 500: ...match event interrupt flag Reset type SYSRSn 0h R W No interrupt generated 1h R W Interrupt was generated 7 PCR R 0h Position compare ready interrupt flag Reset type SYSRSn 0h R W No interrupt generat...

Page 501: ...sition counter error interrupt flag Reset type SYSRSn 0h R W No interrupt generated 1h R W Interrupt was generated 0 INT R 0h Global interrupt status flag Reset type SYSRSn 0h R W No interrupt generat...

Page 502: ...rrupt flag 8 PCM R 0 W1S 0h Clear eQEP compare match event interrupt flag Reset type SYSRSn 0h R W No effect 1h R W Clears the interrupt flag 7 PCR R 0 W1S 0h Clear position compare ready interrupt fl...

Page 503: ...W1S 0h Clear position counter error interrupt flag Reset type SYSRSn 0h R W No effect 1h R W Clears the interrupt flag 0 INT R 0 W1S 0h Global interrupt clear flag Reset type SYSRSn 0h R W No effect 1...

Page 504: ...e interrupt 8 PCM R W 0h Force position compare match interrupt Reset type SYSRSn 0h R W No effect 1h R W Force the interrupt 7 PCR R W 0h Force position compare ready interrupt Reset type SYSRSn 0h R...

Page 505: ...effect 1h R W Force the interrupt 1 PCE R W 0h Force position counter error interrupt Reset type SYSRSn 0h R W No effect 1h R W Force the interrupt 0 RESERVED R 0h Reserved www ti com Enhanced Quadrat...

Page 506: ...e movement 1h R W Clockwise rotation or forward movement 4 QDLF R 0h eQEP direction latch flag Reset type SYSRSn 0h R W Counter clockwise rotation or reverse movement on index event marker 1h R W Cloc...

Page 507: ...riptions Bit Field Type Reset Description 15 0 QCTMR R W 0h This register provides time base for edge capture unit Reset type SYSRSn 7 10 2 22 QCPRD Register Offset 1Eh reset 0h QEP Capture Period Fig...

Page 508: ...7 10 2 24 QCPRDLAT Register Offset 20h reset 0h QEP Capture Period Latch Figure 7 44 QCPRDLAT Register 15 14 13 12 11 10 9 8 QCPRDLAT R 0h 7 6 5 4 3 2 1 0 QCPRDLAT R 0h Table 7 29 QCPRDLAT Register F...

Page 509: ...n Support 519 8 4 ADC Conversion Priority 520 8 5 Sequential Sampling Mode 523 8 6 Simultaneous Sampling Mode 523 8 7 EOC and Interrupt Operation 524 8 8 Power Up Sequence 525 8 9 ADC Calibration 525...

Page 510: ...OCs or Start Of Conversions Functions of the ADC module include 12 bit ADC core with built in dual sample and hold S H Simultaneous sampling or sequential sampling modes Full range analog input 0 V to...

Page 511: ...eo TI Precision Labs Analog to digital converter ADC drive topologies Video TI Precision Labs Electrical overstress on data converters Video TI Precision Labs High speed ADC fundamentals Video TI Prec...

Page 512: ...NB5 ADCINB6 ADCINB7 3 4 5 6 7 RESULT Registers VREFLO 0 1 VREFLO VREFHI Int Gain Trim Bandgap Reference Circuit Ext Gain Trim ADCCTL1 ADCREFSEL 0 1 SOCx Signals SOC ADC Interrupt Logic EOCx CHSEL CHSE...

Page 513: ...SEL SOC SOC0 ADCSOCFRC 1 SOC0 0 1 12 2 ADCTRIG1 ADCTRIG2 ADCTRIG12 0 1 2 3 ADCINT1 ADCINT2 undefined ADCSOC2CTL CHSEL ADCSOC0CTL CHSEL Latch Set Clear SOCOVF ADCSOCFLG1 SOC0 ADCSOC15CTL ACQPS ADCSOC0C...

Page 514: ...to a proper value to obtain correct frequency of operation For more information on the ADCCTL2 register refer to Section 8 13 8 2 1 ADC Acquisition Sample and Hold Window External drivers vary in the...

Page 515: ...racterized as being able to meet the settling error and real time requirements of the system using a supported ACQPS setting A low bandwidth source signal is one that requires a longer S H duration th...

Page 516: ...pF Cp 5pF Rs 56 Cs 2 2nF fADCCLK 30MHz The time constant would be calculated as 563 34003 1 6L 563 2200L 5L 5 5JO 123 5JO 129JO And the number of required time constants would be G ln F 212 5 0 25 5 G...

Page 517: ...to at least PO D G Finally tS H is used to determine the minimum value to program into the ACQPS field of the ADCSOCxCTL registers 325 PO D B F 1 Where the following parameters are provided by the AD...

Page 518: ...the maximum source resistance would be calculated and rounded down to a common value 4O 1IO 2 33J 15 2G3 12k3 Now the time constant and multiple k can be calculated as 34003 1 6L 5 4JO G ln F 212 5 0...

Page 519: ...nnels are converted ADCINA0 is shared with VREFHI and therefore cannot be used as a variable input source when using external reference voltage mode See Section 8 10 for details on this mode 8 3 ONESH...

Page 520: ...wo forms of priority determines the order in which they are converted The default priority method is round robin In this scheme no SOC has an inherent higher priority than another Priority depends on...

Page 521: ...C SOC2 SOC12 triggers rcvd simultaneously SOC12 is first on round robin wheel SOC12 configured channel is converted while SOC2 stays pending RRPOINTER changes to point to SOC 12 SOC2 configured channe...

Page 522: ...SOC 2 configured channel is converted while SOC 12 stays pending RRPOINTER stays pointing to 7 SOC12 configured channel is now converted RRPOINTER changes to point to SOC 12 SOC13 is now 1st on round...

Page 523: ...ollowing odd numbered SOCx SOC0 and SOC1 are coupled together with one enable bit SIMULEN0 in this case The coupling behavior is as follows Either SOCx s trigger will start a pair of conversions The p...

Page 524: ...se interrupts can be configured to accept any of the available EOCx signals as its source The configuration of which EOCx is the source is done in the INTSELxNy registers Additionally the ADCINT1 and...

Page 525: ...of internal oscillator settings These settings are embedded into the TI reserved OTP memory as part of a C callable function named Device_cal Called during the startup boot procedure in the Boot ROM t...

Page 526: ...t the maximum input voltage As in offset error gain error can be positive or negative A positive full scale gain error means that the full scale digital result is reached before the maximum voltage is...

Page 527: ...in this mode is Digital Value 0 when Input VREFLO Digital Value 4096 Input VREFLO VREFHI VREFLO when VREFLO Input VREFHI Digital Value 4095 when Input VREFHI All fractional values are truncated 8 11 A...

Page 528: ...inimum 7 ADCCLKs ADCSOCFLG 1 SOC1 ADCSOCFLG 1 SOC2 ADCRESULT 1 EOC0 Pulse EOC1 Pulse EOC2 Pulse 2 ADCCLKs Analog Input SOC1 Sample Window SOC0 Sample Window SOC2 Sample Window Figure 8 9 Timing Exampl...

Page 529: ...1 Result 0 B Latched Conversion 1 A 13 ADC Clocks ADCRESULT 2 50 EOC0 Pulse EOC1 Pulse EOC2 Pulse 1 ADCCLK 2 ADCCLKs 2 ADCCLKs Analog Input B SOC0 Sample B Window SOC2 Sample B Window Analog Input A...

Page 530: ...SULT 1 Result 0 B Latched Conversion 1 A 13 ADC Clocks ADCRESULT 2 50 EOC0 Pulse EOC1 Pulse EOC2 Pulse 2 ADCCLKs 2 ADCCLKs Analog Input B SOC0 Sample B Window SOC2 Sample B Window Analog Input A SOC0...

Page 531: ...ost sample 156ns min X ADC Clocks Conversion 2 13 ADC Clocks Figure 8 12 Timing Example for NONOVERLAP Mode Note The NONOVERLAP bit in the ADCCTL2 register when enabled removes the overlap of sampling...

Page 532: ...or sample into a temperature unit The transfer function to determine a temperature is defined as Temperature sensor Offset Slope Slope C LSB LSB Offset 0 C LSB value Temperature Figure 8 13 Temperatur...

Page 533: ...SEL1N2 bit INT1SEL 1 Connect ADCINT1 to EOC1 AdcRegs INTSEL1N2 bit INT1E 1 Enable ADCINT1 EDIS Sample the temperature sensor AdcRegs ADCSOCFRC1 all 0x03 Sample temp sensor while AdcRegs ADCINTFLG bit...

Page 534: ...er 1 Section 8 13 4 ADCSAMPLEMODE 0x12 1 Sampling Mode Register 1 Section 8 13 5 1 ADCINTSOCSEL1 0x14 1 Interrupt SOC Selection 1 Register for 8 channels 1 Section 8 13 5 2 ADCINTSOCSEL2 0x15 1 Interr...

Page 535: ...eset during a system reset If an ADC module reset is desired at any other time you can do so by writing a 1 to this bit After two clock cycles you can then write the appropriate values to the ADCCTL1...

Page 536: ...nce circuitry is powered down 1 The analog circuitry inside the core is powered up 6 ADCBGPWD Bandgap circuit power down active low 0 Bandgap circuitry is powered down 1 Bandgap buffer s circuitry ins...

Page 537: ...GEND R W Read Write R Read only n value after reset Table 8 5 ADC Control Register 2 ADCCTL2 Field Descriptions Bit Field Value Description 1 15 3 Reserved 0 Reads return a zero writes have no effect...

Page 538: ...DC interrupt pulse generated 1 ADC Interrupt pulse generated If the ADC interrupt is placed in continuous mode INTSELxNy register then further interrupt pulses are generated whenever a selected EOC ev...

Page 539: ...rites have no effect 8 0 ADCINTx x 9 to 1 ADC interrupt Flag Clear Bit 0 No action 1 Clears respective flag bit in the ADCINTFLG register Boundary condition for clearing or setting flag bits If hardwa...

Page 540: ...flow occurred when generating ADCINT pulses If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs 0 No ADC interrupt overflow even...

Page 541: ...Register ADCINTOVFCLR Field Descriptions Bit Field Value Description 15 9 Reserved 0 Reads return a zero Writes have no effect 8 0 ADCINTx x 9 to 1 ADC Interrupt Overflow Clear Bits 0 No action 1 Clea...

Page 542: ...E INT4SEL R 0 R W 0 R W 0 R W 0 7 6 5 4 0 Reserved INT3CONT INT3E INT3SEL R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 8 22 Interrupt Select 5 and 6 Register INTS...

Page 543: ...le 8 11 Interrupt Select Register INTSELxNy Field Descriptions Bit Field Value Description 1 15 Reserved 0 Reserved 14 INTyCONT ADCINTy Continuous Mode Enable 0 No further ADCINTy pulses are generated...

Page 544: ...flag in ADCINTFLG register is cleared by user 1 ADCINTx pulses are generated whenever an EOC pulse is generated irrespective if the flag bit is cleared or not 5 INTxE ADCINTx Interrupt Enable 0 ADCIN...

Page 545: ...convert SOC7 is highest round robin priority 07h SOC7 was last round robin SOC to convert SOC8 is highest round robin priority 08h SOC8 was last round robin SOC to convert SOC9 is highest round robin...

Page 546: ...ority SOC7 SOC15 are in round robin mode 08h SOC0 SOC7 are high priority SOC8 SOC15 are in round robin mode 09h SOC0 SOC8 are high priority SOC9 SOC15 are in round robin mode 0Ah SOC0 SOC9 are high pr...

Page 547: ...ample for SOC12 and SOC13 Lowest three bits of CHSEL field define the pair of channels to be converted EOC12 and EOC13 associated with SOC12 and SOC13 pair SOC12 and SOC13 results will be placed in AD...

Page 548: ...ULT4 and ADCRESULT5 registers respectively 1 SIMULEN2 Simultaneous sampling enable for SOC2 SOC3 Couples SOC2 and SOC3 in simultaneous sampling mode See Section 8 5 for details This bit should not be...

Page 549: ...tected 8 13 5 3 ADC Interrupt Trigger SOC Select 2 Register ADCINTSOCSEL2 Figure 8 28 ADC Interrupt Trigger SOC Select 2 Register ADCINTSOCSEL2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOC15 SOC14 SOC13...

Page 550: ...conversions 0 No sample pending for SOCx 1 Trigger has been received and sample is pending for SOCx The bit will be automatically cleared when the respective SOCx conversion is started If contention...

Page 551: ...e SOCx flag bit in the ADCSOCFLG1 register This can be used to initiate a software initiated conversion Writes of 0 are ignored 0 No action 1 Force SOCx flag bit to 1 This will cause a conversion to s...

Page 552: ...2 ADC SOC Overflow Clear 1 Register ADCSOCOVFCLR1 15 14 13 12 11 10 9 8 SOC15 SOC14 SOC13 SOC12 SOC11 SOC10 SOC9 SOC8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 SOC7 SOC6 SOC5 SOC...

Page 553: ...IG0 Software only 01h ADCTRIG1 CPU Timer 0 TINT0n 02h ADCTRIG2 CPU Timer 1 TINT1n 03h ADCTRIG3 CPU Timer 2 TINT2n 04h ADCTRIG4 XINT2 XINT2SOC 05h ADCTRIG5 ePWM1 ADCSOCA 06h ADCTRIG6 ePWM1 ADCSOCB 07h...

Page 554: ...5 Eh ADCINB6 Fh ADCINB7 Simultaneous Sampling Mode SIMULENx 1 0h ADCINA0 ADCINB0 pair 1h ADCINA1 ADCINB1 pair 2h ADCINA2 ADCINB2 pair 3h ADCINA3 ADCINB3 pair 4h ADCINA4 ADCINB4 pair 5h ADCINA5 ADCINB5...

Page 555: ...s long 6 1 clock cycles 07h Sample window is 8 cycles long 7 1 clock cycles 08h Sample window is 9 cycles long 8 1 clock cycles 09h Sample window is 10 cycles long 9 1 clock cycles 3Fh Sample window i...

Page 556: ...l Bandgap Coarse Trim A maximum value of 30 is supported These bits should not be modified after device boot code loads them with the factory trim setting 1 This register is EALLOW protected 8 13 6 2...

Page 557: ...15 12 Reserved Reads return a zero Writes have no effect 11 COMP3_HYST_ DISABLE Comparator 3 Hysteresis disable 0 Hysteresis enabled 1 Hysteresis disabled 10 7 Reserved Reserved 6 COMP2_HYST_ DISABLE...

Page 558: ...Registers ADCRESULTx Field Descriptions Bit Field Value Description 15 12 Reserved Reads return a zero Writes have no effect 11 0 RESULT 12 bit right justified ADC result Sequential Sampling Mode SIMU...

Page 559: ...for a list of device specific differences within a type 9 1 Introduction 560 9 2 Comparator Function 561 9 3 DAC Reference 561 9 4 Ramp Generator Input 562 9 5 Initialization 563 9 6 Digital Domain M...

Page 560: ...t is routed to both the ePWM Trip Zone modules as well as the GPIO output multiplexer 9 1 2 Block Diagram Note Comparator hysteresis feedback is enabled by default and may interfere with high impedanc...

Page 561: ...parator after qualification is reflected by the COMPSTS bit in the COMPSTS register The COMPSTS register will not update if the module clock is not enabled 9 3 DAC Reference Each comparator block cont...

Page 562: ...is loaded from RAMPMAXREF_SHDW and the register remains static until the first PWMSYNC signal is received If the COMPSTS bit is set by the comparator while the ramp generator is active the RAMPSTS reg...

Page 563: ...tput They are 1 Inverter circuit Controlled by the CMPINV bit in the COMPCTL register will apply a logical NOT to the output of the comparator This function is asynchronous while its control requires...

Page 564: ...0x05 1 Reserved DACVAL 0x06 1 10 bit DAC Value Section 9 7 4 Reserved 0x07 1 Reserved RAMPMAXREF_ACTIVE 0x08 1 Ramp Generator Maximum Reference Active Section 9 7 5 Reserved 0x09 1 Reserved RAMPMAXRE...

Page 565: ...ssed through 1h Input to the block must be consistent for 2 consecutive clocks before output of Qual block can change 2h Input to the block must be consistent for 3 consecutive clocks before output of...

Page 566: ...Value Description 1 15 14 FREE SOFT Emulation mode behavior Selects ramp generator behavior during emulation suspend 0h Stop immediately 1h Complete current ramp and stop on the next PWMSYNC signal 2...

Page 567: ...e RAMPMAXREF_ACTIVE Register Field Descriptions Bit Field Value Description 15 0 RAMPMAXREFA 0 FFFFh 16 bit maximum reference active value for down ramp generator This value is loaded from RAMPMAXREF_...

Page 568: ...ment Value Shadow RAMPDECVAL_SHDW Register 15 0 RAMPDECVALS R W 0 LEGEND R W Read Write n value after reset Table 9 11 Ramp Generator Decrement Value Shadow RAMPDECVAL_SHDW Register Field Descriptions...

Page 569: ...control loops the main CPU is free to perform other system tasks such as communications and diagnostics This chapter provides an overview of the architectural structure and components of the control...

Page 570: ...l branch and call Data load store operations The CLA program code can consist of up to eight tasks or interrupt service routines The start address of each task is specified by the MVECT registers No l...

Page 571: ...0 16 CPU Read Write Data Bus CLA Execution Register Set CLA Control Register Set MSTF 32 PIE From Shared Peripherals CLA Program Memory MR2 32 MAR1 16 MIOVF 16 MICLR 16 MCTL 16 MICLROVF 16 MEALLOW CLA...

Page 572: ...cations can serve as data memory blocks to the CLA At reset all blocks are mapped to the CPU memory space whereby the CPU can initialize the memory with data tables coefficients and so on for the CLA...

Page 573: ...atically stall if there are memory access conflicts The data write bus has access to the CLA to CPU message RAM CLA data memory and the shared peripherals 10 2 3 Shared Peripherals and EALLOW Protecti...

Page 574: ...a task For example IACK 0x0001 will set bit 0 in the MIFR register to start task 1 Likewise IACK 0x0003 will set bits 0 and 1 in the MIFR register to start task 1 and task 2 The CLA has its own fetch...

Page 575: ...wed from the message RAMs A write protection violation is not generated if the CLA attempts to write to the CPU to CLA message RAM but the write is ignored The arbitration scheme for the message RAMs...

Page 576: ...ram writes are ignored Priority of accesses are highest priority first 1 CLA fetch 2 CPU debug write 3 CPU debug read Note Because the CLA fetch has higher priority than CPU debug reads it is possible...

Page 577: ...access write CPU data write 3 CPU debug access read CPU data read 4 CLA read 10 3 4 Peripheral Registers ePWM HRPWM Comparator eCAP eQEP Accesses to the registers follow these rules If both the CPU an...

Page 578: ...y region in the linker command file System and CLA initialization are performed by the main CPU This would typically be done in C or C but can also include C28x assembly code The main CPU will also co...

Page 579: ...he address is an offset from the base address of the assigned CLA Program memory block Select the task interrupt sources For each task select the interrupt source in the CLA1TASKSRCSELx register If a...

Page 580: ...int in CLA code Insert a CLA breakpoint MDEBUGSTOP instruction into the code where you want the CLA to halt then rebuild and reload the code Because the CLA does not flush its pipeline when you single...

Page 581: ...In this case you have single stepped or halted in task A and the MPC has reached the MSTOP with no tasks pending If task B comes in at this point it will be flagged in the MIFR register but it may or...

Page 582: ...ipeline is very similar to the C28x pipeline with eight stages 1 Fetch 1 F1 During the F1 stage the program read address is placed on the CLA program address bus 2 Fetch 2 F2 During the F2 stage the i...

Page 583: ...to the same location is protected by what is called write followed by read protection This protection automatically stalls the pipeline so that the write will complete before the read In addition som...

Page 584: ...iption for MBCNDD MCCNDD and MRCNDD Example 10 1 Code Fragment For MBCNDD MCCNDD or MRCNDD Instruction 1 I1 Last instruction that can affect flags for the branch call or return operation Instruction 2...

Page 585: ...or there will be a conflict In the case of a conflict the update due to address mode post increment will win and the auxiliary register will not be updated with _X I4 Starting with the 4th instructio...

Page 586: ...be efficiently used for pre processing calculations needed by the task Table 10 3 ADC to CLA Early Interrupt Response ADC Activity CLA Activity F1 F2 D1 D2 R1 R2 E W Sample Sample Sample Conversion Cy...

Page 587: ...MR1 2 MMOV32 MR1 Val MR1 gets the contents of Val MMOV32 completes here MR1 is valid DDF32 completes here MR0 is valid MMPYF32 MR0 MR0 MR1 Any instruction can use MR1 and or MR0 Example 10 4 Multiply...

Page 588: ...assumed to be zero 16FHiHex 16 bit immediate hex value that represents the upper 16 bits of an IEEE 32 bit floating point value Lower 16 bits of the mantissa are assumed to be zero 16FLoHex A 16 bit...

Page 589: ...fore and after instruction execution Some examples are code fragments while other examples are full tasks that assume the CLA is correctly configured and the main CPU has passed it data Operands Each...

Page 590: ...embler will accept both MAR0 and MAR0 0 The mmmm mmmm mmmm mmmm opcode field will be populated with the signed 16 bit pointer offset For example if imm16 is 2 then the opcode field will be 0x0002 Like...

Page 591: ...ummary MABSF32 MRa MRb 32 Bit Floating Point Absolute Value 594 MADD32 MRa MRb MRc 32 Bit Integer Add 595 MADDF32 MRa 16FHi MRb 32 Bit Floating Point Addition 596 MADDF32 MRa MRb 16FHi 32 Bit Floating...

Page 592: ...656 MMOV32 mem32 MSTF Move 32 Bit MSTF Register to Memory 657 MMOV32 MRa mem32 CNDF Conditional 32 Bit Move 658 MMOV32 MRa MRb CNDF Conditional 32 Bit Move 660 MMOV32 MSTF mem32 Move 32 Bit Value fro...

Page 593: ...F32 MRa MRb Convert Unsigned 16 Bit Integer to 32 Bit Floating Point Value 705 MUI32TOF32 MRa mem32 Convert Unsigned 32 Bit Integer to 32 Bit Floating Point Value 706 MUI32TOF32 MRa MRb Convert Unsign...

Page 594: ...lags in the MSTF register Flag TF ZF NF LUF LVF Modified No Yes Yes No No The MSTF register flags are modified as follows NF 0 ZF 0 if MRa 30 23 0 ZF 1 Pipeline This is a single cycle instruction Exam...

Page 595: ...d on the integer results of the operation NF MRa 31 ZF 0 if MRa 31 0 0 ZF 1 Pipeline This is a single cycle instruction Example Given A int32 1 B int32 2 C int32 7 Calculate Y2 A B C _Cla1Task1 MMOV32...

Page 596: ...is the value 1 5 can be represented as 1 5 or 0xBFC0 MRa MRb 16FHi 0 This instruction can also be written as MADDF32 MRa MRb 16FHi Flags This instruction modifies the following flags in the MSTF regi...

Page 597: ...is most useful for representing constants where the lowest 16 bits of the mantissa are 0 Some examples are 2 0 0x40000000 4 0 0x40800000 0 5 0x3F000000 and 1 5 0xBFC00000 The assembler will accept ei...

Page 598: ...uted MNOP Always executed MNOP Always executed MSTOP End of task Example 2 Show the basic operation of MADDF32 Add to MR1 the value 2 0 in 32 bit floating point format Store the result in MR0 MADDF32...

Page 599: ...on LVF 1 if MADDF32 generates an overflow condition Pipeline This is a single cycle instruction Example Given M1 X1 and B1 are 32 bit floating point numbers Calculate Y1 M1 X1 B1 _Cla1Task1 MMOV32 MR0...

Page 600: ...following flags in the MSTF register Flag TF ZF NF LUF LVF Modified No No No Yes Yes The MSTF register flags are modified as follows LUF 1 if MADDF32 generates an underflow condition LVF 1 if MADDF32...

Page 601: ...the contents of MRe and store the result in MRd In parallel move the contents of the 32 bit location mem32 to MRa MRd MRe MRf MRa mem32 Restrictions The destination register for the MADDF32 and the M...

Page 602: ...n A B and C are 32 bit floating point numbers Calculate Y3 A B Y4 A B C _Cla1Task2 MMOV32 MR0 A Load MR0 with A MMOV32 MR1 B Load MR1 with B MADDF32 MR1 MR1 MR0 Add A B MMOV32 MR0 C and in parallel lo...

Page 603: ...eration NF MRa 31 ZF 0 if MRa 31 0 0 ZF 1 Pipeline This is a single cycle instruction Example MMOVIZ MR0 0x5555 MR0 0x5555AAAA MMOVXI MR0 0xAAAA MMOVIZ MR1 0x5432 MR1 0x5432FEDC MMOVXI MR1 0xFEDC 0101...

Page 604: ...NF MRa 31 ZF 0 if MRa 31 0 0 ZF 1 Pipeline This is a single cycle instruction Example Given m2 int32 32 x2 int32 64 b2 int32 128 Calculate m2 m2 2 x2 x2 4 b2 b2 8 _Cla1Task2 MMOV32 MR0 _m2 MR0 32 0x0...

Page 605: ...F 0 0100 LT Less than zero NF 1 0101 LEQ Less than or equal to zero ZF 1 OR NF 1 1010 TF Test flag set TF 1 1011 NTF Test flag not set TF 0 1100 LU Latched underflow LUF 1 1101 LV Latched overflow LVF...

Page 606: ...ange MSTF flags but will have no effect on whether the MBCNDD instruction branches or not This is because the flag modification will occur after the D2 phase of the MBCNDD instruction These instructio...

Page 607: ...I8 I7 I6 I10 I9 I8 I7 I10 I9 I8 I10 I9 I10 Table 10 11 Pipeline Activity For MBCNDD Branch Taken Instruction F1 F2 D1 D2 R1 R2 E W I1 I1 I2 I2 I1 I3 I3 I2 I1 I4 I4 I3 I2 I1 MBCNDD MBCNDD I4 I3 I2 I1...

Page 608: ...end of task if A branch not taken Skip1 MCMPF32 MR0 0 01 Affects flags for 2nd MBCNDD B MNOP MNOP MNOP MBCNDD Skip2 NEQ B If State 0 01 go to Skip2 MNOP Always executed MNOP Always executed MNOP Alway...

Page 609: ...d MMOVXI MR2 RAMPMASK Always executed MOR32 MR1 MR2 Always executed MMOV32 RampState MR1 Execute if A branch not taken MSTOP end of task if A branch not taken Skip1 MMOV32 MR3 SteadyState MMOVXI MR2 S...

Page 610: ...ZF 0 AND NF 0 0011 GEQ Greater than or equal to zero NF 0 0100 LT Less than zero NF 1 0101 LEQ Less than or equal to zero ZF 1 OR NF 1 1010 TF Test flag set TF 1 1011 NTF Test flag not set TF 0 1100...

Page 611: ...structions following MBCNDD are always executed irrespective of whether the branch is taken or not These instructions must not be the following MSTOP MDEBUGSTOP MBCNDD MCCNDD or MRCNDD Instruction 1 I...

Page 612: ...Table 10 13 Pipeline Activity For MCCNDD Call Taken Instruction F1 F2 D1 D2 R1 R2 E W I1 I1 I2 I2 I1 I3 I3 I2 I1 I4 I4 I3 I2 I1 MCCNDD MCCNDD I4 I3 I2 I1 I5 I5 MCCNDD I4 I3 I2 I1 I6 I6 I5 MCCNDD I4 I...

Page 613: ...inued Call Conditional Delayed MRCNDD CNDF www ti com Control Law Accelerator CLA SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedback TMS320x2806x Microcontrollers 613 Copyright 2022 Texa...

Page 614: ...d for this issue The compiler checks the upper bits of the operands by performing a floating point comparison before proceeding to do the integer comparison or subtraction The compiler flag cla_signed...

Page 615: ...pare for Equal Less Than or Greater Than MSUB32 MRa MRb MRc www ti com Control Law Accelerator CLA SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedback TMS320x2806x Microcontrollers 615 Co...

Page 616: ...s positive zero Not a Number NaN will be treated as infinity Flags This instruction modifies the following flags in the MSTF register Flag TF ZF NF LUF LVF Modified No Yes Yes No No The MSTF register...

Page 617: ...is 1 5 can be represented as 1 5 or 0xBFC0 The MCMPF32 instruction is performed as a logical compare operation This is possible because of the IEEE floating point format offsets the exponent Basicall...

Page 618: ...R1 X0 LOOP MMOV32 MR2 MAR1 2 MR2 next element MCMPF32 MR2 MR1 Compare MR2 with MR1 MSWAPF MR1 MR2 GT MR1 MAX MR1 MR2 MADDF32 MR0 MR0 1 0 Decrememt the counter MCMPF32 MR0 0 0 Set clear flags for MBCND...

Page 619: ...MIRUN flag is not cleared and an interrupt is not issued A single step or run operation will continue execution of the task Restrictions The MDEBUGSTOP instruction cannot be placed 3 instructions bef...

Page 620: ...W bit in MSTF only controls access for the CLA while the EALLOW bit in the ST1 register only controls access for the main CPU As with EALLOW the MEALLOW bit is overridden via the JTAG port allowing fu...

Page 621: ...MSTF only controls access for the CLA while the EALLOW bit in the ST1 register only controls access for the main CPU As with EALLOW the MEALLOW bit is overridden via the JTAG port allowing full contr...

Page 622: ...er Flag TF ZF NF LUF LVF Modified No No No Yes Yes The MSTF register flags are modified as follows LUF 1 if MEINVF32 generates an underflow condition LVF 1 if MEINVF32 generates an overflow condition...

Page 623: ...flags in the MSTF register Flag TF ZF NF LUF LVF Modified No No No Yes Yes The MSTF register flags are modified as follows LUF 1 if MEISQRTF32 generates an underflow condition LVF 1 if MEISQRTF32 gen...

Page 624: ...t Square Root Reciprocal Approximation See also MEINVF32 MRa MRb Control Law Accelerator CLA www ti com 624 TMS320x2806x Microcontrollers SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedba...

Page 625: ...g TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle instruction Example MMOVIZ MR0 5 0 MR0 5 0 0x40A00000 MF32TOI16 MR1 MR0 MR1 15 0 MF32TOI16 MR0 0x0005 MR1 31 16 Sign extensio...

Page 626: ...VF Modified No No No No No Pipeline This is a single cycle instruction Example MMOVIZ MR0 0x3FD9 MR0 31 16 0x3FD9 MMOVXI MR0 0x999A MR0 15 0 0x999A MR0 1 7 0x3FD9999A MF32TOI16R MR1 MR0 MR1 15 0 MF32T...

Page 627: ...0A5B Example 2 Given X M and B are IQ24 numbers X IQ24 2 5 0x02800000 M IQ24 1 5 0x01800000 B IQ24 0 5 0xFF800000 Calculate Y X M B Convert M X and B from IQ24 to float _Cla1Task2 MI32TOF32 MR0 _M MR0...

Page 628: ...6 MRb MRa 31 16 0x0000 Flags This instruction does not affect any flags Flag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle instruction Example MMOVIZ MR0 9 0 MR0 9 0 0x41100...

Page 629: ...ags This instruction does not affect any flags Flag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle instruction Example MMOVIZ MR0 0x412C MR0 0x412C MMOVXI MR0 0xCCCD MR0 0xCC...

Page 630: ...nstruction does not affect any flags Flag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle instruction Example MMOVIZ MR0 12 5 MR0 12 5 0x41480000 MF32TOUI32 MR0 MR0 MR0 MF32TO...

Page 631: ...al portion of the 32 bit floating point value in MRb Flags This instruction does not affect any flags Flag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle instruction Example...

Page 632: ...No No No No Pipeline This is a single cycle instruction Example MMOVIZ MR0 0x0000 MR0 31 16 0 0 0x0000 MMOVXI MR0 0x0004 MR0 15 0 4 0 0x0004 MI16TOF32 MR1 MR0 MR1 MI16TOF32 MR0 4 0 0x40800000 MMOVIZ...

Page 633: ...6 Flags This instruction does not affect any flags Flag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle instruction Example Assume A 4 0x0004 B 4 0xFFFC MI16TOF32 MR0 _A MR0 M...

Page 634: ...xFF800000 Calculate Y X M B Convert M X and B from IQ24 to float _Cla1Task3 MI32TOF32 MR0 _M MR0 0x4BC00000 MI32TOF32 MR1 _X MR1 0x4C200000 MI32TOF32 MR2 _B MR2 0xCB000000 MMPYF32 MR0 MR0 0x3380 M 1 1...

Page 635: ...struction does not affect any flags Flag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle instruction Example MMOVIZ MR2 0x1111 MR2 31 16 4369 0x1111 MMOVXI MR2 0x1111 MR2 15 0...

Page 636: ...MRa 31 ZF 0 if MRa 31 0 0 ZF 1 Pipeline This is a single cycle instruction Example Given m2 int32 32 x2 int32 64 b2 int32 128 Calculate m2 m2 2 x2 x2 4 b2 b2 8 _Cla1Task3 MMOV32 MR0 _m2 MR0 32 0x00000...

Page 637: ...ZF NF LUF LVF Modified No Yes Yes No No The MSTF register flags are modified based on the integer results of the operation NF MRa 31 ZF 0 if MRa 31 0 0 ZF 1 Pipeline This is a single cycle instruction...

Page 638: ...e the contents of floating point registers and move from register to memory The destination register for the MMOV32 cannot be the same as the destination registers for the MMACF32 MR3 MR3 MR2 MRd MRe...

Page 639: ...MR1 Y3 M MACF32 MR3 MR2 MR2 MR0 MR1 MR3 A B C MR2 D X3 Y3 MMOV32 MR0 MAR0 In parallel MR0 X4 MMOV32 MR1 MAR1 MR1 Y4 MMPYF32 MR2 MR0 MR1 MR2 E X4 Y4 MADDF32 MR3 MR3 MR2 in parallel MR3 A B C D MADDF32...

Page 640: ...late with Parallel Move MMOV32 _Y1 MR3 Y1 MR3 MSTOP end of task See also MMPYF32 MRa MRb MRc MADDF32 MRd MRe MRf Control Law Accelerator CLA www ti com 640 TMS320x2806x Microcontrollers SPRUH18I JANUA...

Page 641: ...NF LUF LVF Modified No Yes Yes No No The ZF and NF flags are configured on the result of the operation not the result stored in the destination register if MRa MRb ZF 1 NF 0 if MRa MRb ZF 0 NF 0 if M...

Page 642: ...element MMAXF32 MR1 MR2 MR1 MAX MR1 MR2 MADDF32 MR0 MR0 1 0 Decrememt the counter MCMPF32 MR0 0 0 Set clear flags for MBCNDD MNOP MNOP MNOP MBCNDD LOOP NEQ Branch if not equal to zero MMOV32 _Result...

Page 643: ...hex or float as the immediate value That is 1 5 can be represented as 1 5 or 0xBFC0 Special cases for the output from the MMAXF32 operation NaN output will be converted to infinity A denormalized out...

Page 644: ...NF LUF LVF Modified No Yes Yes No No The ZF and NF flags are configured on the result of the operation not the result stored in the destination register if MRa MRb ZF 1 NF 0 if MRa MRb ZF 0 NF 0 if MR...

Page 645: ...2 MAR1 2 MR2 next element MMINF32 MR1 MR2 MR1 MAX MR1 MR2 MADDF32 MR0 MR0 1 0 Decrememt the counter MCMPF32 MR0 0 0 Set clear flags for MBCNDD MNOP MNOP MNOP MBCNDD LOOP NEQ Branch if not equal to zer...

Page 646: ...ex or float as the immediate value That is 1 5 can be represented as 1 5 or 0xBFC0 Special cases for the output from the MMINF32 operation NaN output will be converted to infinity A denormalized outpu...

Page 647: ...s when loading the auxiliary registers I1 and I2 The two instructions following MMOV16 will use MAR0 MAR1 before the update occurs Thus these two instructions will use the old value of MAR0 or MAR1 I3...

Page 648: ...32 MR1 _TABLE_SIZEDivTwoPi MR1 TABLE_SIZE 2 Pi MMPYF32 MR1 MR0 MR1 MR1 rad TABLE_SIZE 2 Pi MMOV32 MR2 _TABLE_MASK MR2 TABLE_MASK MF32TOI32 MR3 MR1 MR3 K int rad TABLE_SIZE 2 Pi MAND32 MR3 MR3 MR2 MR3...

Page 649: ...ad result eval N 1 N break N 28 endloop MMOVZ16 MR0 _ConversionCount I29 Current Conversion MMOV16 MAR1 MR0 _VoltageCLA I30 Next array location MUI16TOF32 MR0 MR0 I31 Convert count to float32 MADDF32...

Page 650: ...y registers I1 and I2 The two instructions following MMOV16 will use MAR0 MAR1 before the update occurs Thus these two instructions will use the old value of MAR0 or MAR1 I3 Loading of an auxiliary re...

Page 651: ...result register may be read on the 36th instruction after the task begins _Cla1Task2 asg 0 N loop MNOP I1 I28 Wait till I36 to read result eval N 1 N break N 28 endloop MMOVZ16 MR0 _ConversionCount I2...

Page 652: ...Value MMOVIZ MR0 0 0 MMOV16 _ConversionCount MR0 MSTOP _ClaT8End Control Law Accelerator CLA www ti com 652 TMS320x2806x Microcontrollers SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedb...

Page 653: ...mmm mmmm mmmm mmmm Opcode for MMOV16 mem16 MAR1 MSW 0111 0110 1100 addr Description Store the contents of MAR0 or MAR1 in the 16 bit memory location pointed to by mem16 mem16 MAR0 Flags No flags MSTF...

Page 654: ...the analog value the ADC will trigger this task early It takes 10 5 ADCCLKs to complete a conversion the ADCCLK being SYSCLK 4 T_sys 1 200MHz 5ns T_adc 4 T_sys 20ns The ADC will take 10 5 4 or 42 SYS...

Page 655: ...MR1 If branch taken restart count MSTOP end of task This task initializes the ConversionCount to zero _Cla1Task8 MMOVIZ MR0 0 0 MMOV16 _ConversionCount MR0 MSTOP _ClaT8End See also MMOVIZ MRa 16FHi M...

Page 656: ...VI16 MAR1 _Y MAR1 points to Y array MNOP Delay for MAR0 MAR1 load MNOP Delay for MAR0 MAR1 load MAR0 valid MMOV32 MR0 MAR0 2 MR0 X0 MAR0 2 MAR1 valid MMOV32 MR1 MAR1 2 MR1 Y0 MAR1 2 MMPYF32 MR2 MR0 MR...

Page 657: ...three cycles later when MCCNDD enters its execution E phase The user must therefore save the old RPC before MCCNDD updates it in the D2 phase that is it must save MSTF three instructions prior to the...

Page 658: ...equal to zero ZF 1 OR NF 1 1010 TF Test flag set TF 1 1011 NTF Test flag not set TF 0 1100 LU Latched underflow LUF 1 1101 LV Latched overflow LVF 1 1110 UNC Unconditional None 1111 UNCF 2 Unconditio...

Page 659: ...MPF32 MR0 MR1 MMOV32 MR2 _M1 EQ if A B MR2 M1 Y M1 X MMOV32 MR2 _M2 NEQ if A B MR2 M2 Y M2 X MMOV32 MR3 _X MMPYF32 MR3 MR2 MR3 Calculate Y MMOV32 _Y MR3 Store Y MSTOP end of task See also MMOV32 MRa M...

Page 660: ...F 1 1010 TF Test flag set TF 1 1011 NTF Test flag not set TF 0 1100 LU Latched underflow LUF 1 1101 LV Latched overflow LVF 1 1110 UNC Unconditional None 1111 UNCF 2 Unconditional with flag modificati...

Page 661: ...R3 8 0 MMOV32 MR1 _A GT true MR1 A 2 0 MMOV32 MR1 _B LT false does not load MR1 MMOV32 MR2 MR1 GT true MR2 MR1 2 0 MMOV32 MR2 MR0 LT false does not load MR2 MSTOP See also MMOV32 MRa mem32 CNDF www ti...

Page 662: ...calls via MCCNDD MSTF mem32 Flags This instruction modifies the following flags in the MSTF register Flag TF ZF NF LUF LVF Modified Yes Yes Yes Yes Yes Loading the status register will overwrite all f...

Page 663: ...A1 Y2 B2 X2 X1 X1 X0 Y2 Y1 Y1 sum _Cla1Task2 MMOV32 MR0 _B2 MR0 B2 MMOV32 MR1 _X2 MR1 X2 MMPYF32 MR2 MR1 MR0 MR2 X2 B2 MMOV32 MR0 _B1 MR0 B1 MMOVD32 MR1 _X1 MR1 X1 X2 X1 MMPYF32 MR3 MR1 MR0 MR3 X1 B1...

Page 664: ...e from Memory with Data Copy See also MMOV32 MRa mem32 CNDF Control Law Accelerator CLA www ti com 664 TMS320x2806x Microcontrollers SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedback Co...

Page 665: ...n floating point representation That is 3 0 can only be represented as 3 0 0x40400000 will result in an error MRa 32F Flags This instruction modifies the following flags in the MSTF register Flag TF Z...

Page 666: ...uxiliary registers I1 and I2 The two instructions following MMOVI16 will use MAR0 MAR1 before the update occurs Thus these two instructions will use the old value of MAR0 or MAR1 I3 Loading of an auxi...

Page 667: ...F2 D1 D2 R1 R2 E W MMOVI16 MAR0 _X MMOVI16 I1 I1 MMOVI16 I2 I2 I1 MMOVI16 I3 I3 I2 I1 MMOVI16 I4 I4 I3 I2 I1 MMOVI16 I5 I5 I4 I3 I2 I1 MMOVI16 I6 I6 I5 I4 I3 I2 I1 MMOVI16 www ti com Control Law Acce...

Page 668: ...er The assembler will only accept a hex immediate value That is 3 0 can only be represented as 0x40400000 3 0 will result in an error MRa 32FHex Flags This instruction modifies the following flags in...

Page 669: ...Register with the Immediate See also MMOVIZ MRa 16FHi MMOVXI MRa 16FLoHex MMOVF32 MRa 32F www ti com Control Law Accelerator CLA SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedback TMS320...

Page 670: ...a floating point register with a constant in which the lowest 16 bits of the mantissa are 0 Some examples are 2 0 0x40000000 4 0 0x40800000 0 5 0x3F000000 and 1 5 0xBFC00000 If a constant requires all...

Page 671: ...ed by MRa MRa 31 16 0 MRa 15 0 mem16 Flags This instruction modifies the following flags in the MSTF register Flag TF ZF NF LUF LVF Modified No Yes Yes No No The MSTF register flags are modified based...

Page 672: ...16 bits of an IEEE 32 bit floating point value The upper 16 bits of MRa will not be modified MMOVXI can be combined with the MMOVIZ instruction to initialize all 32 bits of a MRa register MRa 15 0 16...

Page 673: ...timate 1 X Ye Ye 2 0 Ye X Ye Ye 2 0 Ye X _Cla1Task1 MMOV32 MR1 _Den MR1 Den MEINVF32 MR2 MR1 MR2 Ye Estimate 1 Den MMPYF32 MR3 MR2 MR1 MR3 Ye Den MSUBF32 MR3 2 0 MR3 MR3 2 0 Ye Den MMPYF32 MR2 MR2 MR3...

Page 674: ...will accept either a hex or float as the immediate value That is the value 1 5 can be represented as 1 5 or 0xBFC0 MRa MRb 16FHi 0 This instruction can also be written as MMPYF32 MRa MRb 16FHi Flags...

Page 675: ...MPYF32 MR1 MR1 0x3380 X 1 1 2 24 iqx 2 5 0x40200000 MMPYF32 MR2 MR2 0x3380 B 1 1 2 24 iqb 5 0xBF000000 MMPYF32 MR3 MR0 MR1 M X MADDF32 MR2 MR2 MR3 Y MX B 3 25 0x40500000 Convert Y from float32 to IQ24...

Page 676: ...will accept either a hex or float as the immediate value That is the value 1 5 can be represented as 1 5 or 0xBFC0 MRa MRb 16FHi 0 This instruction can also be written as MMPYF32 MRa 16FHi MRb Flags...

Page 677: ...iqm 1 5 0x3FC00000 MMPYF32 MR1 0x3380 MR1 X 1 1 2 24 iqx 2 5 0x40200000 MMPYF32 MR2 0x3380 MR2 B 1 1 2 24 iqb 5 0xBF000000 MMPYF32 MR3 MR0 MR1 M X MADDF32 MR2 MR2 MR3 Y MX B 3 25 0x40500000 Convert Y...

Page 678: ...00 0000 Description Multiply the contents of two floating point registers with parallel addition of two registers MRa MRb MRc MRd MRe MRf Restrictions The destination register for the MMPYF32 and the...

Page 679: ...MAR0 2 In parallel MR0 X1 MAR0 2 MMOV32 MR1 MAR1 2 MR1 Y1 MAR1 2 MMPYF32 MR3 MR0 MR1 MR3 B X1 Y1 MMOV32 MR0 MAR0 2 In parallel MR0 X2 MAR0 2 MMOV32 MR1 MAR1 2 MR1 Y2 MAR2 2 MMACF32 MR3 MR2 MR2 MR0 MR1...

Page 680: ...t is MRa cannot be the same register as MRd Flags This instruction modifies the following flags in the MSTF register Flag TF ZF NF LUF LVF Modified No Yes Yes Yes Yes The MSTF register flags are modif...

Page 681: ...1 MR0 Multiply A B MMOV32 MR0 C and in parallel load MR0 with C MMPYF32 MR1 MR1 MR0 Multiply A B by C MMOV32 Y2 MR1 and in parallel store A B MMOV32 Y3 MR1 Store the result MSTOP end of task See also...

Page 682: ...MSTF register Flag TF ZF NF LUF LVF Modified No No No Yes Yes The MSTF register flags are modified as follows LUF 1 if MMPYF32 generates an underflow condition LVF 1 if MMPYF32 generates an overflow...

Page 683: ...d the MSUBF32 must be unique That is MRa cannot be the same register as MRd Flags This instruction modifies the following flags in the MSTF register Flag TF ZF NF LUF LVF Modified No No No Yes Yes The...

Page 684: ...Test flag set TF 1 1011 NTF Test flag not set TF 0 1100 LU Latched underflow LUF 1 1101 LV Latched overflow LVF 1 1110 UNC Unconditional None 1111 UNCF 2 Unconditional with flag modification None 1 V...

Page 685: ...0 Ye X _Cla1Task1 MMOV32 MR1 _Den MR1 Den MEINVF32 MR2 MR1 MR2 Ye Estimate 1 Den MMPYF32 MR3 MR2 MR1 MR3 Ye Den MSUBF32 MR3 2 0 MR3 MR3 2 0 Ye Den MMPYF32 MR2 MR2 MR3 MR2 Ye Ye 2 0 Ye Den MMPYF32 MR3...

Page 686: ...k1 MMOVI16 MAR1 _X Start address MUI16TOF32 MR0 _len Length of the array MNOP delay for MAR1 load MNOP delay for MAR1 load MMOV32 MR1 MAR1 2 MR1 X0 LOOP MMOV32 MR2 MAR1 2 MR2 next element MMAXF32 MR1...

Page 687: ...modified based on the integer results of the operation NF MRa 31 ZF 0 if MRa 31 0 0 ZF 1 Pipeline This is a single cycle instruction Example MMOVIZ MR0 0x5555 MR0 0x5555AAAA MMOVXI MR0 0xAAAA MMOVIZ...

Page 688: ...ues not shown are reserved 2 This is the default operation if no CNDF field is specified This condition will allow the ZF and NF flags to be modified when a conditional operation is executed All other...

Page 689: ...return Destination 7 d7 Cannot be stop branch call or return MRCNDD NEQ Return to Instruction 8 if not equal to zero Three instructions after MRCNDD are always executed whether the return is taken or...

Page 690: ...ne Activity For MRCNDD Return Taken Instruction F1 F2 D1 D2 R1 R2 E W d4 d4 d3 d2 d1 I7 I6 I5 d5 d5 d4 d3 d2 d1 I7 I6 d6 d6 d5 d4 d3 d2 d1 i7 d7 d7 d6 d5 d4 d3 d2 d1 MRCNDD MRCNDD d7 d6 d5 d4 d3 d2 d8...

Page 691: ...3 2 1 0 RNDF 32 Reserved TF Reserved ZF NF LUF LVF The VALUE field indicates the value the flag should be set to 0 or 1 Flags This instruction modifies the following flags in the MSTF register Flag T...

Page 692: ...e MPC has reached the MSTOP with no tasks pending If task B comes in at this point it will be flagged in the MIFR register but it may or may not start if you continue to single step through the MSTOP...

Page 693: ...ed and Prioritized I3 I2 New Task Arbitrated and Prioritized I3 I1 I1 I2 I2 I1 I3 I3 I2 I1 I4 I4 I3 I2 I1 I5 I5 I4 I3 I2 I1 I6 I6 I5 I4 I3 I2 I1 I7 I7 I6 I5 I4 I3 I2 I1 etc Example Given A int32 1 B i...

Page 694: ...lags are modified as follows NF MRa 31 ZF 0 if MRa 31 0 0 ZF 1 Pipeline This is a single cycle instruction Example Given A int32 1 B int32 2 C int32 7 Calculate Y2 A B C _Cla1Task3 MMOV32 MR0 _A MR0 1...

Page 695: ...ates an underflow condition LVF 1 if MSUBF32 generates an overflow condition Pipeline This is a single cycle instruction Example Given A B and C are 32 bit floating point numbers Calculate Y2 A B C _C...

Page 696: ...represented as 1 5 or 0xBFC0 MRa 16FHi 0 MRb Flags This instruction modifies the following flags in the MSTF register Flag TF ZF NF LUF LVF Modified No No No Yes Yes The MSTF register flags are modifi...

Page 697: ...SUBF32 MRd MRe MRf MMOV32 MRa mem32 MSUBF32 MRd MRe MRf MMOV32 mem32 MRa MMPYF32 MRa MRb MRc MSUBF32 MRd MRe MRf www ti com Control Law Accelerator CLA SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit D...

Page 698: ...egisters and move from memory to a floating point register MRd MRe MRf MRa mem32 Restrictions The destination register for the MSUBF32 and the MMOV32 must be unique That is MRa cannot be the same regi...

Page 699: ...contents of two floating point registers and move from a floating point register to memory MRd MRe MRf mem32 MRa Flags This instruction modifies the following flags in the MSTF register Flag TF ZF NF...

Page 700: ...1 1010 TF Test flag set TF 1 1011 NTF Test flag not set TF 0 1100 LU Latched underflow LUF 1 1101 LV Latched overflow LVF 1 1110 UNC Unconditional None 1111 UNCF 2 Unconditional with flag modificatio...

Page 701: ...d MMOV32 MR1 MAR1 2 MR1 X0 LOOP MMOV32 MR2 MAR1 2 MR2 next element MCMPF32 MR2 MR1 Compare MR2 with MR1 MSWAPF MR1 MR2 GT MR1 MAX MR1 MR2 MADDF32 MR0 MR0 1 0 Decrememt the counter MCMPF32 MR0 0 0 Set...

Page 702: ...NF 1 1010 TF Test flag set TF 1 1011 NTF Test flag not set TF 0 1100 LU Latched underflow LUF 1 1101 LV Latched overflow LVF 1 1110 UNC Unconditional None 1111 UNCF 2 Unconditional with flag modificat...

Page 703: ...uted MOR32 MR1 MR2 Always executed MMOV32 _RampState MR1 Execute if A branch not taken MSTOP end of task if A branch not taken _Skip1 MMOV32 MR3 _SteadyState MMOVXI MR2 STEADYMASK MOR32 MR3 MR2 MBCNDD...

Page 704: ...the MF32TOI16R UI16R operation will round to nearest even value MRa UI16TOF32 mem16 Flags This instruction does not affect any flags Flag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a si...

Page 705: ...R UI16R operation will round to nearest even value MRa UI16TOF32 MRb Flags This instruction does not affect any flags Flag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle inst...

Page 706: ...b2 are Uint32 numbers x2 Uint32 2 0x00000002 m2 Uint32 1 0x00000001 b2 Uint32 3 0x00000003 Calculate y2 x2 m2 b2 _Cla1Task1 MUI32TOF32 MR0 _m2 MR0 1 0 0x3F800000 MUI32TOF32 MR1 _x2 MR1 2 0 0x40000000...

Page 707: ...lag TF ZF NF LUF LVF Modified No No No No No Pipeline This is a single cycle instruction Example MMOVIZ MR3 0x8000 MR3 31 16 0x8000 MMOVXI MR3 0x1111 MR3 15 0 0x1111 MR3 2147488017 MUI32TOF32 MR3 MR3...

Page 708: ...re modified based on the integer results of the operation NF MRa 31 ZF 0 if MRa 31 0 0 ZF 1 Pipeline This is a single cycle instruction Example MMOVIZ MR0 0x5555 MR0 0x5555AAAA MMOVXI MR0 0xAAAA MMOVI...

Page 709: ...upt Flag Register Section 10 7 3 4 MIOVF 0x0021 1 Yes Yes Interrupt Overflow Flag Register Section 10 7 3 5 MIFRC 0x0022 1 Yes Yes Interrupt Force Register Section 10 7 3 6 MICLR 0x0023 1 Yes Yes Inte...

Page 710: ...MVECT1 2 3 4 5 6 7 8 Field Descriptions Bits Name Value Description 1 15 12 Reserved Any writes to these bit s must always have a value of 0 11 0 MVECT 0000 0FFF Offset of the first instruction in th...

Page 711: ...OW bit This allows the main CPU to efficiently trigger a CLA task through software Examples IACK 0x0001 Write a 1 to MIFRC bit 0 to force task 1 IACK 0x0003 Write a 1 to MIFRC bit 0 and 1 to force tas...

Page 712: ...ot allowed 1 RAM2E 0 CPU data accesses to CLA Data RAM 2 are always allowed RAM2E 1 CPU data accesses to CLA Data RAM 2 are allowed 9 RAM1CPUE CLA Data RAM 1 CPU Access Enable Bit Allow two SYSCLKOUT...

Page 713: ...s have a value of 0 0 PROGE CLA Program Space Enable Allow two SYSCLKOUT cycles between changing this bit and accessing the memory 0 CLA program SARAM is mapped to the main CPU program and data space...

Page 714: ...L1 Register Field Descriptions Bits Field Value 1 Description 2 31 28 PERINT8SEL Task 8 Peripheral Interrupt Input Select 0000 ADCINT8 is the input for interrupt task 8 default 0010 CPU Timer 0 is the...

Page 715: ...EPWM2_INT xxx1 No interrupt source for task 2 3 0 PERINT1SEL Task 1Peripheral Interrupt Input Select 0000 ADCINT1 is the input for interrupt task 1 default 0010 ePWM1 is the input for interrupt task 1...

Page 716: ...execution 4 INT5 Task 5 Interrupt Flag 0 A task 5 interrupt is currently not flagged default 1 A task 5 interrupt has been received and is pending execution 3 INT4 Task 4 Interrupt Flag 0 A task 4 in...

Page 717: ...errupt overflow has not occurred default 1 A task 8 interrupt overflow has occurred 6 INT7 Task 7 Interrupt Overflow Flag 0 A task 7 interrupt overflow has not occurred default 1 A task 7 interrupt ov...

Page 718: ...effect 1 Write a 1 to force the task 8 interrupt 6 INT7 Task 7 Interrupt Force 0 This bit always reads back 0 and writes of 0 have no effect 1 Write a 1 to force the task 7 interrupt 5 INT6 Task 6 Int...

Page 719: ...0 have no effect 1 Write a 1 to clear the task 7 interrupt flag 5 INT6 Task 6 Interrupt Flag Clear 0 This bit always reads back 0 and writes of 0 have no effect 1 Write a 1 to clear the task 6 interru...

Page 720: ...lag 5 INT6 Task 6 Interrupt Overflow Flag Clear 0 This bit always reads back 0 and writes of 0 have no effect 1 Write a 1 to clear the task 6 interrupt overflow flag 4 INT5 Task 5 Interrupt Overflow F...

Page 721: ...ed R 0 7 6 5 4 3 2 1 0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 30 Interrupt Enable Regist...

Page 722: ...ble 0 Task 1 interrupt is disabled default 1 Task 1 interrupt is enabled 1 This register is protected by EALLOW and the dual code security module Control Law Accelerator CLA www ti com 722 TMS320x2806...

Page 723: ...Register MIRUN Field Descriptions Bits Name Value Description 1 15 8 Reserved Any writes to these bit s must always have a value of 0 7 INT8 Task 8 Run Status 0 Task 8 is not executing default 1 Task...

Page 724: ...ister for debug purposes but it can not write to it 10 7 4 2 CLA Status Register MSTF The CLA status register MSTF reflects the results of different operations These are the basic rules for the flags...

Page 725: ...h the MTESTTF instruction is false 1 The condition tested with the MTESTTF instruction is true 5 4 Reserved These two bits may change based on integer results These flags are not however used by the C...

Page 726: ...32 MMACF32 MEINVF32 MEISQRTF32 The MSETFLG and MMOV32 MSTF mem32 instructions can also be used to modify this flag 0 An overflow condition has not been latched 1 An overflow condition has been latched...

Page 727: ...re useful for structuring data into blocks for optimal CPU processing 11 1 Introduction 728 11 2 DMA Overview 728 11 3 Architecture 729 11 4 Pipeline Timing and Throughput 732 11 5 CPU Arbitration 733...

Page 728: ...dependent PIE interrupt to let the CPU know when a DMA transfers has either started or completed Five of the six channels are exactly the same while Channel 1 has one additional feature the ability to...

Page 729: ...AM 8Kx16 L7 I F L7 SARAM 8Kx16 L8 I F L8 SARAM 8Kx16 PF3 I F McBSP Event triggers DMA 6 ch External interrupts CPU timers CPU bus DMA bus PIE INT7 DINT CH1 CH6 CPU ePWM HRPWM registers PF3 I F PF3 I F...

Page 730: ...s PERINTFLG bit the bit stays pending until the priority logic of the state machine starts the burst transfer for that channel Once the burst transfer starts the flag is cleared If a new interrupt tr...

Page 731: ...Full USB USB Endpoint 1 Transmit Empty USB USB Endpoint 2 Receive Full USB USB Endpoint 2 Transmit Empty USB USB Endpoint 3 Receive Full USB USB Endpoint 3 Transmit Empty 11 3 3 DMA Bus The DMA bus ar...

Page 732: ...N 1 Figure 11 4 4 Stage Pipeline With One Read Stall McBSP as source In addition to the pipeline there are a few other behaviors of the DMA that affect it s total throughput A 1 cycle delay is added a...

Page 733: ...n the case of RAM a ping pong scheme can be implemented to avoid the CPU and the DMA accessing the same RAM block concurrently thus avoiding any stalls or corruption issues 11 6 Channel Priority Two p...

Page 734: ...e burst execution is halted and CH1 is serviced for the complete burst count When the CH1 burst is complete execution returns to the channel that was active when the CH1 trigger occurred All other cha...

Page 735: ...ointer The first and default method is by adding the signed value contained in the SRC DST_TRANSFER_STEP register to the appropriate pointer The second is via a process called wrapping where a wrap ad...

Page 736: ...NT register at the beginning of each transfer The TRANSFER_COUNT register keeps track of how many bursts of data the channel has transferred and when it reaches zero the DMA transfer is complete Sourc...

Page 737: ...continue until TRANSFER_COUNT is zero Note When ONESHOT mode is enabled the DMA will continuously transfer bursts of data on the given channel until the TRANSFER_COUNT value is zero This could potent...

Page 738: ...ata Out active DST_ADDR BURST_COUNT ADDR BURST_STEP BURST_ COUNT 0 No BURSTSTS 0 TRANSFER_ COUNT 0 Yes No WRAP_ COUNT 0 Yes No BEG_ADDR WRAP_STEP ADDR BEG_ADDR WRAP_COUNT WRAP_SIZE WRAP_COUNT TRANSFER...

Page 739: ...w registers never change except by software The active registers never change except by hardware and a shadow register is only copied into its own active register never an active register by another n...

Page 740: ...RANSFER_COUNT Transfer Count Register Section 11 9 13 0x1028 SRC_TRANSFER_STEP Source Transfer Step Size Register Section 11 9 14 0x1029 DST_TRANSFER_STEP Destination Transfer Step Size Register Secti...

Page 741: ...Registers 0x10C0 0x10DF Same as above 1 All DMA register writes are EALLOW protected 11 9 1 DMA Control Register DMACTRL EALLOW Protected The DMA control register DMACTRL is shown in Figure 11 7 and...

Page 742: ...ext highest enabled channel 0 HARDRESET 0 Writing a 1 to the hard reset bit resets the whole DMA and aborts any current access similar to applying a device reset Writes of 0 are ignored and this bit a...

Page 743: ...is shown in Figure 11 9 and described in Table 11 5 Figure 11 9 Revision Register REVISION 15 8 7 0 TYPE REV R R LEGEND R W Read Write R Read only n value after reset Table 11 5 Revision Register REVI...

Page 744: ...ld Descriptions Bit Field Value Description 15 1 Reserved Reserved 0 CH1PRIORITY DMA Ch1 Priority This bit selects whether channel 1 has higher priority or not 0 Same priority as all other channels 1...

Page 745: ...e shadow bits and indicate which channel was interrupted by CH1 When CH1 service is completed the shadow bits are copied back to the ACTIVESTS bits If this bit field is zero or the same as the ACTIVES...

Page 746: ...configure the pointer step increment and size to accommodate 32 bit data transfers See Section 11 7 for details 13 12 Reserved Reserved 11 CONTINUOUS Continuous Mode Bit If this bit is set to 1 then D...

Page 747: ...DC 2 2 ADCINT2 None 3 XINT1 None External Interrupts 4 XINT2 None 5 XINT3 None 6 Reserved None No peripheral connection 7 USB0EP1RX None USB 0 8 USB0EP1TX None 9 USB0EP2RX None 10 USB0EP2TX None 11 TI...

Page 748: ...TS Burst Status Bit This bit is set to 1 when a DMA burst transfer begins and the BURST_COUNT is initialized with the BURST_SIZE This bit is cleared to zero when BURST_COUNT reaches zero This bit is a...

Page 749: ...oft Reset Bit Writing a 1 to this bit completes current read write access and places the channel into a default state as follows RUNSTS 0 TRANSFERSTS 0 BURSTSTS 0 BURST_COUNT 0 TRANSFER_COUNT 0 SRC_WR...

Page 750: ...urst count register BURST_COUNT is shown in Figure 11 15 and described in Table 11 11 Figure 11 15 Burst Count Register BURST_COUNT 15 5 4 0 Reserved BURSTCOUNT R 0 R W 0 LEGEND R W Read Write R Read...

Page 751: ...ld Descriptions Bit Field Value Description 15 0 SRCBURSTSTEP These bits specify the source address post increment decrement step size while processing a burst of data 0x0FFF Add 4095 to address 0x000...

Page 752: ...4095 to address 0x0002 Add 2 to address 0x0001 Add 1 to address 0x0000 No address change 0xFFFF Sub 1 from address 0xFFFE Sub 2 from address 0xF000 Sub 4096 from address Only values from 4096 to 4095...

Page 753: ...Protected The source transfer step size register SRC_TRANSFER_STEP is shown in Figure 11 20 and described in Table 11 16 Figure 11 20 Source Transfer Step Size Register SRC_TRANSFER_STEP 15 0 SRCTRANS...

Page 754: ...ead only n value after reset Table 11 17 Destination Transfer Step Size Register DST_TRANSFER_STEP Field Descriptions Bit Field Value Description 15 0 DSTTRANSFERSTEP These bits specify the destinatio...

Page 755: ...d to a number larger than the TRANSFERSIZE bit field 11 9 17 Source Destination Wrap Count Register SCR DST_WRAP_COUNT The source destination wrap count register SCR DST_WRAP_COUNT is shown in Figure...

Page 756: ...Read only n value after reset Table 11 20 Source Destination Wrap Step Size Registers SRC DST_WRAP_STEP Field Descriptions Bit Field Value Description 15 0 WRAPSTEP These bits specify the source begin...

Page 757: ...ed Reserved 21 0 BEGADDR 22 bit address value 11 9 20 Active Source Begin and Current Address Pointer Registers SRC_BEG_ADDR DST_BEG_ADDR The active source begin and current address pointer registers...

Page 758: ...erved Reserved 21 0 ADDR 22 bit address value 11 9 22 Active Destination Begin and Current Address Pointer Registers SRC_ADDR DST_ADDR The active destination begin and current address pointer register...

Page 759: ...expansion using devices such as shift registers display drivers and analog to digital converters ADCs Multi device communications are supported by the master or slave operation of the SPI The port su...

Page 760: ...active high SPI transmits data one half cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal Rising edge without phase delay SPICLK inactive...

Page 761: ...SPIINT RXINT TXINT Registers SPI SPIAENCLK LSPCLK SPISOMI GPIO MUX SPISIMO SPICLK SPISTE Peripheral Bus SYSRS Figure 12 1 SPI CPU Interface www ti com Serial Peripheral Interface SPI SPRUH18I JANUARY...

Page 762: ...on as the first bit of a new transmission The register bit fields that are reset by SPISWRESET are found in Section 12 5 Configuring a GPIO to Emulate SPISTE In many systems a SPI master may be connec...

Page 763: ...that a transmit or receive operation has completed before the previous character has been read from the buffer The OVERRUN_FLAG will generate an interrupt on the SPIINT vector if the OVERRUNINTENA bi...

Page 764: ...peripheral bus This access is limited to 16 bit register read writes Each SPI module can generate two DMA events SPITXDMA and SPIRXDMA The DMA events are controlled by configuring the SPIFFTX TXFFIL a...

Page 765: ...SPISOMI SPISIMO RXFFST TXFFST H RXFFIL TXFFIL SPIRXDMA SPITXDMA Figure 12 3 SPI DMA Trigger Diagram www ti com Serial Peripheral Interface SPI SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document...

Page 766: ...ta slave sends data Master sends dummy data slave sends data The master can initiate data transfer at any time because it controls the SPICLK signal The software however determines how the master dete...

Page 767: ...ripheral Interface Block Diagram www ti com Serial Peripheral Interface SPI SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedback TMS320x2806x Microcontrollers 767 Copyright 2022 Texas Inst...

Page 768: ...4 Data written to SPIDAT or SPITXBUF is transmitted to the network when appropriate edges of the SPICLK signal are received from the network master A character written to the SPITXBUF register will be...

Page 769: ...s any bits that remain from previous transmission s that have been shifted to the left shown in Example 12 1 Example 12 1 Transmission of Bit from SPIRXBUF Conditions 1 Transmission character length 1...

Page 770: ...frequency Refer to the device data sheet for the maximum GPIO toggle frequency Example 12 2 shows how to determine the SPI baud rates Example 12 2 Baud Rate Determination For SPIBRR 3 to 127 SPI Baud...

Page 771: ...nd receives data on the rising edge of the SPICLK signal The selection procedure for the SPI clocking scheme is shown in Table 12 3 Examples of these four clocking schemes relative to transmitted and...

Page 772: ...ded from transmit FIFO only after the last bit of the shift register is shifted out 7 Delayed transfer The rate at which transmit words in the FIFO are transferred to transmit shift register is progra...

Page 773: ...receive and transmit paths within the SPI are connected any data transmitted by the SPI module is also received by itself The application software must take care to perform a dummy read to clear the...

Page 774: ...Table 12 5 3 Wire SPI Pin Configuration Pin Mode SPIPRI TRIWIRE SPICTL TALK SPISIMO SPISOMI Master Mode 4 wire 0 X TX RX 3 pin mode 1 0 RX Disconnect from SPI 1 TX RX Slave Mode 4 wire 0 X RX TX 3 pin...

Page 775: ...equired with the exception of SPISWRESET To change the SPI configuration 1 Clear the SPI Software Reset bit SPISWRESET to 0 to force the SPI to the reset state 2 Configure the SPI as desired Select ei...

Page 776: ...0 CLOCK PHASE 1 B SPISTE K SPICLK signal options A Slave writes 0D0h to SPIDAT and waits for the master to shift out the data B Master sets the slave SPISTE signal low active C Master writes 058h to S...

Page 777: ...path and then transmit dummy data in order to initiate the transfer from the slave Because the TALK bit is 0 unlike in transmit mode the master dummy data does not appear on the SPISIMOx pin and the m...

Page 778: ...e 12 11 Note This configuration is only applicable to slave mode MASTER_SLAVE 0 When the SPI is configured as master MASTER_SLAVE 1 the STEINV bit will have no effect on the SPISTE pin SPIB_STE SPIB_S...

Page 779: ...be modified Table 12 7 SPI_REGS Registers Offset Acronym Register Name Write Protection Section 0h SPICCR SPI Configuration Control Register Section 12 5 2 1 1h SPICTL SPI Operation Control Register S...

Page 780: ...j k l m n When these variables are used in a register name an offset or an address they refer to the value of a register array where the register is part of a group of repeating registers The registe...

Page 781: ...s the SPI operating flags to the reset condition Specifically the RECEIVER OVERRUN Flag bit SPISTS 7 the SPI INT FLAG bit SPISTS 6 and the TXBUF FULL Flag bit SPISTS 5 are cleared SPISTE will become i...

Page 782: ...tput on falling edge and input on rising edge When no SPI data is sent SPICLK is at high level The data input and output edges depend on the value of the CLOCK PHASE bit SPICTL 3 as follows CLOCK PHAS...

Page 783: ...gth 1 Reset type SYSRSn 0h R W 1 bit word 1h R W 2 bit word 2h R W 3 bit word 3h R W 4 bit word 4h R W 5 bit word 5h R W 6 bit word 6h R W 7 bit word 7h R W 8 bit word 8h R W 9 bit word 9h R W 10 bit...

Page 784: ...EIVER_OVERRUN interrupts 3 CLK_PHASE R W 0h SPI Clock Phase Select This bit controls the phase of the SPICLK signal CLOCK PHASE and CLOCK POLARITY SPICCR 6 make four different clocking schemes possibl...

Page 785: ...ode operation If not previously configured as a general purpose I O pin the SPISOMI pin will be put in the high impedance state Master mode operation If not previously configured as a general purpose...

Page 786: ...y set This means that in order to allow new overrun interrupt requests the user must clear this flag bit by writing a 1 to SPISTS 7 each time an overrun condition occurs In other words if the RECEIVER...

Page 787: ...ed word from SPIRXBUF to the Receive FIFO will clear this bit Use the FIFO status or FIFO interrupt bits for similar functionality Reset type SYSRSn 0h R W No full words have been received or transmit...

Page 788: ...ck output on the SPICLK pin If the SPI is a network slave the module receives a clock on the SPICLK pin from the network master Therefore these bits have no effect on the SPICLK signal The frequency o...

Page 789: ...ansferred to SPIRXEMU and SPIRXBUF where it can be read At the same time SPI INT FLAG is set This mirror register was created to support emulation Reading SPIRXBUF clears the SPI INT FLAG bit SPISTS 6...

Page 790: ...of the current character is complete the contents of this register are automatically loaded in SPIDAT and the TX BUF FULL Flag is cleared If no transmission is currently active data written to this r...

Page 791: ...he serial output pin if the TALK bit SPICTL 1 is set When the SPI is operating as a master a data transfer is initiated When initiating a transfer check the CLOCK POLARITY bit SPICCR 6 described in Se...

Page 792: ...Enable Reset type SYSRSn 0h R W SPI FIFO enhancements are disabled 1h R W SPI FIFO enhancements are enabled 13 TXFIFO R W 1h TX FIFO Reset Reset type SYSRSn 0h R W Write 0 to reset the FIFO pointer to...

Page 793: ...YSRSn 0h R W A TX FIFO interrupt request is generated when there are no words remaining in the TX buffer 1h R W A TX FIFO interrupt request is generated when there is 1 word or no words remaining in t...

Page 794: ...pe SYSRSn 0h R W Write 0 does not affect RXFFOVF flag bit Bit reads back a zero 1h R W Write 1 to clear SPIFFRX RXFFOVF 13 RXFIFORESET R W 1h Receive FIFO Reset Reset type SYSRSn 0h R W Write 0 to res...

Page 795: ...s avoids frequent interrupts after reset as the receive FIFO will be empty most of the time Reset type SYSRSn 0h R W A RX FIFO interrupt request is generated when there is 0 or more words in the RX bu...

Page 796: ...er has completed shifting of the last bit This is required to pass on the delay between transfers to the data stream In the FIFO mode TXBUF should not be treated as one additional level of buffer Rese...

Page 797: ...mulation suspend occurs before the start of a transmission that is before the first SPICLK pulse then the transmission will not occur If the emulation suspend occurs after the start of a transmission...

Page 798: ...SPISTEn is active low normal 1h R W SPISTE is active high inverted 0 TRIWIRE R W 0h SPI 3 wire Mode Enable Reset type SYSRSn 0h R W Normal 4 wire SPI mode 1h R W 3 wire SPI mode enabled The unused pin...

Page 799: ...on parity overrun and framing errors The bit rate is programmable to different speeds through a 16 bit baud select register 13 1 Introduction 800 13 2 Architecture 801 13 3 SCI Module Signal Summary 8...

Page 800: ...extra bit to distinguish addresses from data address bit mode only Four error detection flags parity overrun framing and break detection Two wake up multiprocessor modes idle line and address bit Half...

Page 801: ...major registers lower half of Figure 13 2 RXSHF register receiver shift register Shifts data in from SCIRXD pin one bit at a time SCIRXBUF receiver data buffer register Contains data to be read by the...

Page 802: ...o CPU AutoBaud Detect logic SCICTL1 1 SCIFFENA Interrupts Interrupts Figure 13 2 Serial Communications Interface SCI Module Block Diagram 13 4 Configuring Device Pins The GPIO mux registers must be co...

Page 803: ...nd is one to eight bits in length Each character of data is formatted with a start bit one or two stop bits and optional parity and address bits A character of data with its formatting information is...

Page 804: ...is more efficient than the address bit mode for handling blocks that contain more than ten bytes of data The idle line mode should be used for typical non multiprocessor SCI communication The address...

Page 805: ...upt 3 The interrupt service routine compares the received address sent by a remote transmitter to its own 4 If the CPU is being addressed the service routine clears the SLEEP bit and receives the rest...

Page 806: ...is free again SCITXBUF contents are shifted to TXSHF the TXWAKE value is shifted to WUT and then TXWAKE is cleared Because TXWAKE was set to a 1 the start data and parity bits are replaced by an idle...

Page 807: ...AKE after TXSHF and WUT are loaded Can be written to immediately since both TXSHF and WUT are both double buffered 3 Leave the TXWAKE bit set to 0 to transmit non address frames in the block Note As a...

Page 808: ...rity vote Start bit LSB of data SCICLK internal SCIRXD 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 8 SCICLK periods per data bit 8 SCICLK periods per data bit Figure 13 7 SCI Asynchronous Communications Format...

Page 809: ...shift register TXSHF The transmitter is ready for a second character TXRDY goes high and it requests an interrupt to enable an interrupt bit TX INT ENA SCICTL2 bit 0 must be set 4 The program writes a...

Page 810: ...or 9 625 bit periods following a missing stop bit This action sets the BRKDT flag bit SCIRXST bit 5 and initiates an interrupt If the TX INT ENA bit SCICTL2 0 is set the transmitter peripheral interru...

Page 811: ...r SCI characters written to SCITXBUF are queued in to SCI TXFIFO and the characters received in SCI RXFIFO can be read using SCIRXBUF 7 Delayed transfer The rate at which words in the FIFO are transfe...

Page 812: ...2 RXERRINTENA 0 RXINT Receive break BRKDT RX BKINTENA 0 RXINT Data receive RXRDY RX BKINTENA 0 RXINT Transmit empty TXRDY TXINTENA 0 TXINT SCI with FIFO Receive error and receive break RXERR RXERRINTE...

Page 813: ...tect hardware will detect the incoming baud rate and set the ABD bit 4 The auto detect hardware will update the baud rate register with the equivalent baud value hex The logic will also generate an in...

Page 814: ...13 14 2 2 2h SCIHBAUD SCI Baud Rate high Register Section 13 14 2 3 3h SCILBAUD SCI Baud Rate low Register Section 13 14 2 4 4h SCICTL2 SCI Control Register 2 Section 13 14 2 5 5h SCIRXST SCI Receive...

Page 815: ...k l m n When these variables are used in a register name an offset or an address they refer to the value of a register array where the register is part of a group of repeating registers The register...

Page 816: ...address bit is included in the parity calculation if parity is enabled For characters of less than eight bits the remaining unused bits should be masked out of the parity calculation Reset type SYSRS...

Page 817: ...IRXEMU and are padded with leading zeros in SCIRXBUF SCITXBUF doesn t need to be padded with leading zeros Reset type SYSRSn 0h R W SCICHAR_LENGTH_1 1h R W SCICHAR_LENGTH_2 2h R W SCICHAR_LENGTH_3 3h...

Page 818: ...is held in the specified reset state until a 1 is written to SW RESET the bit values following a reset are shown beneath each register diagram in this section Thus after a system reset re enable the S...

Page 819: ...IRXST bit 5 2 BRKDT FE OE and PE unless the address byte is detected SLEEP is not cleared when the address byte is detected Reset type SYSRSn 0h R W Sleep mode disabled 1h R W Sleep mode enabled 1 TXE...

Page 820: ...ck LSPCLK signal and the two baud select registers The SCI uses the 16 bit value of these registers to select one of 64K serial clock rates for the communication modes BRR SCIHBAUD 8 SCILBAUD The SCI...

Page 821: ...ee SCIHBAUD Detailed Description Reset type SYSRSn 13 14 2 5 SCI Control Register 2 SCICTL2 Offset 4h reset C0h SCICTL2 enables the receive ready break detect and transmit ready interrupts as well as...

Page 822: ...1 RXBKINTENA R W 0h Receiver buffer break interrupt enable This bit controls the interrupt request caused by either the RXRDY flag or the BRKDT flag bits SCIRXST 6 and 5 being set However RX BK INT EN...

Page 823: ...lag s set 6 RXRDY R 0h SCI receiver ready flag When a new character is ready to be read from the SCIRXBUF register the receiver sets this bit and a receiver interrupt is generated if the RX BK INT ENA...

Page 824: ...a mismatch between the number of 1s and its parity bit The address bit is included in the calculation If parity generation and detection is not enabled the PE flag is disabled and read as 0 The PE bi...

Page 825: ...register SCIRXEMU is not physically implemented it is just a different address location to access the SCIRXBUF register without clearing the RXRDY flag Figure 13 17 SCI Receive Emulation Buffer SCIRX...

Page 826: ...o frame error occurred while receiving the character in bits 7 0 This bit is associated with the character on the top of the FIFO 1h R W A frame error occurred while receiving the character in bits 7...

Page 827: ...1 0 TXDT R W 0h Table 13 16 SCI Transmit Data Buffer SCITXBUF Register Field Descriptions Bit Field Type Reset Description 15 8 RESERVED R 0h Reserved 7 0 TXDT R W 0h Transmit data buffer Reset type...

Page 828: ...FFINTCLR R 0 W1S 0h Transmit FIFO clear Reset type SYSRSn 0h R W Write 0 has no effect on TXFIFINT flag bit Bit reads back a zero 1h R W Write 1 to clear TXFFINT flag in bit 7 5 TXFFIENA R W 0h Transm...

Page 829: ...word is lost 14 RXFFOVRCLR R 0 W1S 0h RXFFOVF clear Reset type SYSRSn 0h R W Write 0 has no effect on RXFFOVF flag bit Bit reads back a zero 1h R W Write 1 to clear RXFFOVF flag in bit 15 13 RXFIFORES...

Page 830: ...nerates an interrupt whenever the FIFO status bits RXFFST4 0 are greater than or equal to the FIFO level bits RXFFIL4 0 The maximum value that can be assigned to these bits to generate an interrupt ca...

Page 831: ...the delay between every transfer from FIFO transmit buffer to transmit shift register The delay is defined in the number of SCI serial baud clock cycles The 8 bit register could define a minimum dela...

Page 832: ...ermine what occurs when an emulation suspend event occurs for example when the debugger hits a break point The peripheral can continue whatever it is doing free run mode or if in stop mode it can eith...

Page 833: ...ata transmitted or received by the I2C module can have fewer than 8 bits however for convenience a unit of data is called a data byte throughout this document The number of bits in a data byte is sele...

Page 834: ...ew Video Understanding the I2C Bus Application Report Getting Started Materials Configuring the TMS320F280x DSP as an I2C Processor Application Report I2C Buffers Overview Video I2C Dynamic Addressing...

Page 835: ...8 bit FIFO Supports two ePIE interrupts I2Cx Interrupt Any of the following events can be configured to generate an I2Cx interrupt Transmit data ready Receive data ready Register access ready No ackn...

Page 836: ...ndition See the I2CMDR register in Section 14 6 for RM bit information The I2C module consists of the following primary blocks A serial interface one data pin SDA and one clock pin SCL Data registers...

Page 837: ...down the SYSCLK to produce the I2C module clock and this I2C module clock is divided further to produce the I2C master clock on the SCL pin Figure 14 3 shows the clock generation diagram for I2C modul...

Page 838: ...1 5 when the I2C module is a master the I2C module clock is divided down further to use as the master clock on the SCL pin As shown in Figure 14 4 the shape of the master clock depends on two divide...

Page 839: ...e clock see Figure 14 5 The high or low state of the data line SDA should change only when the clock signal on SCL is low Data line stable data Change of data allowed SDA SCL Figure 14 5 Bit Transfer...

Page 840: ...CL The clock pulses are inhibited and SCL is held low when the intervention of the device is required RSFULL 1 in I2CSTR after a byte has been received Master transmitter mode The I2C module is a mast...

Page 841: ...elow I2C Interrupts using I2CIER Addressed as slave AAS Transmit Ready XRDY Receive Ready RRDY FIFO mode 4 Enable and configure TX RX FIFO Configure TX FIFO level TXFFIL Configure RX FIFO level RXFFIL...

Page 842: ...interrupt TXFFINT Yes ACK received Non repeat mode I2CCNT not equal to 0 or Repeat mode More bytes to be transmitted Yes More bytes needs to be transmitted Yes No No more bytes to be transmitted No N...

Page 843: ...bits including MST STT and STP see Section 14 6 The I2C peripheral cannot detect a START or STOP condition while it is in reset IRS 0 The BB bit will remain in the cleared state BB 0 while the I2C per...

Page 844: ...receive 65536 bytes and not 0 bytes Repeat mode When I2CMDR RM 1 I2C module is configured in repeat mode I2CCNT register contents don t determine the number of bytes to be transmitted or received Numb...

Page 845: ...r reset Disabling expanded address I2CMDR XA 0 and free data format I2CMDR FDF 0 enables 7 bit addressing format In this format see Figure 14 10 the first byte after a START condition S consists of a...

Page 846: ...epending on the BC field of I2CMDR No address or data direction bit is sent Therefore the transmitter and the receiver must both support the free data format and the direction of the data must be cons...

Page 847: ...the clock synchronization The wired AND property of SCL means that a device that first generates a low period on SCL overrules the other devices At this high to low transition the clock generators of...

Page 848: ...receiver mode sets the arbitration lost ARBL flag and generates the arbitration lost interrupt request If during a serial transfer the arbitration procedure is still in progress when a repeated START...

Page 849: ...ss in the I2COAR register Figure 14 16 shows the signal routing in digital loopback mode I2CDRR I2CRSR 0 1 I2CSAR I2COAR 0 1 I2CDXR I2CXSR 0 1 0 0 DLB SCL_IN SCL_OUT Address data To internal I2C logic...

Page 850: ...u intend to receive Master receiver mode AND Repeat mode RM 1 in I2CMDR Generate a STOP condition STP 1 in I2CMDR Reset the module IRS 0 in I2CMDR Set the NACKMOD bit of I2CMDR before the rising edge...

Page 851: ...est Interrupt Source XRDYINT Transmit ready condition The data transmit register I2CDXR is ready to accept new data because the previous data has been copied from I2CDXR to the transmit shift register...

Page 852: ...NT The I2C module has a backwards compatibility bit BC in the I2CEMDR register The timing diagram in demonstrates the effect the backwards compatibility bit has on I2C module registers and interrupts...

Page 853: ...IRS in the I2C mode register I2CMDR All status bits in I2CSTR are forced to their default values and the I2C module remains disabled until IRS is changed to 1 The SDA and SCL pins are in the high imp...

Page 854: ...LKH I2C Clock High time Divider Section 14 6 2 5 5h I2CCNT I2C Data Count Section 14 6 2 6 6h I2CDRR I2C Data Receive Section 14 6 2 7 7h I2CSAR I2C Slave Address Section 14 6 2 8 8h I2CDXR I2C Data T...

Page 855: ...Variables i j k l m n When these variables are used in a register name an offset or an address they refer to the value of a register array where the register is part of a group of repeating registers...

Page 856: ...R 0h R W 0h 7 6 5 4 3 2 1 0 OAR R W 0h Table 14 10 I2C Own Address Register I2COAR Field Descriptions Bit Field Type Reset Description 15 10 RESERVED R 0h Reserved 9 0 OAR R W 0h In 7 bit addressing...

Page 857: ...h Transmit data ready interrupt enable bit This bit should not be set when using FIFO mode Reset type SYSRSn 0h R W Interrupt request disabled 1h R W Interrupt request enabled 3 RRDY R W 0h Receive da...

Page 858: ...K sent bit This bit is used when the I2C module is in the receiver mode One instance in which NACKSNT is affected is when the NACK mode is used see the description for NACKMOD in Reset type SYSRSn 0h...

Page 859: ...e following events Data is written to I2CDXR The I2C module is reset 9 AAS R 0h Addressed as slave bit Reset type SYSRSn 0h R W In the 7 bit addressing mode the AAS bit is cleared when receiving a NAC...

Page 860: ...I2CDRR do not affect this bit RRDY is manually cleared To clear this bit write a 1 to it The I2C module is reset 1h R W I2CDRR ready Data has been copied from I2CRSR to I2CDRR 2 ARDY R W1C 0h Registe...

Page 861: ...dgment 0 ARBL R W1C 0h Arbitration lost interrupt flag bit only applicable when the I2C module is a master transmitter ARBL primarily indicates when the I2C module has lost an arbitration contest with...

Page 862: ...14 6 2 5 I2C Clock High time Divider I2CCLKH Register Offset 4h reset 0h I2C Clock high time divider Figure 14 23 I2C Clock High time Divider I2CCLKH Register 15 14 13 12 11 10 9 8 I2CCLKH R W 0h 7 6...

Page 863: ...NT R W 0h 7 6 5 4 3 2 1 0 I2CCNT R W 0h Table 14 15 I2C Data Count I2CCNT Register Field Descriptions Bit Field Type Reset Description 15 0 I2CCNT R W 0h Data count value I2CCNT indicates the number o...

Page 864: ...alue is right justified and the other bits of I2CDRR 7 0 are undefined For example if BC 011 3 bit data size the receive data is in I2CDRR 2 0 and the content of I2CDRR 7 3 is undefined When in the re...

Page 865: ...write 0s to bits 9 7 Figure 14 26 I2C Slave Address Register I2CSAR 15 14 13 12 11 10 9 8 RESERVED SAR R 0h R W 3FFh 7 6 5 4 3 2 1 0 SAR R W 3FFh Table 14 17 I2C Slave Address Register I2CSAR Field D...

Page 866: ...er I2CXSR The CPU cannot access I2CXSR directly From I2CXSR the I2C module shifts the data byte out on the SDA pin one bit at a time When in the transmit FIFO mode the I2CDXR register acts as the tran...

Page 867: ...ACKMOD is cleared Important To send a NACK bit in the next acknowledge cycle you must set NACKMOD before the rising edge of the last data bit 14 FREE R W 0h This bit controls the action taken by the I...

Page 868: ...ave mode or the master mode MST is automatically changed from 1 to 0 when the I2C master generates a STOP condition Reset type SYSRSn 0h R W Slave mode The I2C module is a slave and receives the seria...

Page 869: ...e address transmitted on the SDA pin is the address in I2COAR Note The free data format FDF 1 is not supported in the digital loopback mode 5 IRS R W 0h I2C module reset bit Reset type SYSRSn 0h R W T...

Page 870: ...ber of bits selected with BC must match the data size of the other device Notice that when BC 000b a data byte has 8 bits BC does not affect address bytes which always have 8 bits Note If the bit coun...

Page 871: ...lue corresponding to that interrupt will then be loaded Otherwise the value will stay cleared In the case of an arbitration lost a no acknowledgment condition detected or a stop condition detected a C...

Page 872: ...it affects the timing of the transmit status bits XRDY and XSMT in the I2CSTR register when in slave transmitter mode Check Backwards Compatibility Mode Bit Slave Transmitter diagram for more details...

Page 873: ...t Figure 14 31 I2C Prescaler I2CPSC Register 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 IPSC R W 0h Table 14 22 I2C Prescaler I2CPSC Register Field Descriptions Bit Field Type Reset Descripti...

Page 874: ...0000 Transmit FIFO is empty Note Since these bits are reset to zero the transmit FIFO interrupt flag will be set when the transmit FIFO operation is enabled and the I2C is taken out of reset This will...

Page 875: ...e equal to or less than these bits the TXFFINT flag will be set This will generate an interrupt if the TXFFIENA bit is set Because the I2C on this device has a 4 level transmit FIFO these bits cannot...

Page 876: ...interrupt condition has occurred 6 RXFFINTCLR R 0 W1S 0h Receive FIFO interrupt flag clear bit Reset type SYSRSn 0h R W Writes of zeros have no effect Reads return a zero 1h R W Writing a 1 to this bi...

Page 877: ...Conditions 896 15 5 Multichannel Selection Modes 904 15 6 SPI Operation Using the Clock Stop Mode 912 15 7 Receiver Configuration 919 15 8 Transmitter Configuration 938 15 9 Emulation and Reset Consid...

Page 878: ...e CLKR and FSR get their signals from the CLKX and FSX pads instead of the CLKR and FSR pins 15 1 1 Features of the McBSP The McBSP features Full duplex communication Double buffered transmission and...

Page 879: ...generator synchronization for the case when GSYNC 1 see Section 15 3 3 MFSXA I O Supplying or reflecting the transmit frame sync signal CPU Interrupt Signals MRINT Receive interrupt to CPU MXINT Trans...

Page 880: ...ual Block Diagram of the McBSP 15 2 McBSP Operation This section addresses the following topics Data transfer process Companding compressing and expanding data Clocking and framing data Frame phases M...

Page 881: ...f RSR2 and RSR1 are copied to RBR2 and RBR1 respectively if RBR1 is not full Then the contents of RBR2 and RBR1 are copied to DRR2 and DRR1 respectively unless the previous content of DRR1 has not bee...

Page 882: ...is otherwise unused the serial port transmit and receive sections are reset the companding hardware can compand internal data This can be used to Convert linear to the appropriate law or A law format...

Page 883: ...pin The time for each bit transfer is controlled by the rising or falling edge of a clock signal The receive clock signal CLKR controls bit transfers from the DR pin to the RSR s The transmit clock si...

Page 884: ...bits to 10b for reception RINTM 10b for transmission XINTM 10b 15 2 3 4 1 Detecting Frame Synchronization Pulses Even in Reset State Unlike other serial port interrupt modes this mode can operate whi...

Page 885: ...synchronization pulse is required to initiate a multipacket transfer The McBSP supports operation of the serial port in this fashion by ignoring the successive frame synchronization pulses Data is cl...

Page 886: ...gnals R X DATDLY 01b 1 bit data delay A1 D R X FS R X CLK R X C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 Figure 15 9 Single Phase Frame for a McBSP Data Transfer 15 2 4 3 Dual Phase Frame Example Figure 15 1...

Page 887: ...the first frame P2W12B0 Because a 1 bit data delay has been chosen the transition on the frame sync signal can occur when P2W12B0 is transferred PxWyBz Phase x Word y Bit z P2W12B0 P2W12B1 MDRA P1W1B1...

Page 888: ...gisters provided that DRR1 is not full with previous data When DRR1 receives new data the receiver ready bit RRDY is set in SPCR1 This indicates that received data is ready to be read by the CPU or th...

Page 889: ...s of both DXRs are copied to the transmit shift registers XSRs as described in the next step If DXR2 is not loaded first the previous content of DXR2 is passed to the XSR2 2 When new data arrives in D...

Page 890: ...to accept the next serial word for transmission 15 3 McBSP Sample Rate Generator Each McBSP contains a sample rate generator SRG that can be programmed to generate an internal data clock CLKG and an i...

Page 891: ...s set to 1 CLKRM 1 for reception CLKXM 1 for transmission the corresponding data clock CLKR for reception CLKX for transmission is driven by the internal sample rate generator output clock CLKG The ef...

Page 892: ...rates transitions on CLKG and FSG Signal on MCLKX pin CLKXP 0 in PCR Rising edge on MCLKX pin generates transitions on CLKG and FSG CLKXP 1 in PCR Falling edge on MCLKX pin generates transitions on CL...

Page 893: ...LKG is the output clock of the sample rate generator 15 3 2 2 Controlling the Period Between the Starting Edges of Frame Synchronization Pulses on FSG You can control the amount of time from the start...

Page 894: ...ad by setting FSXM 0 and connecting FSR to FSX externally The sample rate generator clock drives the transmit and receive clocking CLKRM CLKXM 1 in PCR 15 3 3 2 Synchronization Examples Figure 15 19 a...

Page 895: ...am the sample rate generator registers SRGR1 and SRGR2 as required for your application If necessary other control registers can be loaded with desired values provided the respective portion of the Mc...

Page 896: ...e all the bits of the current frame have been received Such a pulse causes data reception to abort and restart If new data has been copied into the RBRs from the RSRs since the last RBR to DRR copy th...

Page 897: ...from reset a minimum of three words must be received before RFULL is set Either of the following events clears the RFULL bit and allows subsequent transfers to be read properly The CPU or DMA controll...

Page 898: ...ame synchronization pulses The figure assumes that the receiver has been started RRST 1 in SPCR1 Case 3 in the figure is the case in which an error occurs Yes No Yes No running Receiver continues igno...

Page 899: ...this bit If you want the McBSP to notify the CPU of receive frame synchronization errors you can set a special receive interrupt mode with the RINTM bits of SPCR1 When RINTM 11b the McBSP sends a rece...

Page 900: ...is overwritten and thus lost 15 4 4 1 Example of Overwrite Condition Figure 15 26 shows what happens if the data in DXR1 is overwritten before being transmitted Initially DXR1 is loaded with data C A...

Page 901: ...GR2 the transmitter generates a single internal FSX pulse in response to a DXR to XSR copy Otherwise the transmitter waits for the next frame synchronization pulse before sending out the next frame on...

Page 902: ...onization pulses The figure assumes that the transmitter has been started XRST 1 in SPCR2 Case 3 in the figure is the case in which an error occurs Yes No Yes No running Transmit stays ignore frame pu...

Page 903: ...y the CPU of frame synchronization errors you can set a special transmit interrupt mode with the XINTM bits of SPCR2 When XINTM 11b the McBSP sends a transmit interrupt XINT request to the CPU each ti...

Page 904: ...mission In the receiver and in the transmitter the 128 available channels are divided into eight blocks that each contain 16 contiguous channels see Table 15 8 through Table 15 10 It is possible to ha...

Page 905: ...The McBSP has one receive multichannel selection mode described in Section 15 5 6 and three transmit multichannel selection modes described in Section 15 5 7 15 5 3 Configuring a Frame for Multichann...

Page 906: ...s an example of alternating between the channels of partition A and the channels of partition B Channels 0 15 have been assigned to partition A and channels 16 31 have been assigned to partition B In...

Page 907: ...15 5 5 Using Eight Partitions For multichannel selection operation in the receiver and or the transmitter you can use eight partitions or two partitions described in Section 15 5 4 If you choose the...

Page 908: ...e receive multichannel selection mode is enabled In this mode Channels can be individually enabled or disabled The only channels enabled are those selected in the appropriate receive channel enable re...

Page 909: ...of MCR2 determines whether 32 channels or 128 channels are selectable in XCERs 11b This mode is used for symmetric transmission and reception All channels are disabled for transmission unless they ar...

Page 910: ...is configured as follows XPHASE 0 Single phase frame required for multichannel selection modes XFRLEN1 0000011b 4 words per frame XWDLEN1 000b 8 bits per word XMCME 0 2 partition mode only partitions...

Page 911: ...1010b All channels enabled only 1 and 3 unmasked Internal FSX W1 DX b XMCM 01b XPABLK 00b XCERA 1010b Only channels 1 and 3 enabled and unmasked DXR1 to XSR1 copy W3 Write to DXR1 W3 XRDY DXR1 to XSR1...

Page 912: ...dedicated slave enable signal communication between the master and slave is determined by the presence or absence of an active shift clock When the McBSP is operating in SPI master mode and the SPIST...

Page 913: ...determine the transmit packet length XWDLEN1 must be equal to RWDLEN1 because in the clock stop mode The McBSP transmit and receive circuits are synchronized to a single clock RWDLEN1 bits of RCR1 Th...

Page 914: ...ansfers are performed this leads to a minimum idle time of two bit periods between each packet transfer B1 B2 B4 B3 B0 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 FSX SPISTE DX or DR SIMO from master CLKX SPICLK...

Page 915: ...KRP 0 B1 B2 B4 B3 B0 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 FSX SPISTE CLKX SPICLK DX or DR SIMO from master DX or DR SOMI from slave A If the McBSP is the SPI master CLKXM 1 SIMO DX If the McBSP is the SPI...

Page 916: ...erator is released from reset wait two sample rate generator clock periods for the McBSP logic to stabilize If the CPU services the McBSP transmit and receive buffers then you can immediately enable t...

Page 917: ...he divide down value for CLKG FSXM 1 The FSX pin is an output pin driven according to the FSGM bit See the TMS320F2833x TMS320F2823x Digital Signal Controllers DSCs for more information FSGM 0 The tra...

Page 918: ...nts McBSP slave CLKX DX DR FSX SPI compliant master SPICLK SPISOMI SPISIMO SPISTE Figure 15 42 SPI Interface With McBSP Used as Slave Table 15 17 Bit Values Required to Configure the McBSP as an SPI S...

Page 919: ...reset see Section 15 7 2 2 Program McBSP registers for the desired receiver operation see Section 15 7 1 3 Take the receiver out of reset see Section 15 7 2 15 7 1 Programming the McBSP Registers for...

Page 920: ...iven low places the receiver transmitter and sample rate generator in reset When the device reset is removed XRS signal released GRST FRST RRST XRST 0 keep the entire serial port in the reset state pr...

Page 921: ...able the Clock Stop Mode Register Bit Name Function Type Reset Value SPCR1 12 11 CLKSTP Clock stop mode R W 00 CLKSTP 0Xb Clock stop mode disabled normal clocking for non SPI mode CLKSTP 10b Clock sto...

Page 922: ...in Table 15 24 For more details see Section 15 5 6 Table 15 24 Register Bit Used to Enable Disable the Receive Multichannel Selection Mode Register Bit Name Function Type Reset Value MCR1 0 RMCM Rece...

Page 923: ...frame can have one or two phases depending on the value that you load into the RPHASE bit If a single phase frame is selected RWDLEN1 selects the length for every serial word received in the frame If...

Page 924: ...0 RFRLEN1 127 Don t care RFRLEN1 1 words 1 0 RFRLEN1 127 0 RFRLEN2 127 RFRLEN1 1 RFRLEN2 1 words 15 7 10 Enable Disable the Receive Frame Synchronization Ignore Function The RFIG bit see Table 15 29...

Page 925: ...word B is not affected by an unexpected pulse R X SYNCERR D R X FS R X CLK R X C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 Frame synchronization ignored Figure 15 44 Unexpected Frame Synchronization Pulse...

Page 926: ...16 DX 8 8 XSR1 Compress Expand DR RBR1 RSR1 Figure 15 45 Companding Processes for Reception and for Transmission 15 7 11 2 Format of Expanded Data For reception the 8 bit compressed data in RBR1 is ex...

Page 927: ...m is solved because receive data is sampled on the first falling edge of MCLKR where an active high internal FSR is detected However data transmission must begin on the rising edge of the internal CLK...

Page 928: ...sed bits in DRR 1 2 are filled with zeros or with sign bits Table 15 33 and Table 15 34 show the effects of various RJUST values The first table shows the effect on an example 12 bit receive data valu...

Page 929: ...ultichannel selection mode interrupt after every 16 channel block boundary has been crossed within a frame and at the end of the frame For details see Section 15 5 7 3 In any other serial transfer cas...

Page 930: ...ed as necessary so that it is synchronized with the input clock on the MCLKR pin FSG pulses FSG only pulses in response to a pulse on the FSR pin The frame synchronization period defined in FPER is ig...

Page 931: ...The signal is then inverted as determined by FSRP before being used as internal FSR Input 0 1 0 Internal FSR is driven by the sample rate generator frame synchronization signal FSG Output FSG is inver...

Page 932: ...tion FSR FSX are inputs to McBSP and FSRP FSXP 1 the external active low frame synchronization signals are inverted before being sent to the receiver internal FSR and transmitter internal FSX Similarl...

Page 933: ...15 39 shows settings for FPER and FWID Figure 15 49 shows a frame synchronization period of 16 CLKG periods FPER 15 or 00001111b and a frame synchronization pulse with an active width of 2 CLKG perio...

Page 934: ...nals including the receive frame synchronization signal are connected internally through multiplexers to the corresponding transmit signals SPCR1 12 11 CLKSTP Clock stop mode R W 00 CLKSTP 0Xb Clock s...

Page 935: ...ple rate generator clock CLKG internal to the McBSP When FSR and FSX are outputs implying that they are driven by the sample rate generator they are generated transition to their active state on the r...

Page 936: ...e Function Type Reset Value SRGR1 7 0 CLKGDV Sample rate generator clock divide down value R W 0000 0001 The input clock of the sample rate generator is divided by CLKGDV 1 to generate the required sa...

Page 937: ...synchronization period defined in FPER is ignored 15 7 21 Set the SRG Clock Mode Choose an Input Clock Table 15 45 Register Bits Used to Set the SRG Clock Mode Choose an Input Clock Register Bit Name...

Page 938: ...pin The polarity determines whether the rising or falling edge of the input clock generates transitions on CLKG and FSG 15 8 Transmitter Configuration To configure the McBSP transmitter perform the f...

Page 939: ...lso generates the frame synchronization signal FSG as programmed in the sample rate generator registers SPCR2 0 XRST Transmitter reset 0 The serial port transmitter is disabled and in the reset state...

Page 940: ...CLKSTP bits determine whether the clock stop mode is on CLKSTP is described in Table 15 50 Table 15 50 Register Bits Used to Enable Disable the Clock Stop Mode Register Bit Name Function Type Reset Va...

Page 941: ...e MCR2 1 0 XMCM Transmit multichannel selection R W 00 XMCM 00b No transmit multichannel selection mode is on All channels are enabled and unmasked No channels can be disabled or masked XMCM 01b All c...

Page 942: ...EN1 101b 32 bits XWDLEN1 11Xb Reserved XCR2 7 5 XWDLEN2 Transmit word length of frame phase 2 R W 000 XWDLEN2 000b 8 bits XWDLEN2 001b 12 bits XWDLEN2 010b 16 bits XWDLEN2 011b 20 bits XWDLEN2 100b 24...

Page 943: ...you load into the XPHASE bit If a single phase frame is selected XPHASE 0 the frame length is equal to the length of phase 1 If a dual phase frame is selected XPHASE 1 the frame length is the length...

Page 944: ...tion see Section 15 4 5 15 8 10 2 Examples Showing the Effects of XFIG Figure 15 51 shows an example in which word B is interrupted by an unexpected frame synchronization pulse when R X FIG 0 In the c...

Page 945: ...oth encode data into 8 bit code words Companded data is always 8 bits wide the appropriate word length bits RWDLEN1 RWDLEN2 XWDLEN1 XWDLEN2 must therefore be set to 0 indicating an 8 bit wide serial d...

Page 946: ...15 8 12 Set the Transmit Data Delay Table 15 59 Register Bits Used to Set the Transmit Data Delay Register Bit Name Function Type Reset Value XCR2 1 0 XDATDLY Transmitter data delay R W 00 XDATDLY 00...

Page 947: ...usly detects the frame synchronization FSX going active high and immediately starts driving the first bit to be transmitted on the DX pin 15 8 12 3 2 Bit Data Delay A data delay of two bit periods all...

Page 948: ...TM 00 XINT generated when XRDY changes from 0 to 1 XINTM 01 XINT generated by an end of block or end of frame condition in a transmit multichannel selection mode In any of the transmit multichannel se...

Page 949: ...ource of Transmit Frame Synchronization Pulses FSXM FSGM Source of Transmit Frame Synchronization FSX Pin Status 0 0 or 1 An external frame synchronization signal enters the McBSP through the FSX pin...

Page 950: ...ctive low frame synchronization signals are inverted before being sent to the receiver internal FSR and transmitter internal FSX Similarly if internal synchronization FSR FSX are output pins and GSYNC...

Page 951: ...CLKG cycles which allows up to 4096 data bits per frame When GSYNC 1 FPER is a don t care value Each pulse on FSG has a width of FWID 1 CLKG cycles The eight bits of FWID allow a pulse width of 1 to 2...

Page 952: ...CLKX is an output to supply the master clock to any slave devices If the McBSP is a slave make sure that CLKXM 0 so that CLKX is an input to accept the master clock signal 15 8 19 Set the Transmit Cl...

Page 953: ...nd internal clocking is selected CLKXM 1 and CLKX is an output pin the internal rising edge triggered clock internal CLKX is inverted before being sent out on the MCLKX pin Similarly the receiver can...

Page 954: ...nue to run when a breakpoint occurs 15 9 2 Resetting and Initializing McBSP 15 9 2 1 McBSP Pin States DSP Reset Versus Receiver Transmitter Reset Table 15 70 shows the state of McBSP pins when the ser...

Page 955: ...coming out of a device reset this step is not required 2 While the serial port is in the reset state program only the McBSP configuration registers not the data registers as required 3 Wait for two c...

Page 956: ...smit frame has two phases Phase 1 has eight 16 bit words Phase 2 has four 12 bit words There is 1 bit data delay between the start of a frame sync pulse and the first data bit transmitted SPCR2 0031h...

Page 957: ...than 16 bits make sure you access DRR2 DXR2 before you access DRR1 DXR1 McBSP activity is tied to accesses of DRR1 DXR1 During the reception of 24 bit or 32 bit words read DRR2 and then read DRR1 Othe...

Page 958: ...py RBR1 to DRR1 copy Word 4 Word 3 Word 2 Word 1 Figure 15 63 8 Bit Data Words Transferred at Maximum Packet Frequency Figure 15 64 shows the McBSP configured to treat this data stream as a continuous...

Page 959: ...tichannel control register 1 Go Eh RCERA Receive channel enable partition A Go Fh RCERB Receive channel enable partition B Go 10h XCERA Transmit channel enable partition A Go 11h XCERB Transmit channe...

Page 960: ...ables are used in a register name an offset or an address they refer to the value of a register array where the register is part of a group of repeating registers The register groups form a hierarchic...

Page 961: ...rd low byte Reset type SYSRSn 15 11 2 DRR1 Register Offset 1h reset 0h DRR1 is shown in Figure 15 66 and described in Table 15 74 Return to the Summary Table DRR1 contains the lower 16 bits of the rec...

Page 962: ...word low byte Reset type SYSRSn 15 11 4 DXR1 Register Offset 3h reset 0h DXR1 is shown in Figure 15 68 and described in Table 15 76 Return to the Summary Table DXR1 contains the lower 16 bits of the...

Page 963: ...red in the high level language debugger When one of the clocks stops the corresponding data transfer transmission or reception stops Reset type SYSRSn 7 FRST R W 0h Frame synchronization logic reset b...

Page 964: ...hanges from 0 to 1 indicating that transmitter is ready to accept new data the content of DXR 1 2 has been copied to XSR 1 2 Regardless of the value of XINTM you can check XRDY to determine whether a...

Page 965: ...oller Reset type SYSRSn 0h R W Transmitter not ready When DXR1 is loaded XRDY is automatically cleared 1h R W Transmitter ready DXR 1 2 is ready to accept new data If both DXRs are needed word length...

Page 966: ...CLKX are supplied by their respective pins or are generated internally depending on the mode bits FSXM and CLKXM 1h R W Enabled Internal receive signals are supplied by internal transmit signals MDRx...

Page 967: ...properly enabled inside the CPU the CPU services the interrupt request otherwise the CPU ignores the request Reset type SYSRSn 0h R W The McBSP sends a receive interrupt RINT request to the CPU when...

Page 968: ...SP sends a receive interrupt request to the CPU when RRDY changes from 0 to 1 Also when RRDY changes from 0 to 1 the McBSP sends a receive synchronization event REVT signal to the DMA controller Reset...

Page 969: ...me The receive frame has only one phase phase 1 1h R W Dual phase frame The receive frame has two phases phase 1 and phase 2 14 8 RFRLEN2 R W 0h Receive frame length 2 1 to 128 words Each frame of rec...

Page 970: ...h R W u law companding 8 bit data MSB received first 3h R W A law companding 8 bit data MSB received first 2 RFIG R W 0h Receive frame synchronization ignore bit If a frame synchronization pulse start...

Page 971: ...See Section 15 7 9 to determine the frame length This length corresponds to the number of words or logical time slots or channels per frame synchronization period Program the RFRLEN fields with w min...

Page 972: ...two phases program XWDLEN2 and XFRLEN2 Reset type SYSRSn 14 8 XFRLEN2 R W 0h Transmit frame length 2 1 to 128 words Each frame of transmit data can have one or two phases depending on value that you...

Page 973: ...ronization ignore bit If a frame synchronization pulse starts the transfer of a new frame before the current frame is fully transmitted this pulse is treated as an unexpected frame synchronization pul...

Page 974: ...e See Section 15 8 9 to determine the frame length This length corresponds to the number of words or logical time slots or channels per frame synchronization period Program the XFRLEN fields with w mi...

Page 975: ...iptions Bit Field Type Reset Description 15 GSYNC R W 0h Clock synchronization mode bit for CLKG GSYNC is used only when the input clock source for the sample rate generator is external on the MCLKR p...

Page 976: ...Rate Generator 0 1 LSPCLK 1 1 Signal on MCLKX pin 12 FSGM R W 0h Sample rate generator transmit frame synchronization mode bit The transmitter can get frame synchronization from the FSX pin FSXM 0 or...

Page 977: ...cy Input clock frequency CLKGDV 1 The input clock is selected by the SCLKME and CLKSM bits SCLKME CLKSM Input Clock For Sample Rate Generator 0 0 Reserved 0 1 LSPCLK 1 0 Signal on MCLKR pin 1 1 Signal...

Page 978: ...transmitter can transmit or withhold data in any of the 32 channels that are assigned to partitions A and B of the transmitter The 128 transmit channels of the McBSP are divided equally among 8 block...

Page 979: ...0h Transmit multichannel selection mode bits XMCM determines whether all channels or only selected channels are enabled and unmasked for transmission Reset type SYSRSn 0h R W No transmit multichannel...

Page 980: ...type SYSRSn 0h R W 2 partition mode Only partitions A and B are used You can control up to 32 channels in the receive multichannel selection mode RMCM 1 Assign 16 channels to partition A with the RPA...

Page 981: ...set type SYSRSn 0h R W Block 1 channels 16 through 31 1h R W Block 3 channels 48 through 63 2h R W Block 5 channels 80 through 95 3h R W Block 7 channels 112 through 127 6 5 RPABLK R W 0h Receive part...

Page 982: ...annel selection mode Channels can be individually enabled or disabled The only channels enabled are those selected in the appropriate receive channel enable registers RCERs The way channels are assign...

Page 983: ...x 15 11 16 RCERB Register Offset Fh reset 0h RCERB is shown in Figure 15 80 and described in Table 15 88 Return to the Summary Table RCERB contains the receive channel enable registers for the B parti...

Page 984: ...multichannel selection when XMCM 10b all channels enabled but masked unless selected Mask the channel that is mapped to XCEx For multichannel selection when XMCM 11b all channels masked unless selecte...

Page 985: ...multichannel selection when XMCM 10b all channels enabled but masked unless selected Mask the channel that is mapped to XCEx For multichannel selection when XMCM 11b all channels masked unless selecte...

Page 986: ...ernally or internally The polarity of the signal on the FSX pin is determined by the FSXP bit Reset type SYSRSn 0h R W Transmit frame synchronization is supplied by an external source via the FSX pin...

Page 987: ...protocol The sample rate generator drives the internal transmit clock CLKX Internal CLKX is reflected on the MCLKX pin to drive the shift clock of the SPI compliant slaves in the system Internal CLKX...

Page 988: ...R W Transmit frame synchronization pulses are active high 1h R W Transmit frame synchronization pulses are active low 2 FSRP R 0h Receive frame synchronization polarity bit FSRP determines the polarit...

Page 989: ...x 15 11 21 RCERD Register Offset 14h reset 0h RCERD is shown in Figure 15 85 and described in Table 15 93 Return to the Summary Table RCERD contains the receive channel enable registers for the D part...

Page 990: ...multichannel selection when XMCM 10b all channels enabled but masked unless selected Mask the channel that is mapped to XCEx For multichannel selection when XMCM 11b all channels masked unless selecte...

Page 991: ...multichannel selection when XMCM 10b all channels enabled but masked unless selected Mask the channel that is mapped to XCEx For multichannel selection when XMCM 11b all channels masked unless selecte...

Page 992: ...x 15 11 25 RCERF Register Offset 18h reset 0h RCERF is shown in Figure 15 89 and described in Table 15 97 Return to the Summary Table RCERF contains the receive channel enable registers for the F part...

Page 993: ...multichannel selection when XMCM 10b all channels enabled but masked unless selected Mask the channel that is mapped to XCEx For multichannel selection when XMCM 11b all channels masked unless selecte...

Page 994: ...multichannel selection when XMCM 10b all channels enabled but masked unless selected Mask the channel that is mapped to XCEx For multichannel selection when XMCM 11b all channels masked unless selecte...

Page 995: ...x 15 11 29 RCERH Register Offset 1Ch reset 0h RCERH is shown in Figure 15 93 and described in Table 15 101 Return to the Summary Table RCERH contains the receive channel enable registers for the H par...

Page 996: ...multichannel selection when XMCM 10b all channels enabled but masked unless selected Mask the channel that is mapped to XCEx For multichannel selection when XMCM 11b all channels masked unless select...

Page 997: ...multichannel selection when XMCM 10b all channels enabled but masked unless selected Mask the channel that is mapped to XCEx For multichannel selection when XMCM 11b all channels masked unless select...

Page 998: ...tions Bit Field Type Reset Description 15 3 RESERVED R 0h Reserved 2 RINT R W 0h Enable for transmit Interrupt Reset type SYSRSn 0h R W Transmit interrupt on XRDY is disabled 1h R W Transmit interrupt...

Page 999: ...is used where appropriate For a given eCAN module the same address space is used for the module registers in all applicable 28xx 28xxx devices Refer to Programming Examples for the TMS320x28xx eCAN th...

Page 1000: ...retransmission of a frame in case of loss of arbitration or error 32 bit time stamp counter synchronized by a specific message communication in conjunction with mailbox 16 Self test mode Operates in a...

Page 1001: ...icrocontrollers from Texas Instruments with some minor changes The eCAN module features several enhancements such as increased number of mailboxes with individual acceptance masks time stamping and so...

Page 1002: ...an 11 bit identifier and extended frames with 29 bit identifier CAN standard data frames contain from 44 to 108 bits and CAN extended data frames contain 64 to 128 bits Furthermore up to 23 stuff bits...

Page 1003: ...CPK is to decode all messages received on the CAN bus and to transfer these messages into a receive buffer Another function is to transmit messages on the CAN bus according to the CAN protocol The mes...

Page 1004: ...highest priority that is ready to be transmitted is transferred into the CPK by the message controller If two mailboxes have the same priority then the mailbox with the higher number is transmitted fi...

Page 1005: ...not used in an application disabled in the CANME register may be used as general purpose data memory by the CPU 16 4 2 1 32 bit Access to Control and Status Registers As indicated in Section 16 4 2 o...

Page 1006: ...n Control CANOPC TX I O Control CANTIOC RX I O Control CANRIOC Time Stamp Counter CANTSC Global Interrupt Flag 1 CANGIF1 Time Out Control CANTOC Time Out Status CANTOS Reserved eCAN A Control and Stat...

Page 1007: ...tifier extension bit IDE MSGID 31 The acceptance mask enable bit AME MSGID 30 The auto answer mode bit AAM MSGID 29 The transmit priority level TPL MSGCTRL 12 8 The remote transmission request bit RTR...

Page 1008: ...h 6174 6175h 6176 6177h 15 6178 6179h 617A 617Bh 617C 617Dh 617E 617Fh 16 6180 6181h 6182 6183h 6184 6185h 6186 6187h 17 6188 6189h 618A 618Bh 618C 618Dh 618E 618Fh 18 6190 6191h 6192 6193h 6194 6195h...

Page 1009: ...7h 60F6h 60F7h 28 6078h 6079h 60B8h 60B9h 60F8h 60F9h 29 607Ah 607Bh 60BAh 60BBh 60FAh 60FBh 30 607Ch 607Dh 60BCh 60BDh 60FCh 60FDh 31 607Eh 607Fh 60BEh 60BFh 60FEh 60FFh 16 6 1 Transmit Mailbox The C...

Page 1010: ...bit of the mailbox is cleared by the CAN module In addition to the TRS bit the RTR bit is also cleared The mailbox needs to be disabled in order to set this bit again 16 6 3 CAN Module Operation in N...

Page 1011: ...0 CCE 0 Configuration mode active CCR 1 CCE 1 Changing of bit timing parameters enabled Normal mode requested CCR 0 CCE 1 Wait for normal mode CCR 0 CCE 1 CCE 1 Initialization complete Normal mode Fi...

Page 1012: ...ed by resynchronization In the eCAN module the length of a bit on the CAN bus is determined by the parameters TSEG1 BTC 6 3 TSEG2 BTC 2 0 and BRP BTC 23 16 TSEG1 combines the two time segments PROP_SE...

Page 1013: ...lustrative purposes only In a real world application parameters such as the oscillator accuracy and the propagation delay introduced by various entities such as the network cable transceivers isolator...

Page 1014: ...CCE bit is set CANES 4 1 proceed to next step otherwise set the CCR bit CANMC 12 1 and wait until CCE bit is set CANES 4 1 4 Program the CANBTC register with the appropriate timing values Make sure th...

Page 1015: ...dles the complete transmission of the CAN message 3 Wait until the transmit acknowledge flag of the corresponding mailbox is set TA 1 1 After a successful transmission this flag is set by the CAN modu...

Page 1016: ...ogrammed with the same value To make sure that no message is lost set the OPC flag for objects 4 and 5 which prevents unread messages from being overwritten If the CAN module must store a received mes...

Page 1017: ...re are two different types of interrupts One type of interrupt is a mailbox related interrupt for example the receive message pending interrupt or the abort acknowledge interrupt The other type of int...

Page 1018: ...IM 0 1 Wake up BOIF0 BOIF1 BOIF BOIM 0 1 Bus off EPIF0 EPIF1 EPIF EPIM 0 1 Error passive WLIF0 WLIF1 WLIF WLIM 0 1 Warning level GIL CANGIM Interrupt level select Interrupt masks Interrupt sources Int...

Page 1019: ...received RMP n 1 in a receive mailbox or transmitted TA n 1 from a transmit mailbox an interrupt is asserted If a mailbox is configured as remote request mailbox CANMD n 1 MSGCTRL RTR 1 an interrupt...

Page 1020: ...Interrupt flag bits can be set in either CANGIF0 or CANGIF1 registers This is determined by either the GIL bit in CANGIM register or MILn bit in the CANMIL register depending on the interrupt under c...

Page 1021: ...ear the transmit acknowledge bit TA 31 0 by writing a 1 to it 16 7 4 3 3 Interrupt Handling Sequence In order for the CPU core to recognize and service CAN interrupts the following must be done in any...

Page 1022: ...when the PDR bit is cleared or if any bus activity is detected on the CAN bus line if the wake up on bus activity is enabled The automatic wake up on bus activity can be enabled or disabled with the c...

Page 1023: ...odule is disabled upon reset 16 7 5 4 Possible Failure Modes External to the CAN Controller Module This section lists some potential failure modes in a CAN based system The failure modes listed are ex...

Page 1024: ...the local acceptance mask are used If the local acceptance mask identifier extension bit is reset LAMI 0 the identifier extension bit stored in the mailbox determines the messages that are received Fi...

Page 1025: ...he identifier of a mailbox is denied and an interrupt write denied interrupt generated if enabled 0 The corresponding mailbox RAM area is disabled for the eCAN however it is accessible to the CPU as n...

Page 1026: ...while the eCAN module tries to clear it the bit is set Setting CANTRS n causes the particular message n to be transmitted Several bits can be set simultaneously Therefore all messages with the TRS bit...

Page 1027: ...ission Request Reset Register CANTRR Field Descriptions Bit Field Value Description 31 0 TRR 31 0 Transmit request reset bits 1 Setting TRRn cancels a transmission request 0 No operation 16 9 5 Transm...

Page 1028: ...coming message overwrites the stored one if the OPC n OPC 31 0 bit is cleared otherwise the next mailboxes are checked for a matching ID If a mailbox is overwritten the corresponding status bit RML n...

Page 1029: ...ritten by a new one in that mailbox 0 No message was lost Note The RMLn bit is cleared by clearing the set RMPn bit 16 9 9 Remote Frame Pending Register CANRFP Whenever a remote frame request is recei...

Page 1030: ...he new data and clear the CDR bit to indicate to the eCAN that the access is finished Until the CDR bit is cleared the transmission of this mailbox is not permitted Therefore the newest data is sent T...

Page 1031: ...e used for the filter In case of a standard frame only the first eleven bits bit 28 to 18 of the identifier and the global acceptance mask are used The IDE bit of the receive mailbox is a don t care a...

Page 1032: ...run in SUSPEND The node would participate in CAN communication normally sending acknowledge generating error frames transmitting receiving data while in SUSPEND 0 SOFT mode The peripheral shuts down d...

Page 1033: ...tivity 0 The module leaves the power down mode only after writing a 0 to the PDR bit 8 CDR Change data field request This bit allows fast data message update 1 The CPU requests write access to the dat...

Page 1034: ...not get an acknowledgment or if there are some other errors it transmits an error frame and then goes to SUSPEND state The TEC is modified accordingly In the second case that is it is suspended after...

Page 1035: ...he CAN module clock BRPreg denotes the register value of the prescaler that is value written into bits 23 16 of the CANBTC register This value is automatically enhanced by 1 when the CAN module access...

Page 1036: ...ines PROP_SEG and PHASE_SEG1 segments TSEG1 PROP_SEG PHASE_SEG1 where PROP_SEG and PHASE_SEG1 are the length of these two segments in TQ units TSEG1reg denotes the register value of time segment 1 tha...

Page 1037: ...d and writes have no effect 24 FE Form error flag 1 A form error occurred on the bus This means that one or more of the fixed form bit fields had the wrong level on the bus 0 No form error detected th...

Page 1038: ...a frame when the suspend mode is activated the module enters suspend mode only at the end of the frame Run mode is when SOFT mode is activated CANMC 16 1 1 The module has entered suspend mode 0 The mo...

Page 1039: ...hing the bus off state the receive error counter is cleared It is then incremented after every 11 consecutive recessive bits on the bus These 11 bits correspond to the gap between two frames on the bu...

Page 1040: ...by the CPU by writing a 1 to the appropriate bit or by clearing the interrupt causing condition The GMIFx flags must be cleared by writing a 1 to the appropriate bit in the CANTA register or the CANRM...

Page 1041: ...25 Global Interrupt Flag 1 Register CANGIF1 31 18 17 16 Reserved MTOF1 TCOF1 R x R 0 RC 0 15 14 13 12 11 10 9 8 GMIF1 AAIF1 WDIF1 WUIF1 RMLIF1 BOIF1 EPIF1 WLIF1 R W 0 R 0 RC 0 RC 0 R 0 RC 0 RC 0 RC 0...

Page 1042: ...a CAN interrupt asserted 0 The CPU write access to the mailbox was successful 12 WUIF0 WUIF1 Wake up interrupt flag 1 During local power down this flag indicates that the module has left sleep mode 0...

Page 1043: ...ND R Read W Write WP Write in EALLOW mode only n value after reset Table 16 22 Global Interrupt Mask Register CANGIM Field Descriptions Bit Field Value Description 31 18 Reserved Reads are undefined a...

Page 1044: ...line is disabled 16 9 15 3 Mailbox Interrupt Mask Register CANMIM There is one interrupt flag available for each mailbox This can be a receive or a transmit interrupt depending on the configuration of...

Page 1045: ...s in the CANOPC register If the corresponding bit OPC n is set to 1 the old message is protected against being overwritten by the new message thus the next mailboxes are checked for a matching ID If n...

Page 1046: ...ANTX pin is used for the CAN transmit functions 0 Reserved 2 0 Reserved Reserved Figure 16 31 RX I O Control Register CANRIOC 31 16 Reserved R x 15 4 3 2 0 Reserved RXFUNC Reserved R 0 RWP 0 LEGEND RW...

Page 1047: ...ending on the setting of CANMD 16 bit a message successfully This is enabled by setting the MBCC bit CANMC 15 Therefore it is possible to use mailbox 16 for global time synchronization of the network...

Page 1048: ...sequentially there can be a delay before the TOS n bit is set 16 9 18 2 1 Message Object Time Out Registers MOTO This register holds the time out value of the TSC by which the corresponding mailbox da...

Page 1049: ...registers and compares them to the time stamp counter value Since all the time out registers are scanned sequentially it is possible that even though a transmit mailbox has timed out the TOSn bit is n...

Page 1050: ...successful This situation must be handled carefully The application should not re transmit a mailbox if the mailbox is sent between the time the interrupt is asserted and the time the ISR is attemptin...

Page 1051: ...28 0 ID 28 0 Message identifier 1 In standard identifier mode if the IDE bit MSGID 31 0 the message identifier is stored in bits ID 28 18 In this case bits ID 17 0 have no meaning 0 In extended identi...

Page 1052: ...12 8 TPL 4 0 Transmit priority level This 5 bit field defines the priority of this mailbox as compared to the other 31 mailboxes The highest number has the highest priority When two mailboxes have the...

Page 1053: ...sabled CANME n CANME 31 0 0 If TRS n TRS 31 0 1 the registers CANMDL n and CANMDH n cannot be written unless CDR CANMC 8 1 with MBNR CANMC 4 0 set to n These settings also apply for a message object c...

Page 1054: ...Area Network CAN www ti com 1054 TMS320x2806x Microcontrollers SPRUH18I JANUARY 2011 REVISED JUNE 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated This page intentionally l...

Page 1055: ...1058 17 3 Initialization and Configuration 1068 17 4 USB Global Interrupts 1069 17 5 USB Registers 1069 Chapter 17 Universal Serial Bus USB Controller www ti com Universal Serial Bus USB Controller SP...

Page 1056: ...agram is shown in Figure 17 1 Packet Encode Decode Endpoint Control EP0 7 Control Transmit Receive Combine Endpoints Host Transaction Scheduler Packet Encode Packet Decode CRC Gen Check FIFO RAM Contr...

Page 1057: ...making any pin capable of reading a 5V input is to use a series resistance in conjunction with the ESD diode clamps already present inside the device on every pin It is recommended to use a 100k seri...

Page 1058: ...t from SUSPEND mode and recognition of start of frame SOF are all described When in device mode IN transactions are controlled by the endpoint transmit interface and uses the transmit endpoint registe...

Page 1059: ...d results may occur Single Packet Buffering If the size of the transmit endpoint s FIFO is less than twice the maximum packet size for this endpoint as set in the USB Transmit Dynamic FIFO Sizing USBT...

Page 1060: ...o the Host controller If the AUTOCL bit in the USB Receive Control and Status Endpoint n High USBRXCSRH n register is set and a maximum sized packet is unloaded from the FIFO the RXRDY and FULL bits a...

Page 1061: ...et is used to indicate the end of a control transfer In normal operation such packets should only be received after the entire length of the device request has been transferred However if the Host sen...

Page 1062: ...ct The USB controller connection to the USB bus is handled by software The USB PHY can be switched between normal mode and non driving mode by setting or clearing the SOFTCONN bit of the USBPOWER regi...

Page 1063: ...errupt IN endpoint 2 Before accessing any device whether for point to point communications or for communications via a hub the relevant USB Receive Functional Address Endpoint n USBRXFUNCADDRn or USB...

Page 1064: ...e of every frame to every 255 frames in 1 frame increments Bulk endpoints do not allow scheduling parameters but do allow for a NAK timeout in the event an endpoint on a device is not responding The U...

Page 1065: ...R register is set the USB Host controller completes the current transaction then stops the transaction scheduler and frame counter No further transactions are started and no SOF packets are generated...

Page 1066: ...rent to the user application code no changes need be made The C28x core only supports 8 bit accesses through a byte intrinsic type This can be used to perform 8 bit reads or writes to the USB controll...

Page 1067: ...xEE __byte int 0x0E 0 0x00EE 0x0F TEST 0xFF __byte int 0x0F 0 0x00FF C28x 16 Bit C28x 32 Bit Access Data Access Data short 0x00 0x1100 long 0x00 0x33221100 short 0x01 0x1100 long 0x01 0x33221100 short...

Page 1068: ...External Power Enable EPEN and Power Fault PFLT were not implemented in hardware Instead it is left up to the user to implement these signals in software Examples of how to implement these signals in...

Page 1069: ...to VBUS via the USB0EPEN signal 17 4 USB Global Interrupts Global interrupt enable flag and clear registers have been added to ensure that no interrupt is missed The USB interrupt can be enabled or b...

Page 1070: ...ss Endpoint 3 Section 17 5 21 0x09A USBTXHUBADDR3 2 R W 0x00 USB Transmit Hub Address Endpoint 3 Section 17 5 22 0x09B USBTXHUBPORT3 2 R W 0x00 USB Transmit Hub Port Endpoint 3 Section 17 5 23 0x09C U...

Page 1071: ...Type Endpoint 3 Section 17 5 41 0x13D USBRXINTERVAL3 2 R W 0x00 USB Host Receive Polling Interval Endpoint 3 Section 17 5 42 0x304 USBRQPKTCOUNT1 2 R W 0x0000 1 USB Request Packet Count in Block Tran...

Page 1072: ...ial considerations when writing this register see the Setting the Device Address in Section 17 2 1 1 4 USBFADDR is shown in Figure 17 3 and described in Table 17 4 Figure 17 3 Function Address Registe...

Page 1073: ...r Management Register USBPOWER in Host Mode Field Descriptions Bit Field Value Description 7 4 Reserved 0 Reserved 3 RESET RESET signaling 0 Ends RESET signaling on the bus 1 Enables RESET signaling o...

Page 1074: ...eserved 0 Reserved 3 RESET RESET signaling 0 Ends RESET signaling on the bus 1 Enables RESET signaling on the bus 2 RESUME RESUME signaling The bit should be cleared by software 10 ms a maximum of 15...

Page 1075: ...EP0 bit of the USBTXIS register Mode s Host Device USBTXIS is shown in Figure 17 6 and described in Table 17 7 Figure 17 6 USB Transmit Interrupt Status Register USBTXIS 15 4 3 2 1 0 Reserved EP3 EP2...

Page 1076: ...17 8 Figure 17 7 USB Receive Interrupt Status Register USBRXIS 15 4 3 2 1 0 Reserved EP3 EP2 EP1 Rsvd R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 17 8 USB Receive...

Page 1077: ...R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 17 9 USB Transmit Interrupt Status Register USBTXIE Field Descriptions Bit Field Value Description 15 4 Reserved Reserved 2 EP2...

Page 1078: ...ite R Read only n value after reset Table 17 10 USB Receive Interrupt Register USBRXIE Field Descriptions Bit Field Value Description 15 4 Reserved Reserved 3 EP3 RX Endpoint 3 Interrupt Enable 0 The...

Page 1079: ...the VBUS Valid threshold during a session 6 SESREQ Session Request 0 No interrupt 1 SESSION REQUEST signaling has been detected 5 DISCON Session Disconnect 0 No interrupt 1 A Device disconnect has be...

Page 1080: ...of frame 0 No interrupt 1 A new frame has started 2 RESET RESET Signaling Detected 0 No interrupt 1 RESET signaling has been detected on the bus 1 RESUME RESUME Signaling Detected This interrupt can o...

Page 1081: ...0 The DISCON interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set 4 CONN Enable Connect...

Page 1082: ...e USBIS register is set 2 RESET RESET Signaling Detected 0 The RESET interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent to the interrupt controller when the RESET...

Page 1083: ...ster USBEPIDX is used with the USBTXFIFOSZ USBRXFIFOSZ USBTXFIFOADD and USBRXFIFOADD registers Mode s Host Device USBEPIDX is shown in Figure 17 15 and described in Table 17 16 Figure 17 15 USB Endpoi...

Page 1084: ...e read using the DEV bit of the USBDEVCTL register The operating speed is determined from the FORCEFS bit 0 No effect 1 Forces the USB controller to enter Host mode when the SESSION bit is set regardl...

Page 1085: ...the bus connection may be read using the DEV bit of the USBDEVCTL register The operating speed is determined from the FORCEFS bit 6 FIFOACC FIFO Access 0 No effect 1 Transfers the packet in the endpoi...

Page 1086: ...e of the FIFO and the expected maximum packet size the FIFOs support either single packet or double packet buffering see Single Packet Buffering in Section 17 2 1 1 2 Burst writing of multiple packets...

Page 1087: ...gress 6 FSDEV Full Speed Device Detected 0 A full speed Device has not been detected on the port 1 A full speed Device has been detected on the port 5 LSDEV Low Speed Device Detected 0 A low speed Dev...

Page 1088: ...ded a session When the USB controller is in SUSPEND mode this bit may be cleared by software to perform a software disconnect 1 The USB controller has started a session When set by software the Sessio...

Page 1089: ...Read only n value after reset Table 17 21 USB Transmit Dynamic FIFO Sizing Register USBTXFIFOSZ Field Descriptions Bit Field Value Description 7 5 Reserved 0 Reserved 4 DPB Double Packet Buffering Sup...

Page 1090: ...e 17 22 USB Receive Dynamic FIFO Sizing Register USBRXFIFOSZ Field Descriptions Bit Field Value Description 7 5 Reserved 0 Reserved 4 DPB Double Packet Buffering Support 0 Single packet buffering is s...

Page 1091: ...FIFOADDR 15 9 8 0 Reserved ADDR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 23 USB Transmit FIFO Start Address Register USBTXFIFOADDR Field Descriptions Bit Field Value De...

Page 1092: ...FOADDR 15 9 8 0 Reserved ADDR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 24 USB Receive FIFO Start Address Register USBRXFIFOADDR Field Descriptions Bit Field Value Descr...

Page 1093: ...Register USBCONTIM Field Descriptions Bit Field Value Description 7 4 WTCON 5h The connect wait field configures the wait required to allow for the user s connect disconnect filter in units of 533 3...

Page 1094: ...s 17 5 20 USB Low Speed Last Transaction to End of Frame Timing Register USBLSEOF offset 0x07E The USB low speed last transaction to end of frame timing 8 bit configuration register USBLSEOF specifies...

Page 1095: ...s Host The USBTXFUNCADDR n registers are shown in Figure 17 27 and described in Table 17 28 Figure 17 27 USB Transmit Functional Address Endpoint n Registers USBTXFUNCADDR n 7 6 0 Reserved ADDR R 0 R...

Page 1096: ...t for each register see Table 17 3 Mode s Host The USBTXHUBADDR n registers are shown in Figure 17 27 and described in Table 17 28 Figure 17 28 USB Transmit Hub Address Endpoint n Registers USBTXHUBAD...

Page 1097: ...the specific offset for each register see Table 17 3 Mode s Host The USBTXHUBPORTn registers are shown in Figure 17 29 and described in Table 17 30 Figure 17 29 USB Transmit Hub Port Endpoint n Regis...

Page 1098: ...17 3 Mode s Host The USBRXFUNCADDR n registers are shown in Figure 17 30 and described in Table 17 31 Figure 17 30 USB Receive Functional Address Endpoint n Registers USBFIFO n 7 6 0 Reserved ADDR R...

Page 1099: ...s are shown in Figure 17 31 and described in Table 17 32 Figure 17 31 USB Receive Hub Address Endpoint n Registers USBRXHUBADDR n 7 6 0 MULTTRAN ADDR R w 0 R W 0 LEGEND R W Read Write n value after re...

Page 1100: ...he specific offset for each register see Table 17 3 Mode s Host The USBRXHUBPORTn registers are shown in Figure 17 32 and described in Table 17 33 Figure 17 32 USB Transmit Hub Port Endpoint n Registe...

Page 1101: ...e endpoint the transmit endpoint FIFO must be completely flushed using the FLUSH bit in USBTXCSRLn after writing the new value to this register Note USBTXMAXP n must be set to an even number of bytes...

Page 1102: ...the same time as the TXRDY or REQPKT bit is set This bit is automatically cleared when the STATUS stage is over 5 REQPKT Request Packet This bit is cleared when the RXRDY bit is set 0 No request 1 Req...

Page 1103: ...o this bit clears the SETEND bit 6 RXRDYC RXRDY Clear 0 No effect 1 Writing a 1 to this bit clears the RXRDY bit 5 STALL Send Stall 0 No effect 1 Terminates the current transaction and transmits the S...

Page 1104: ...t after loading an IN data packet into the TX FIFO The EP0 bit in the USBTXIS register is also set in this situation 0 RXRDY Receive Packet Ready 0 No receive packet has been received 1 A data packet...

Page 1105: ...not be written 1 Enables the current state of the endpoint 0 data toggle to be written see DT bit 1 DT Data Toggle When read this bit indicates the current state of the endpoint 0 data toggle If DTWE...

Page 1106: ...e Description 7 1 Reserved 0 Reserved 0 FLUSH Flush FIFO This bit is automatically cleared after the flush is performed 0 No effect 1 Flushes the next packet to be transmitted read from the endpoint 0...

Page 1107: ...ed data bytes in the endpoint 0 FIFO 17 5 31 USB Type Endpoint 0 Register USBTYPE0 offset 0x10A The USB type endpoint 0 8 bit register USBTYPE0 must be written with the operating speed of the targeted...

Page 1108: ...d by the limit set in this register the endpoint is halted Note A value of 0 or 1 disables the NAK timeout function Mode s Host USBNAKLMT is shown in Figure 17 40 and described in Table 17 41 Figure 1...

Page 1109: ...1 Indicates that a STALL handshake has been received When this bit is set any DMA request that is in progress is stopped the FIFO is completely flushed and the TXRDY bit is cleared 4 SETUP Setup Pack...

Page 1110: ...d 6 CLRDT Clear Data Toggle 0 No effect 1 Writing a 1 to this bit clears the DT bit in the USBTXCSRH n register 5 STALLED Endpoint Stalled Software must clear this bit 0 A STALL handshake has not been...

Page 1111: ...has been transmitted The EPn bit in the USBTXIS register is also set at this point TXRDY is also automatically cleared prior to loading a second packet into a double buffered FIFO 0 No transmit packet...

Page 1112: ...and receive transactions 0 Enables the endpoint direction as RX 1 Enables the endpoint direction as TX 4 DMAEN DMA Request Enable Note Three TX and three RX endpoints can be connected to the DMA modul...

Page 1113: ...it FIFO If a packet of less than the maximum packet size is loaded then the TXRDY bit must be set manually 6 Reserved Reserved Should always have a value of 0 5 MODE Mode Note This bit only has an eff...

Page 1114: ...O size if double buffering is required Note USBRXMAXP n must be set to an even number of bytes for proper interrupt generation in DMA Basic Mode For the specific offset for each register see Table 17...

Page 1115: ...cleared when the RXRDY bit is set 0 No request 1 Requests an IN transaction 4 FLUSH Flush FIFO If the FIFO is double buffered FLUSH may have to be set twice to completely clear the FIFO Note This bit...

Page 1116: ...Device Mode Field Descriptions Bit Field Value Description 7 CLRDT Clear Data Toggle 0 No effect 1 Writing a 1 to this bit clears the DT bit in the USBRXCSRH n register 6 STALLED Endpoint Stalled Sof...

Page 1117: ...bit is clear or if packets of less than the maximum packet size are unloaded then software must clear this bit manually when the packet has been unloaded from the receive FIFO 0 No data packet has bee...

Page 1118: ...ly cleared when a short packet is received 0 No effect 1 Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared 5 DMAEN DMA Request Enable Note Three TX and three RX endpoints ca...

Page 1119: ...6 Reserved Reserved 5 DMAEN DMA Request Enable Note Three TX and three RX endpoints can be connected to the DMA module If this bit is set for a particular endpoint the DMAARX DMABRX or DMACRX field in...

Page 1120: ...ster see Table 17 3 Mode s Host Device The USBRXCOUNT n registers are shown in Figure 17 50 and described in Table 17 51 Figure 17 50 USB Maximum Receive Data Endpoint n Registers USBRXCOUNT n 15 13 1...

Page 1121: ...Host Transmit Configure Type Endpoint n Register USBTXTYPE n Field Descriptions Bit Field Value Description 7 6 SPEED Operating Speed This bit field specifies the operating speed of the target Device...

Page 1122: ...he NAK Limit is 2 m 1 frames A value of 0 or 1 disables the NAK timeout function For the specific offset for each register see Table 17 3 Mode s Host The USBTXINTERVAL n registers are shown in Figure...

Page 1123: ...ost Configure Receive Type Endpoint n Register USBRXTYPE n Field Descriptions Bit Field Value Description 7 6 SPEED Operating Speed This bit field specifies the operating speed of the target Device 0h...

Page 1124: ...he NAK Limit is 2 m 1 frames A value of 0 or 1 disables the NAK timeout function For the specific offset for each register see Table 17 3 Mode s Host The USBRXINTERVAL n registers are shown in Figure...

Page 1125: ...Table 17 3 Mode s Host The USBRQPKTCOUNT n registers are shown in Figure 17 55 and described in Table 17 58 Figure 17 55 USB Request Packet Count in Block Transfer Endpoint n Registers USBRQPKTCOUNT n...

Page 1126: ...BRXDPKTBUFDIS 15 4 3 2 1 0 Reserved EP3 EP2 EP1 Rsvd R 0 R W 1 R W 1 R W 1 R 0 LEGEND R W Read Write R Read only n value after reset Table 17 59 USB Receive Double Packet Buffer Disable Register USBRX...

Page 1127: ...SBTXDPKTBUFDIS 15 4 3 2 1 0 Reserved EP3 EP2 EP1 Rsvd R 0 R W 1 R W 1 R W 1 R 0 LEGEND R W Read Write R Read only n value after reset Table 17 60 USB Transmit Double Packet Buffer Disable Register USB...

Page 1128: ...EPENDE bits 1h Tristate USB0EPEN is undriven tristate 2h Low USB0EPEN is driven Low 3h High USB0EPEN is driven High 7 Reserved 0 Reserved 6 PFLTAEN Power Fault Action Enable This bit specifies whethe...

Page 1129: ...the power supply 0 Not Driven The USB0EPEN signal is high impedance 1 Driven The USB0EPEN signal is driven to the logical value specified by the value of the EPEN field 1 0 EPEN External Power Supply...

Page 1130: ...1 1 0 Reserved PF R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 17 62 USB External Power Control Raw Interrupt Status Register USBEPCRIS Field Descriptions Bit Field Value Descri...

Page 1131: ...PF R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 17 63 USB External Power Control Interrupt Mask Register USBEPCIM Field Descriptions Bit Field Value Description 31 1 Reserved 0...

Page 1132: ...ter reset Table 17 64 USB External Power Control Interrupt Status and Clear Register USBEPCISC Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved Reset is 0x0000 000 0 PF USB Powe...

Page 1133: ...tus Register USBDRRIS 31 1 0 Reserved RESUME R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 17 65 USB Device RESUME Raw Interrupt Status Register USBDRRIS Field Descriptions Bit F...

Page 1134: ...R W Read Write R Read only n value after reset Table 17 66 USB Device RESUME Raw Interrupt Status Register USBDRRIS Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved Reset is 0x...

Page 1135: ...alue after reset Table 17 67 USB Device RESUME Interrupt Status and Clear Register USBDRISC Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved Reset is 0x0000 000 0 RESUME RESUME...

Page 1136: ...urpose Control and Status Register USBGPCS 31 2 1 0 Reserved DEVMODOTG DEVMOD R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 68 USB General Purpose Control and Status R...

Page 1137: ...mapping of the third USB endpoint on DMA channel 5 primary assignment 0h Reserved 1h Endpoint 1 TX 2h Endpoint 2 TX 3h Endpoint 3 TX 19 16 DMACRX DMA C RX Select specifies the RX and TX mapping of the...

Page 1138: ...ved 1h Endpoint 1 TX 2h Endpoint 2 TX 3h Endpoint 3 TX 3 0 DMAARX DMA A RX Select specifies the RX mapping of the first USB endpoint on DMA channel 0 primary assignment 0h Reserved 1h Endpoint 1 RX 2h...

Page 1139: ...d Section 4 4 3 404 Chapter 5 High Resolution Capture HRCAP 405 Added Section 5 1 1 406 Chapter 6 Enhanced Capture eCAP 429 Chapter 7 Enhanced Quadrature Encoder Pulse eQEP 461 Changed Table 7 2 469 C...

Page 1140: ...erial Port McBSP 877 Chapter 16 Controller Area Network CAN 999 Changed last paragraph in Section 16 6 2 1010 Chapter 17 Universal Serial Bus USB Controller 1055 Revision History www ti com 1140 TMS32...

Page 1141: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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