12.5.2.4 SPI Baud Rate Register (SPIBRR) (Offset = 4h) [reset = 0h]
SPIBRR contains the bits used for baud-rate selection.
Figure 12-16. SPI Baud Rate Register (SPIBRR)
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
SPI_BIT_RATE
R-0h
R/W-0h
Table 12-12. SPI Baud Rate Register (SPIBRR) Field Descriptions
Bit
Field
Type
Reset
Description
15-7
RESERVED
R
0h
Reserved
6-0
SPI_BIT_RATE
R/W
0h
SPI Baud Rate Control
These bits determine the bit transfer rate if the SPI is the network
SPI BIT RATE 0 master. There are 125 data-transfer rates (each
a function of the CPU clock, LSPCLK) that can be selected. One
data bit is shifted per SPICLK cycle. (SPICLK is the baud rate clock
output on the SPICLK pin.)
If the SPI is a network slave, the module receives a clock on the
SPICLK pin from the network master. Therefore, these bits have no
effect on the SPICLK signal. The frequency of the input clock from
the master should not exceed the slave SPI's LSPCLK signal divided
by 4.
In master mode, the SPI clock is generated by the SPI and is output
on the SPICLK pin. The SPI baud rates are determined by the
following formula:
For SPIBRR = 3 to 127: SPI Baud Rate = LSPCLK / ( 1)
For SPIBRR = 0, 1, or 2: SPI Baud Rate = LSPCLK / 4
Reset type: SYSRSn
3h (R/W) = SPI Baud Rate = LSPCLK/4
4h (R/W) = SPI Baud Rate = LSPCLK/5
7Eh (R/W) = SPI Baud Rate = LSPCLK/127
7Fh (R/W) = SPI Baud Rate = LSPCLK/128
Serial Peripheral Interface (SPI)
788
TMS320x2806x Microcontrollers
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
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