MRCNDD {CNDF}
(continued)
Return Conditional Delayed
Referring to the following code fragment and the pipeline diagrams in
, the instructions before and after MRCNDD have the following properties:
;
;
<Instruction 1> ; I1 Last instruction that can affect flags for
; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
<Instruction 10> ; I10
....
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD NEQ ; Return to <Instruction 8> if not equal to zero
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
<Destination 12> ; d12
....
....
MSTOP
....
•
d4
– d4 is the last instruction that can effect the CNDF flags for the MRCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to return or not when MRCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for d4.
•
d5, d6 and d7
– The three instructions proceeding MRCNDD can change MSTF flags but will have
no effect on whether the MRCNDD instruction makes the return or not. This is
because the flag modification will occur after the D2 phase of the MRCNDD
instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD or MRCNDD.
•
d8, d9 and d10
– The three instructions following MRCNDD are always executed irrespective of
whether the return is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD or MRCNDD.
Control Law Accelerator (CLA)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
689
Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
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