When in Host mode, IN transactions are controlled by an endpoint’s receive interface. All IN transactions use the
receive endpoint registers and all OUT endpoints use the transmit endpoint registers for a given endpoint. As in
device mode, the FIFOs for endpoints should take into account the maximum packet size for an endpoint.
• Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size
if double buffering is used (described further in the following section).
• Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet
size if double buffering is used.
• It is also possible to specify a separate control endpoint to communicate with a device. However, in most
cases the USB controller should use the dedicated control endpoint to communicate with a device’s endpoint
0.
17.2.2.1 Endpoint Registers
The endpoint registers are used to control the USB endpoint interfaces which communicate with device(s) that
are connected. The endpoints consist of a dedicated control IN endpoint and a dedicated control OUT endpoint.
The remaining available endpoints are configurable, with one-half of them being OUT endpoints, and one-half of
them being IN endpoints. See
for the number of available endpoints on this device.
The dedicated control interface can only be used for control transactions to endpoint 0 of devices. These
control transactions are used during enumeration or other control functions that communicate using endpoint 0
of devices. This control endpoint shares the first 64 bytes of the USB controller’s FIFO RAM for IN and OUT
transactions. The remaining IN and OUT interfaces can be configured to communicate with control, bulk, or
interrupt endpoints.
These USB interfaces can be used to simultaneously schedule as many as three independent OUT and three
independent IN transactions to any endpoints on any device. The IN and OUT controls are paired together in
the same set of registers for the respective endpoints. However, they can be configured to communicate with
different types of endpoints and different endpoints on devices. For example, the first pair of endpoint controls
can be split so that the OUT portion is communicating with a device’s bulk OUT endpoint 1, while the IN portion
is communicating with a device’s interrupt IN endpoint 2.
Before accessing any device, whether for point-to-point communications or for communications via a hub,
the relevant USB Receive Functional Address Endpoint n (USBRXFUNCADDRn) or USB Transmit Functional
Address Endpoint n (USBTXFUNCADDRn) registers must be set for each receive or transmit endpoint to record
the address of the device being accessed.
The USB controller also supports connections to devices through a USB hub by providing a register that
specifies the hub address and port of each USB transfer. The FIFO address and size are customizable and
can be specified for each USB IN and OUT transfer. Customization includes allowing one FIFO per transaction,
sharing a FIFO across transactions, and allowing for double-buffered FIFOs.
17.2.2.2 IN Transactions as a Host
IN transactions are handled in a similar manner to the way in which OUT transactions are handled when the
USB controller is in device mode except that the transaction first must be initiated by setting the REQPKT bit
in the USBCSRL0 register, indicating to the transaction scheduler that there is an active transaction on this
endpoint. The transaction scheduler then sends an IN token to the target device. When the packet is received
and placed in the receive FIFO, the RXRDY bit in the USBCSRL0 register is set, and the appropriate receive
endpoint interrupt is signaled to indicate that a packet can now be unloaded from the FIFO.
When the packet has been unloaded, RXRDY must be cleared. The AUTOCL bit in the USBRXCSRHn register
can be used to have RXRDY automatically cleared when a maximum-sized packet has been unloaded from the
FIFO. The AUTORQ bit in USBRXCSRHn causes the REQPKT bit to be automatically set when the RXRDY
bit is cleared. When the RXRDY bit is cleared, the controller sends an acknowledge to the device. When there
is a known number of packets to be transferred, the USB Request Packet Count in Block Transfer Endpoint
n (USBRQPKTCOUNTn) register associated with the endpoint should be configured to the number of packets
to be transferred. The USB controller decrements the value in the USBRQPKTCOUNTn register following each
request. When the USBRQPKTCOUNTn value decrements to 0, the AUTORQ bit is cleared to prevent any
further transactions being attempted. For cases where the size of the transfer is unknown, USBRQPKTCOUNTn
Universal Serial Bus (USB) Controller
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
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Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
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