(CLKRM = 0 and MCLKR is an input pin), the external rising-edge triggered input clock on MCLKR is inverted
to a falling-edge triggered clock before being sent to the receiver. If CLKRP = 1 and internal clocking is selected
(CLKRM = 1), the internal falling-edge triggered clock is inverted to a rising-edge triggered clock before being
sent out on the MCLKR pin.
CLKRP = CLKXP in a system where the same clock (internal or external) is used to clock the receiver and
transmitter. The receiver uses the opposite edge as the transmitter to ensure valid setup and hold of data around
this edge.
shows how data clocked by an external serial device using a rising edge can be sampled
by the McBSP receiver on the falling edge of the same clock.
B6
B7
DR
CLKR
Data hold
Á
Á
Á
Á
Data setup
Internal
Figure 15-50. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a
Falling Edge
15.7.19 Set the SRG Clock Divide-Down Value
Table 15-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value
Register
Bit
Name
Function
Type
Reset Value
SRGR1
7-0
CLKGDV
Sample rate generator clock divide-down value
R/W
0000 0001
The input clock of the sample rate generator is divided by (CLKGDV
+ 1) to generate the required sample rate generator clock frequency.
The default value of CLKGDV is 1 (divide input clock by 2).
15.7.19.1 Sample Rate Generator Clock Divider
The first divider stage generates the serial data bit clock from the input clock. This divider stage utilizes a
counter, preloaded by CLKGDV, that contains the divide ratio value.
The output of the first divider stage is the data bit clock, which is output as CLKG and which serves as the input
for the second and third stages of the divider.
CLKG has a frequency equal to 1/( 1) of sample rate generator input clock. Thus, the sample
generator input clock frequency is divided by a value between 1 and 256. When CLKGDV is odd or equal to
0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide-down, the
high-state duration is p + 1 cycles and the low-state duration is p cycles.
Multichannel Buffered Serial Port (McBSP)
936
TMS320x2806x Microcontrollers
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
Page 2: ......
