1.3.2.4.1.3 PLL Lock Period (PLLLOCKPRD) Register
Figure 1-27. PLL Lock Period (PLLLOCKPRD) Register
15
0
PLLLOCKPRD
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-26. PLL Lock Period (PLLLOCKPRD) Register Field Descriptions
Bit
Field
Value
15-0
PLLLOCKPRD
PLL Lock Period Counter Value
These 16 bits configure the PLL lock period. This value is programmable, so shorter PLL lock-time
can be programmed by user. The user needs to compute the number of OSCCLK cycles (based on
the OSCCLK value used in the design) and update this register.
PLL Lock Period
FFFFh 65535 OSCLK Cycles (default on reset)
FFFEh 65534 OSCLK Cycles
...
...
0001h 1 OSCCLK Cycle
0000h 0 OSCCLK Cycles (no PLL lock period)
(1)
PLLLOCKPRD is affected by the XRSn signal only.
(2)
This register is EALLOW protected. See
for more information.
System Control and Interrupts
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
81
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Summary of Contents for TMS320 2806 Series
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