Texas Instruments TMS320 2806 Series, Technical Reference Manual

Page: 747 / 1141

Table 11-8. Mode Register (MODE) Field Descriptions (continued)
Bit Field Value Description
7 OVRINTE
(1)
Overflow Interrupt Enable: This bit when set to 1 enables the DMA to generate an interrupt
when an overflow event is detected.
0 Overflow interrupt disabled
1 Overflow interrupt enabled
An overflow interrupt is generated when the PERINTFLG is set and another interrupt event
occurs. The PERINTFLG being set indicates a previous peripheral event is latched and has
not been serviced by the DMA.
6-5 Reserved Reserved
4-0 PERINTSEL Peripheral Interrupt Source Select Bits: These bits select which interrupt triggers a DMA burst
for the given channel. Only one interrupt source can be selected. A DMA burst can also be
forced via the PERINTFRC bit.
Value Interrupt Sync Peripheral
0 None None No peripheral connection
1 ADCINT1 None ADC
(2)
2 ADCINT2 None
3 XINT1 None External Interrupts
4 XINT2 None
5 XINT3 None
6 Reserved None No peripheral connection
7 USB0EP1RX None USB-0
8 USB0EP1TX None
9 USB0EP2RX None
10 USB0EP2TX None
11 TINT0 None CPU Timers
12 TINT1 None
13 TINT2 None
14 MXEVTA None McBSP-A
15 MREVTA None
16 Reserved None No peripheral connection
17 Reserved None
18 ePWM2SOCA None ePWM2
19 ePWM2SOCB None
20 ePWM3SOCA None ePWM3
21 ePWM3SOCB None
22 ePWM4SOCA None ePWM4
23 ePWM4SOCB None
24 ePWM5SOCA None ePWM5
25 ePWM5SOCB None
26 ePWM6SOCA None ePWM6
27 ePWM6SOCB None
28 ePWM7SOCA None ePWM7
29 ePWM7 SOCB None
30 USB0EP3RX None USB-0
31 USB0EP3TX None
(1) The overflow interrupt is ORed together with the DMACH interrupt as shown in Figure 11-6 .
(2) The ADCSYNC only works when the sequencer override bit is set in the ADC sequencer control registers.
www.ti.com Direct Memory Access (DMA) Module
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
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