the CLKSM bit of SRGR2. If a pin is used, the polarity of the incoming signal can be inverted with the appropriate
polarity bit (CLKXP of PCR or CLKRP of PCR).
The sample rate generator has a three-stage clock divider that gives CLKG and FSG programmability. The three
stages provide:
• Clock divide-down. The source clock is divided according to the CLKGDV bits of SRGR1 to produce CLKG.
• Frame period divide-down. CLKG is divided according to the FPER bits of SRGR2 to control the period from
the start of a frame-pulse to the start of the next pulse.
• Frame-synchronization pulse-width countdown. CLKG cycles are counted according to the FWID bits of
SRGR1 to control the width of each frame-synchronization pulse.
Note
The McBSP cannot operate at a frequency faster than ½ the source clock frequency. Choose an input
clock frequency and a CLKGDV value such that CLKG is less than or equal to ½ the source clock
frequency.
In addition to the three-stage clock divider, the sample rate generator has a frame-synchronization pulse
detection and clock synchronization module that allows synchronization of the clock divide down with an
incoming frame-synchronization pulse on the FSR pin. This feature is enabled or disabled with the GSYNC
bit of SRGR2.
For details on getting the sample rate generator ready for operation, see
Reset and Initialization
Procedure
.
15.3.1.1 Clock Generation in the Sample Rate Generator
The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter, or both.
Use of the sample rate generator to drive clocking is controlled by the clock mode bits (CLKRM and CLKXM)
in the pin control register (PCR). When a clock mode bit is set to 1 (CLKRM = 1 for reception, CLKXM = 1 for
transmission), the corresponding data clock (CLKR for reception, CLKX for transmission) is driven by the internal
sample rate generator output clock (CLKG).
The effects of CLKRM = 1 and CLKXM = 1 on the McBSP are partially affected by the use of the digital loopback
mode and the clock stop (SPI) mode, respectively, as described in
) is selected with the DLB bit of SPCR1. The clock stop mode (described in
) is selected with the CLKSTP bits of SPCR1.
When using the sample rate generator as a clock source, make sure the sample rate generator is enabled
(GRST = 1).
Table 15-4. Effects of DLB and CLKSTP on Clock Modes
Mode Bit Settings
Effect
CLKRM = 1
DLB = 0
(Digital loopback mode disabled)
CLKR is an output pin driven by the sample rate generator output clock (CLKG).
DLB = 1
(Digital loopback mode enabled)
CLKR is an output pin driven by internal CLKX. The source for CLKX depends
on the CLKXM bit.
CLKXM = 1
CLKSTP = 00b or 01b
(Clock stop (SPI) mode disabled)
CLKX is an output pin driven by the sample rate generator output clock (CLKG).
CLKSTP = 10b or 11b
(Clock stop (SPI) mode enabled)
The McBSP is a master in an SPI system. Internal CLKX drives internal CLKR
and the shift clocks of any SPI-compliant slave devices in the system. CLKX is
driven by the internal sample rate generator.
15.3.1.2 Choosing an Input Clock
The sample rate generator must be driven by an input clock signal from one of the three sources selectable with
the SCLKME bit of PCR and the CLKSM bit of SRGR2 (see
). When CLKSM = 1, the minimum divide
down value in CLKGDV bits is 1. CLKGDV is described in
.
Multichannel Buffered Serial Port (McBSP)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
891
Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
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