EMIF
7.3.3.11 Power Management
This section defines the power management capabilities and requirements.
7.3.3.11.1 Clock Stop Mode
The memory controller supports Clock Stop mode for LPDDR1/mDDR. The memory controller
automatically stops the clocks to the memory, after the memory controller is idle for REG_CS_TIM number
of DDR clock cycles and the REG_LP_MODE field is set to 1. The REG_LP_MODE and REG_CS_TIM
fields can be programmed in the power management control register (PMCR).
When the clock to the memory is stopped, the memory controller services register accesses as normal. If
an SDRAM access is requested, or the Refresh Must level is reached while in the Clock Stop mode, the
memory controller will start the clocks. The memory controller now can issue any commands. If the power
saving mode is changed by changing REG_LP_MODE from 1 to some other value, the memory controller
will exit Clock Stop mode and enter the new power saving mode.
7.3.3.11.2 Self-Refresh Mode
The DDR2/3/mDDR memory controller supports self-refresh mode for low power. The memory controller
automatically puts the SDRAM into self-refresh after the memory controller is idle for REG_SR_TIM
number of DDR clock cycles and the REG_LP_MODE field is set to 2. The REG_LP_MODE and
REG_SR_TIM fields can be programmed in the Power Management Control register(PMCR). The memory
controller will complete all pending refreshes before it puts the SDRAM into self-refresh. Therefore, after
the expiration of REG_SR_TIM, the memory controller will start issuing refreshes to complete the refresh
backlog, and then issue a SELF-REFRESH command to the SDRAM.
In self-refresh mode, the memory controller automatically stops the clocks DDR_CLK to the SDRAM. The
memory controller maintains DDR_CKE low to maintain the self-refresh state. When the SDRAM is in self-
refresh, the memory controller services register accesses as normal. If the REG_LP_MODE field is set not
equal to 2, or an SDRAM access is requested while it is in self-refresh, and T_CKE + 1 cycles have
elapsed since the SELF-REFRESH command was issued, the memory controller will bring the SDRAM
out of self-refresh. The value of T_CKE is taken from SDRAM Timing 2 register. For DDR3, memory
controller will also exit self-refresh to perform incremental leveling.
Exit sequence of self-refresh mode for LPDDR1 device: The memory controller:
•
Enables clocks.
•
Drives DDR_CKE high.
•
Waits for 1 cycles. The value of T_XSNR is taken from SDRAM Timing 2 register.
•
Starts an auto-refresh cycle in the next cycle.
•
Enters its idle state and can issue any commands.
Exit sequence of self-refresh mode for DDR2 device: The memory controller:
•
Enables clocks.
•
Drives DDR_CKE high.
•
Waits for 1 cycles. The value of T_XSNR is taken from SDRAM Timing 2 register.
•
If the REG_DDR_DISABLE_DLL bit in the SDRAM Config register is 1, issues a LOAD MODE
REGISTER command to the extended mode register 1 with the pad_a_o bits set as follows:
Bits
Value
Description
DDR_A[15:13]
0x0
!reg_ddr2_ddqs
DDR_A[12]
0x0
Output buffer enabled
DDR_A[11]
0x0
RDQS disable
DDR_A[10]
!reg_ddr2_ddqs
Differential DQS enable value from SDRAM Config register
DDR_A[9:7]
0x0
Exit OCD calibration mode
DDR_A[6]
reg_ddr_term[1]
DDR2 termination resistor value from SDRAM Config register
DDR_A[5:3]
0x0
Additive latency = 0
DDR_A[2]
reg_ddr_term[0]
DDR2 termination resistor value from SDRAM Config register
419
SPRUH73H – October 2011 – Revised April 2013
Memory Subsystem
Copyright © 2011–2013, Texas Instruments Incorporated
