Functional Description
For the CPDMA, the reset state is entered at packet boundaries, at which time the CPDMA reset occurs.
The CPGMAC_SL soft reset is immediate. Submodule reset status is determined by reading or polling the
submodule reset bit. If the submodule reset bit is read as a one, then the reset process has not yet
completed. The submodule soft reset process could take up to 2ms each. The reset has completed if the
submodule reset bit is read as a zero.
After all three submodules (in any order) have been reset and a read of each submodule reset bit
indicates that the reset process is complete, the CPSW_3G software reset register bit may be written to
complete the CPSW_3G module software reset operation. The CPSW_3G software reset bit controls the
reset of the FIFO’s, the statistics submodule, and the address lookup engine (ALE). The CPSW_3G
software reset is immediate and will be indicated by reading a zero from the soft reset bit.
The CPSW_3GSS software reset bit controls the reset of the INT, REGS and CPPI. The CPSW_3GSS
software reset is immediate and will be indicated by reading a zero from the soft reset bit.
14.3.2.19 FIFO Loopback
FIFO loopback mode is entered when the fifo_loopback bit in the CPSW_Control register is set. FIFO
loopback mode causes packets received on a port to be turned around and transmitted back on the same
port. Port 0 receive is fixed on channel zero in FIFO loopback mode. The RXSOFOVERRUN statistic is
incremented for each packet sent in FIFO loopback mode. Packets sent in with errors are returned with
errors (they are not dropped). FIFO loopback is intended as a simple mechanism for test purposes. FIFO
loopback should be performed in fullduplex mode only.
14.3.2.20 CPSW_3G Network Statistics
The CPSW_3G has a set of statistics that record events associated with frame traffic on selected switch
ports. The statistics values are cleared to zero 38 clocks after the rising edge of VBUSP_RST_N. When
one or more port enable bits (stat_port_en[2:0]) are set, all statistics registers are write to decrement. The
value written will be subtracted from the register value with the result being stored in the register. If a
value greater than the statistics value is written, then zero will be written to the register (writing 0xffffffff will
clear a statistics location).
When all port enable bits are cleared to zero, all statistics registers are read/write (normal write direct, so
writing 0x00000000 will clear a statistics location). All write accesses must be 32-bit accesses. In the
below statistics descriptions, “the port” refers to any enabled port (with a corresponding set
stat_port_en[2:0] bit).
The statistics interrupt (STAT_PEND) will be issued if enabled when any statistics value is greater than or
equal to 0x80000000. The statistics interrupt is removed by writing to decrement any statistics value
greater than 0x80000000. The statistics are mapped into internal memory space and are 32-bits wide. All
statistics rollover from 0xFFFFFFFF to 0x00000000.
14.3.2.20.1 Rx-only Statistics Descriptions
14.3.2.20.1.1 Good Rx Frames (Offset = 0h)
The total number of good frames received on the port. A good frame is defined to be:
•
Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched
due to promiscuous mode
•
Had a length of 64 to rx_maxlen bytes inclusive
•
Had no CRC error, alignment error or code error.
See the Rx Align/Code Errors and Rx CRC errors statistic descriptions for definitions of alignment, code
and CRC errors. Overruns have no effect upon this statistic.
14.3.2.20.1.2 Broadcast Rx Frames (Offset = 4h)
The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:
•
Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF
1211
SPRUH73H – October 2011 – Revised April 2013
Ethernet Subsystem
Copyright © 2011–2013, Texas Instruments Incorporated
