Functional Description
22.3.12.3 Separate Transmit and Receive Initialization
In many cases, it is desirable to separately initialize the McASP transmitter and receiver. For example, you
may delay the initialization of the transmitter until the type of data coming in on the receiver is recognized.
Or a change in the incoming data stream on the receiver may necessitate a reinitialization of the
transmitter.
In this case, you may still follow the sequence outlined in
, but use it for each section
(transmit, receive) individually. The GBLCTL register is aliased to RGBLCTL and XGBLCTL to facilitate
separate initialization of transmit and receive sections.
22.3.12.4 Importance of Reading Back GBLCTL
In
, steps 3b, 4b, 6c, 8b, and 9b state that GBLCTL should be read back until the bits
that were written are successfully latched. This is important, because the transmitter and receiver state
machines run off of the respective bit clocks, which are typically about tens to hundreds of times slower
than the processor's internal bus clock. Therefore, it takes many cycles between when the processor
writes to GBLCTL (or RGBLCTL and XGBLCTL), and when the McASP actually recognizes the write
operation. If you skip this step, then the McASP may never see the reset bits in the global control registers
get asserted and de-asserted; resulting in an uninitialized McASP.
Therefore, the logic in McASP has been implemented such that once the processor writes GBLCTL,
RGBLCTL, or XGBLCTL, the resulting write is not visible by reading back GBLCTL until the McASP has
recognized the change. This typically requires two bit clocks plus two processor bus clocks to occur.
Also, if the bit clocks can be completely stopped, any software that polls GBLCTL should be implemented
with a time-out. If GBLCTL does not have a time-out, and the bit clock stops, the changes written to
GBLCTL will not be reflected until the bit clock restarts.
Finally, please note that while RGBLCTL and XGBLCTL allow separate changing of the receive and
transmit halves of GBLCTL, they also immediately reflect the updated value (useful for debug purposes).
Only GBLCTL can be used for the read back step.
22.3.12.5 Synchronous Transmit and Receive Operation (ASYNC = 0)
When ASYNC = 0 in ACLKXCTL, the transmit and receive sections operate synchronously from the
transmit section clock and transmit frame sync signals (
). The receive section may have a
different (but compatible in terms of slot size) data format.
When ASYNC = 0, the receive frame sync generator is internally disabled. If the AFSX pin is configured
as an output, it serves as the frame sync signal for both transmit and receive. The AFSR pin should not be
used because the transmit frame sync generator output, which is used by both the transmitter and the
receiver when ASYNC = 0, is not propagated to the AFSR pin (
).
When ASYNC = 0, the transmit and receive sections must share some common settings, since they both
use the same clock and frame sync signals:
•
DITEN = 0 in DITCTL (TDM mode is enabled).
•
The total number of bits per frame must be the same (that is, RSSZ × RMOD must equal
XSSZ × XMOD).
•
Both transmit and receive should either be specified as burst or TDM mode, but not mixed.
•
The settings in ACLKRCTL are irrelevant.
•
FSXM must match FSRM.
•
FXWID must match FRWID.
For all other settings, the transmit and receive sections may be programmed independently.
22.3.12.6 Asynchronous Transmit and Receive Operation (ASYNC = 1)
When ASYNC = 1 in ACLKXCTL, the transmit and receive sections operate completely independently and
have separate clock and frame sync signals (
, and
). The events
generated by each section come asynchronously.
3820
Multichannel Audio Serial Port (McASP)
SPRUH73H – October 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
