Renesas SH7709S, Hardware Manual

Page: 441 / 807

Rev. 5.00, 09/03, page 397 of 760
12.2.4 Timer Constant Registers (TCOR)
The TMU has three TCOR registers, one for each channel. TCOR specifies the value for setting in
TCNT when a TCNT count-down results in an under flow.
TCOR is a 32-bit readable/writable register. TCOR is initialized to H'FFFFFFFF by a power-on
reset or manual reset, but is not initialized, and retains its contents, in standby mode.
Bit: 31 30 29 28 27 26 25 24
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23 22 21 20 19 18 17 16
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
12.2.5 Timer Counters (TCNT)
The timer counters are 32-bit readable/writable registers. The TMU has three timer counters, one
for each channel.
TCNT counts down upon input of a clock. The clock input is selected using the TPSC2
–
TPSC0
bits in the timer control register (TCR).
When a TCNT count-down results in an underflow (H'00000000
→
H'FFFFFFFF), the underflow
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the count-down continues from that value.