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Rev. 5.00, 09/03, page 527 of 760

Upper 8 bits:

15

14

13

12

11

10

9

8

PER3

PER2

PER1

PER0

FER3

FER2

FER1

FER0

Initial value:

0

0

0

0

0

0

0

0

R/W:

R

R

R

R

R

R

R

R

Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicate the quantity of data
including a parity error in the receive data stored in the receive FIFO data register (SCFRDR).
The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR.

Bits 11 to 8—Number of Framing Errors 3 to 0 (FER3 to FER0): Indicate the quantity of data
including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to
8 represents the number of framing errors in SCFRDR.

16.2.8

Bit Rate Register (SCBRR)

The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.

The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.

Bit:

7

6

5

4

3

2

1

0

Initial value:

1

1

1

1

1

1

1

1

R/W:

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

The SCBRR setting is calculated as follows:

Asynchronous mode:

N =

P

φ

64

×

2

2n – 1

×

B

×

10

6

– 1

B:

Bit rate (bits/s)

N:

SCBRR setting for baud rate generator (0

≤

N

≤

255)

P

φ

: Operating frequency for peripheral modules (MHz)

n:

Baud rate generator clock source (n

=

0, 1, 2, 3) (for the clock sources and values of

n, see table 16.3.)

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Summary of Contents for SH7709S

Page 1: ...crocomputer SuperH RISC engine Family SH7700 Series Rev 5 00 The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of revisions and additions Details should always be checked by referring to the relevant text ...

Page 2: ......

Page 3: ...Renesas 32 Bit RISC Microcomputer SuperH RISC engine Family SH7700 Series SH7709S Group Hardware Manual REJ09B0081 0500O ...

Page 4: ... The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corp by various means including the Renesas Technology Corp Semiconductor home page http www renesas com 4...

Page 5: ...ization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of pro...

Page 6: ...items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage notes are given as required as the final part of each section 7 List of Registers 8 Electrical Characteristics 9 Appendix 10 Main Revisions and Additions...

Page 7: ...ed Purpose This manual provides the information of the hardware functions and electrical characteristics of the SH7709S The SH3 SH 3E SH3 DSP Programming Manual contains detailed information of executable instructions Please read the Programming Manual together with this manual How to Use the Book To understand general functions Read the manual from the beginning The manual explains the CPU system...

Page 8: ...liv User manuals for development tools Name of Document Document No C C Compiler Assembler Optimizing Linkage Editor User s Manual ADE 702 246 Simulator Debugger User s Manual ADE 702 186 Embedded Workshop User s Manual ADE 702 201 ...

Page 9: ...e registers are initialized In the manual reset state the internal states of the CPU and registers of on chip supporting modules other than the bus state controller BSC are initialized Refer to the register configurations in the relevant sections for further details 5 4 Memory Mapped Cache 5 4 1 Address Array 113 Description amended This operation is used to invalidate the address specification fo...

Page 10: ... F000 3FF0 This involves a total of 1 024 writes The above operation should be performed using a non cacheable area 2 Invalidating a Specific Address Newly added 3 Reading Data from a Specific Entry Description amended R0 H F100 004C Data array access Entry H 04 Way 0 Longword address 3 MOV L R0 R1 Longword 3 is read 6 2 6 Interrupt Exception Handling and Priority Table 6 4 Interrupt Exception Han...

Page 11: ... FRQCR should not be changed while a DMAC transfer is in progress Bits IFC2 to IFC0 are changed STC2 to STC0 are not changed The clock ratio of Iφ on chip clock to Bφ bus clock after the change is other than 1 1 9 8 2 Changing the Frequency 218 219 Description added 5 The counter stops at a value of H 00 or H 01 The stop value depends on the clock ratio When the following three conditions are all ...

Page 12: ...n Access Cycles 320 Figure amended T1 CKIO A25 to A0 T2 Twait T1 T2 Twait T1 T2 10 3 10 MCS 0 to MCS 7 Pin Control 323 Description amended This enables 32 64 128 or 256 Mbit memory to be connected to area 0 or area 2 However only CS2 0 0 area 0 should be used for MCSCR0 Table 10 15 shows MCSCR0 MCSCR7 settings and MCS 0 MCS 7 assertion conditions 11 6 Usage Notes 387 Description added 13 DMAC tran...

Page 13: ...n the receive trigger number is read from the receive data register SCFRDR by the DMAC 1 is read from the RDF flag after which 0 is written to it to clear it Description amended 1 SCFTDR Writing and TDFE Flag However if the number of data bytes written to SCFTDR is equal to or less than the transmit trigger number the TDFE flag will be set to 1 again even after having been cleared to 0 TDFE cleari...

Page 14: ...lies a low level is input at the RESETP pin and CKIO has operated for a maximum of 4 clock cycles internal circuits remain unsettled and so pin states are also undefined The system design must ensure that these undefined states do not cause erroneous system operation Note that the RESETP pin cannot receive a low level signal while a low level signal is being input to the CA pin Test conditions for...

Page 15: ...e Row Address CAS Latency 2 690 Tnop cycle deleted from figure A25 to A16 High tAD tAD tAD tCASD2 tCSD3 tRWD tDQMD tBSD tRDH2 tRDS2 tRDH2 tRDS2 tBSD tRASD2 tCASD2 tDQMD tRWD tCSD3 tAD tAD tAD Tc1 Tc2 Tc3 Td1 Tc4 Td2 Td3 Td4 CKIO A12 or A10 A15 to A0 CSn RD WR RAS CAS DQMxx D31 to D0 BS CKE Row address DACKn tDAKD1 tDAKD1 Column address Read command ...

Page 16: ...pply 2 0 1 9 1 8 1 7 V A 2 Pin Specifications Table A 2 Pin Specifications 723 A 3 Treatment of Unused Pins 724 When RTC is not used and When PLL2 is not used amended Before 1 9 1 8V After 2 0 1 9 1 8 1 7V A 4 Pin States in Access to Each Address Space Table A 3 Pin States Ordinary Memory Little Endian Table A 4 Pin States Ordinary Memory Big Endian Table A 5 Pin States Burst ROM Little Endian Tab...

Page 17: ... 25 2 3 Instruction Features 26 2 3 1 Execution Environment 26 2 3 2 Addressing Modes 28 2 3 3 Instruction Formats 32 2 4 Instruction Set 35 2 4 1 Instruction Set Classified by Function 35 2 4 2 Instruction Code Map 50 2 5 Processor States and Processor Modes 53 2 5 1 Processor States 53 2 5 2 Processor Modes 54 Section 3 Memory Management Unit MMU 55 3 1 Overview 55 3 1 1 Features 55 3 1 2 Role o...

Page 18: ...0 3 6 2 Data Array 81 3 6 3 Usage Examples 83 3 7 Usage Note 83 Section 4 Exception Handling 85 4 1 Overview 85 4 1 1 Features 85 4 1 2 Register Configuration 85 4 2 Exception Handling Function 85 4 2 1 Exception Handling Flow 85 4 2 2 Exception Vector Addresses 86 4 2 3 Acceptance of Exceptions 88 4 2 4 Exception Codes 90 4 2 5 Exception Request Masks 91 4 2 6 Returning from Exception Handling 91...

Page 19: ...am 118 6 1 3 Pin Configuration 119 6 1 4 Register Configuration 120 6 2 Interrupt Sources 121 6 2 1 NMI Interrupt 121 6 2 2 IRQ Interrupts 121 6 2 3 IRL Interrupts 122 6 2 4 PINT Interrupts 124 6 2 5 On Chip Peripheral Module Interrupts 124 6 2 6 Interrupt Exception Handling and Priority 125 6 3 INTC Registers 131 6 3 1 Interrupt Priority Registers A to E IPRA IPRE 131 6 3 2 Interrupt Control Regi...

Page 20: ...rce Register BRSR 167 7 2 12 Branch Destination Register BRDR 168 7 2 13 Break ASID Register A BASRA 169 7 2 14 Break ASID Register B BASRB 169 7 3 Operation Description 170 7 3 1 Flow of the User Break Operation 170 7 3 2 Break on Instruction Fetch Cycle 170 7 3 3 Break by Data Access Cycle 171 7 3 4 Sequential Break 172 7 3 5 Value of Saved Program Counter 172 7 3 6 PC Trace 173 7 3 7 Usage Exam...

Page 21: ...203 9 1 Overview 203 9 1 1 Features 203 9 2 Overview of CPG 204 9 2 1 CPG Block Diagram 204 9 2 2 CPG Pin Configuration 206 9 2 3 CPG Register Configuration 206 9 3 Clock Operating Modes 207 9 4 Register Descriptions 211 9 4 1 Frequency Control Register FRQCR 211 9 5 Changing the Frequency 213 9 5 1 Changing the Multiplication Rate 213 9 5 2 Changing the Division Ratio 213 9 6 Overview of WDT 214 ...

Page 22: ...me Constant Register RTCOR 256 10 2 11 Refresh Count Register RFCR 256 10 2 12 Cautions on Accessing Refresh Control Related Registers 257 10 2 13 MCS0 Control Register MCSCR0 258 10 2 14 MCS1 Control Register MCSCR1 259 10 2 15 MCS2 Control Register MCSCR2 259 10 2 16 MCS3 Control Register MCSCR3 259 10 2 17 MCS4 Control Register MCSCR4 259 10 2 18 MCS5 Control Register MCSCR5 259 10 2 19 MCS6 Co...

Page 23: ...n 372 11 3 7 DMA Transfer Ending Conditions 374 11 4 Compare Match Timer CMT 376 11 4 1 Overview 376 11 4 2 Register Descriptions 377 11 4 3 Operation 380 11 4 4 Compare Match 381 11 5 Examples of Use 383 11 5 1 Example of DMA Transfer between On Chip IrDA and External Memory 383 11 5 2 Example of DMA Transfer between A D Converter and External Memory 384 11 5 3 Example of DMA Transfer between Ext...

Page 24: ...MINCNT 412 13 2 4 Hour Counter RHRCNT 412 13 2 5 Day of Week Counter RWKCNT 413 13 2 6 Date Counter RDAYCNT 414 13 2 7 Month Counter RMONCNT 414 13 2 8 Year Counter RYRCNT 415 13 2 9 Second Alarm Register RSECAR 415 13 2 10 Minute Alarm Register RMINAR 416 13 2 11 Hour Alarm Register RHRAR 416 13 2 12 Day of Week Alarm Register RWKAR 417 13 2 13 Date Alarm Register RDAYAR 418 13 2 14 Month Alarm R...

Page 25: ...SC Port Control Register SCPCR SC Port Data Register SCPDR 444 14 2 9 Bit Rate Register SCBRR 446 14 3 Operation 453 14 3 1 Overview 453 14 3 2 Operation in Asynchronous Mode 455 14 3 3 Multiprocessor Communication 465 14 3 4 Synchronous Operation 474 14 4 SCI Interrupts 484 14 5 Usage Notes 485 Section 15 Smart Card Interface 489 15 1 Overview 489 15 1 1 Features 489 15 1 2 Block Diagram 490 15 1...

Page 26: ...ode Register SCSMR 518 16 2 6 Serial Control Register SCSCR 520 16 2 7 Serial Status Register SCSSR 522 16 2 8 Bit Rate Register SCBRR 527 16 2 9 FIFO Control Register SCFCR 534 16 2 10 FIFO Data Count Register SCFDR 536 16 3 Operation 537 16 3 1 Overview 537 16 3 2 Serial Operation 538 16 4 SCIF Interrupts 550 16 5 Usage Notes 551 Section 17 IrDA 555 17 1 Overview 555 17 1 1 Features 555 17 1 2 B...

Page 27: ...A 587 19 2 1 Register Description 587 19 2 2 Port A Data Register PADR 588 19 3 Port B 589 19 3 1 Register Description 589 19 3 2 Port B Data Register PBDR 590 19 4 Port C 591 19 4 1 Register Description 591 19 4 2 Port C Data Register PCDR 592 19 5 Port D 593 19 5 1 Register Description 593 19 5 2 Port D Data Register PDDR 594 19 6 Port E 595 19 6 1 Register Description 595 19 6 2 Port E Data Reg...

Page 28: ... 2 3 A D Control Register ADCR 621 20 3 Bus Master Interface 622 20 4 Operation 623 20 4 1 Single Mode MULTI 0 623 20 4 2 Multi Mode MULTI 1 SCN 0 625 20 4 3 Scan Mode MULTI 1 SCN 1 627 20 4 4 Input Sampling and A D Conversion Time 629 20 4 5 External Trigger Input Timing 630 20 5 Interrupts 631 20 6 Definitions of A D Conversion Accuracy 631 20 7 Usage Notes 632 20 7 1 Setting Analog Input Voltag...

Page 29: ...ctions 654 22 5 2 Points for Attention 655 22 6 Usage Notes 655 22 7 Advanced User Debugger AUD 655 Section 23 Electrical Characteristics 657 23 1 Absolute Maximum Ratings 657 23 2 DC Characteristics 659 23 3 AC Characteristics 663 23 3 1 Clock Timing 664 23 3 2 Control Signal Timing 670 23 3 3 AC Bus Timing 673 23 3 4 Basic Timing 675 23 3 5 Burst ROM Timing 678 23 3 6 Synchronous DRAM Timing 681...

Page 30: ...eatment of Unused Pins 724 A 4 Pin States in Access to Each Address Space 725 Appendix B Memory Mapped Control Registers 739 B 1 Register Address Map 739 B 2 Register Bits 745 Appendix C Product Lineup 757 Appendix D Package Dimensions 758 ...

Page 31: ...3 11 MMU Exception Generation Flowchart 78 Figure 3 12 MMU Exception Signals in Instruction Fetch 79 Figure 3 13 MMU Exception Signals in Data Access 80 Figure 3 14 Specifying Address and Data for Memory Mapped TLB Access 82 Figure 4 1 Vector Table 86 Figure 4 2 Example of Acceptance Order of General Exceptions 89 Figure 4 3 Bit Configurations of EXPEVT INTEVT INTEVT2 and TRA Registers 92 Figure 5...

Page 32: ...ing of Basic Interface 269 Figure 10 7 Example of 32 Bit Data Width Static RAM Connection 270 Figure 10 8 Example of 16 Bit Data Width Static RAM Connection 271 Figure 10 9 Example of 8 Bit Data Width Static RAM Connection 272 Figure 10 10 Basic Interface Wait Timing Software Wait Only 273 Figure 10 11 Basic Interface Wait State Timing Wait State Insertion by WAIT Signal WAITSEL 1 275 Figure 10 12...

Page 33: ...Direct Address Mode in Dual Address Mode 353 Figure 11 6 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode Transfer Source Ordinary Memory Transfer Destination Ordinary Memory 354 Figure 11 7 Indirect Address Operation in Dual Address Mode When External Memory Space has a 16 Bit Width 355 Figure 11 8 Example of Transfer Timing in the Indirect Address Mode in Dual Address Mode ...

Page 34: ...g Periodic Interrupt Function 426 Figure 14 1 Block Diagram of SCI 428 Figure 14 2 SCPT 1 SCK0 Pin 429 Figure 14 3 SCPT 0 TxD0 Pin 430 Figure 14 4 SCPT 0 RxD0 Pin 431 Figure 14 5 Example of Data Format in Asynchronous Communication 8 Bit Data with Parity and Two Stop Bits 455 Figure 14 6 Output Clock and Serial Data Timing Asynchronous Mode 457 Figure 14 7 Sample Flowchart for SCI Initialization 4...

Page 35: ...ssion in SCI Receive Mode 509 Figure 15 10 Retransmission in SCI Transmit Mode 510 Figure 16 1 Block Diagram of SCIF 512 Figure 16 2 SCPT 5 SCK2 Pin 513 Figure 16 3 SCPT 4 TxD2 Pin 514 Figure 16 4 SCPT 4 RxD2 Pin 515 Figure 16 5 Sample Flowchart for SCIF Initialization 540 Figure 16 6 Sample Flowchart for Transmitting Serial Data 542 Figure 16 7 Example of Transmit Operation 8 Bit Data Parity One ...

Page 36: ...re 22 2 TAP Controller State Transitions 651 Figure 22 3 UDI Reset 653 Figure 23 1 EXTAL Clock Input Timing 665 Figure 23 2 CKIO Clock Input Timing 665 Figure 23 3 CKIO Clock Output Timing 665 Figure 23 4 Power on Oscillation Settling Time 666 Figure 23 5 Oscillation Settling Time at Standby Return Return by Reset 666 Figure 23 6 Oscillation Settling Time at Standby Return Return by NMI 667 Figure...

Page 37: ...tency 2 690 Figure 23 32 Synchronous DRAM Burst Read Bus Cycle RAS Down Different Row Address TPC 0 RCD 0 CAS Latency 1 691 Figure 23 33 Synchronous DRAM Burst Read Bus Cycle RAS Down Different Row Address TPC 1 RCD 0 CAS Latency 1 692 Figure 23 34 Synchronous DRAM Burst Write Bus Cycle RAS Down Same Row Address 693 Figure 23 35 Synchronous DRAM Burst Write Bus Cycle RAS Down Different Row Address...

Page 38: ...ode 708 Figure 23 52 I O Port Timing 708 Figure 23 53 DREQ Input Timing 708 Figure 23 54 DRAK Output Timing 709 Figure 23 55 TCK Input Timing 709 Figure 23 56 TRST Input Timing Reset Hold 710 Figure 23 57 UDI Data Transfer Timing 710 Figure 23 58 ASEMD0 Input Timing 710 Figure 23 59 Output Load Circuit 711 Figure 23 60 Load Capacitance vs Delay Time 712 Figure D 1 Package Dimensions FP 208C 758 Fi...

Page 39: ...che Specifications 103 Table 5 2 LRU and Way Replacement When the cache lock function is not used 105 Table 5 3 Register Configuration 105 Table 5 4 Way Replacement when PREF Instruction Ended Up in a Cache Miss 107 Table 5 5 Way Replacement when Instructions Except for PREF Instruction Ended Up in a Cache Miss 108 Table 5 6 LRU and Way Replacement when W2LOCK 1 108 Table 5 7 LRU and Way Replaceme...

Page 40: ...xternal Device Little Endian Access and Data Alignment 264 Table 10 13 Relationship between Bus Width AMX Bits and Address Multiplex Output 279 Table 10 14 Example of Correspondence between SH7709S and Synchronous DRAM Address Pins AMX 3 0 0100 32 Bit Bus Width 281 Table 10 15 MCSCRx Settings and MCS x Assertion Conditions x 0 7 324 Table 11 1 DMAC Pins 330 Table 11 2 DMAC Registers 331 Table 11 3...

Page 41: ...R Status Flags and Transfer of Receive Data 485 Table 15 1 Smart Card Interface Pins 491 Table 15 2 Registers 491 Table 15 3 Register Settings for Smart Card Interface 497 Table 15 4 Relationship of n to CKS1 and CKS0 499 Table 15 5 Examples of Bit Rate B Bits s for SCBRR Settings n 0 499 Table 15 6 Examples of SCBRR Settings for Bit Rate B Bits s n 0 499 Table 15 7 Maximum Bit Rates for Frequenci...

Page 42: ...Operations 604 Table 19 19 Port K Register 605 Table 19 20 Port K Data Register PKDR Read Write Operations 606 Table 19 21 Port L Register 607 Table 19 22 Port L Data Register PLDR Read Write Operation 608 Table 19 23 SC Port Register 609 Table 19 24 Read Write Operation of the SC Port Data Register SCPDR 611 Table 20 1 A D Converter Pins 615 Table 20 2 A D Converter Registers 616 Table 20 3 Analo...

Page 43: ...ations 719 Table A 3 Pin States Ordinary Memory Little Endian 725 Table A 4 Pin States Ordinary Memory Big Endian 727 Table A 5 Pin States Burst ROM Little Endian 729 Table A 6 Pin States Burst ROM Big Endian 731 Table A 7 Pin States Synchronous DRAM Little Endian 733 Table A 8 Pin States Synchronous DRAM Big Endian 734 Table A 9 Pin States PCMCIA Little Endian 735 Table A 10 Pin States PCMCIA Big...

Page 44: ...Rev 5 00 09 03 page xliv of xliv ...

Page 45: ...uperH Series microprocessor SH 1 or SH 2 High speed data transfers can be performed by an on chip direct memory access controller DMAC and an external memory access support function enables direct connection to different types of memory The SH7709S microprocessor also supports an infrared communication function an A D converter and a D A converter A powerful built in power management function keep...

Page 46: ...tions Logical address space 4 Gbytes Space identifier ASID 8 bits 256 logical address space Five stage pipeline Clock pulse generator CPG Clock mode An input clock can be selected from the external input EXTAL or CKIO or crystal oscillator Three types of clocks generated CPU clock 1 24 times the input clock maximum 200 MHz Bus clock 1 4 times the input clock maximum 66 67 MHz Peripheral clock 1 4 ...

Page 47: ...ble for each area Bus size 8 16 or 32 bits Number of wait cycles also supports a hardware wait function Setting the type of space enables direct connection to SRAM Synchronous DRAM and burst ROM Supports PCMCIA interface 2 channels Outputs chip select signal CS0 CS2 CS6 for corresponding area Synchronous DRAM refresh function Programmable refresh interval Support self refresh mode Synchronous DRAM...

Page 48: ...16 byte I O port Twelve 8 bit ports A D converter ADC 10 bits 4 LSB 8 channels Conversion time 16 µs Input range 0 AVcc max 3 6 V D A converter DAC 8 bits 4 LSB 2 channels Conversion time 10 µs Output range 0 AVcc max 3 6 V Product lineup Power Supply Voltage Abbr I O Internal Operating Frequency Model Name Package SH7709S 3 3 0 3 V 2 0 0 15 V 200 MHz HD6417709SHF200B 208 pin plastic HQFP FP 208E ...

Page 49: ... 0 15 V 167 MHz model 1 8 0 25 0 15 V 133 MHz model 1 7 0 25 0 15 V 100 MHz model Operating frequency Internal frequency maximum 200 MHz 200 MHz model 167 MHz 167 MHz model 133 34 MHz 133 MHz model 100 MHz 100 MHz model external frequency maximum 66 67 MHz Process 0 25 µm CMOS 5 layer metal Note 2 0 0 15 0 1 V when an IRL or IRLS interrupt is used ...

Page 50: ... Bus state controller Cache memory Cache memory controller Compare match timer Clock pulse generator watchdog timer Central processing unit D A converter Direct memory access controller User debugging interface INTC IrDA MMU RTC SCI SCIF TLB TMU UBC Interrupt controller Serial communicatiion interface with IrDA Memory management unit Realtime clock Serial communication interface with smart card in...

Page 51: ... PTD 7 DACK0 PTD 5 PTJ 5 PTJ 4 V CC Q CASU PTJ 3 V SS Q CASL PTJ 2 PTJ 1 RAS3L PTJ 0 CKE PTK 5 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 STATUS0 PTJ 6 STATUS1 PTJ 7 TCLK PTH 7 IRQOUT VSSQ CKIO VCCQ TxD0 SCPT 0 SCK0 SCPT 1 TxD1 SCPT 2 ...

Page 52: ...9 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W A B C D E F G H J K L M N P R T U V W Note The pin area enclosed in broken lines is an inner view SH7709S BP 240A Top view Figure 1 3 Pin Assignment BP 240A ...

Page 53: ...rt H 11 F2 IRQ3 IRL3 PTH 3 I External interrupt request input port H 12 F3 IRQ4 PTH 4 I External interrupt request input port H 13 F4 D31 PTB 7 I O Data bus input output port B 14 G1 D30 PTB 6 I O Data bus input output port B 15 G2 D29 PTB 5 I O Data bus input output port B 16 G3 D28 PTB 4 I O Data bus input output port B 17 G4 D27 PTB 3 I O Data bus input output port B 18 H1 D26 PTB 2 I O Data bu...

Page 54: ...sQ Input output power supply 0 V 34 M2 D15 I O Data bus 35 M1 VccQ Input output power supply 3 3 V 36 N4 D14 I O Data bus 37 N3 D13 I O Data bus 38 N2 D12 I O Data bus 39 N1 D11 I O Data bus 40 P4 D10 I O Data bus 41 P3 D9 I O Data bus 42 P2 D8 I O Data bus 43 P1 D7 I O Data bus 44 R4 D6 I O Data bus 45 R3 VssQ Input output power supply 0 V 46 T4 D5 I O Data bus 47 R1 VccQ Input output power suppl...

Page 55: ...68 U7 A13 O Address bus 69 T7 VssQ Input output power supply 0 V 70 W8 A14 O Address bus 71 V8 VccQ Input output power supply 3 3 V 72 U8 A15 O Address bus 73 T8 A16 O Address bus 74 W9 A17 O Address bus 75 V9 A18 O Address bus 76 T9 A19 O Address bus 77 U9 A20 O Address bus 78 V10 A21 O Address bus 79 U10 Vss Power supply 0 V T10 Vss O Power supply 0 V 80 W10 A22 O Address bus 81 U11 Vcc Power su...

Page 56: ... O Read write 94 V14 AUDSYNC PTE 7 O I O AUD synchronous input output port E 95 W14 VssQ Input output power supply 0 V 96 T15 CS0 MCS 0 O Chip select 0 mask ROM chip select 0 97 U15 VccQ Input output power supply 3 3 V 98 T16 CS2 PTK 0 O I O Chip select 2 input output port K 99 W15 CS3 PTK 1 O I O Chip select 3 input output port K 100 U16 CS4 PTK 2 O I O Chip select 4 input output port K 101 W16 C...

Page 57: ...K0 PTD 5 O I O DMA acknowledge 0 input output port D 115 P19 DACK1 PTD 7 O I O DMA acknowledge 1 input output port D 116 P18 PTE 6 I O Input output port E 117 P17 PTE 3 I O Input output port E 118 P16 RAS3U PTE 2 O I O Upper 32 Mbytes address SDRAM RAS input output port E 119 N19 PTE 1 I O Input output port E 120 N18 TDO PTE 0 O I O Test data output input output port E 121 N17 BACK O Bus acknowled...

Page 58: ... port interrupt 139 H18 TCK PTF 4 PNT 12 I Test clock input port F port interrupt 140 H19 IRLS3 PTF 3 PINT 11 I External interrupt request input port F port interrupt 141 G16 IRLS2 PTF 2 PINT 10 I External interrupt request input port F port interrupt 142 G17 IRLS1 PTF 1 PINT 9 I External interrupt request input port F port interrupt 143 G18 IRLS0 PTF 0 PINT 8 I External interrupt request input po...

Page 59: ... 162 A15 CKIO I O System clock input output 163 C17 VccQ Power supply 3 3 V 164 C15 TxD0 SCPT 0 O Transmit data 0 SCI output port 165 D15 SCK0 SCPT 1 I O Serial clock 0 SCI input output port 166 A14 TxD1 SCPT 2 O Transmit data 1 SCI output port 167 B14 SCK1 SCPT 3 I O Serial clock 1 SCI input output port 168 C14 TxD2 SCPT 4 O Transmit data 2 SCI output port 169 D14 SCK2 SCPT 5 I O Serial clock 2 S...

Page 60: ...VccQ Input output power supply 3 3 V 184 C9 RESETOUT PTD 2 O I O Reset output input output port D 185 D9 MCS 3 PTC 3 PINT 3 O I O I Mask ROM chip select input output port C port interrupt 186 B9 MCS 2 PTC 2 PINT 2 O I O I Mask ROM chip select input output port C port interrupt 187 A9 MCS 1 PTC 1 PINT 1 O I O I Mask ROM chip select input output port C port interrupt 188 D8 MCS 0 PTC 0 PINT 0 O I O ...

Page 61: ... connected to the power supply even when the RTC is not used 2 Except in hardware standby mode all of the power supply pins must be connected to the system power supply Supply power constantly In hardware standby mode power must be supplied at least to VCC RTC and VSS RTC If power is not being supplied to any of the power supply pins other than VCC RTC and VSS RTC hold the CA pin low 3 2 0 V for t...

Page 62: ...Rev 5 00 09 03 page 18 of 760 ...

Page 63: ...eral registers R0_BANK0 R7_BANK0 accessed only by the LDC STC instructions When the RB bit is 0 BANK0 general registers R0_BANK0 R7_BANK0 and nonbanked general registers R8 R15 function as the general register set with BANK1 general registers R0_BANK1 R7_BANK1 accessed only by the LDC STC instructions In user mode the 16 registers comprising bank 0 general registers R0_BANK0 R7_BANK0 and non banke...

Page 64: ...2 R6_BANK0 2 R7_BANK0 2 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH MACL PR PC User mode register configuration Notes 1 2 R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing mode Banked register Figure 2 1 User Mode Register Configuration ...

Page 65: ...BR 31 0 b Privileged mode register configuration RB 0 R0_BANK1 1 2 R1_BANK1 2 R2_BANK1 2 R3_BANK1 2 R4_BANK1 2 R5_BANK1 2 R6_BANK1 2 R7_BANK1 2 Notes 1 2 3 R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing mode Banked register When the RB bit of the SR register is 1 the register can be accessed for general use When the RB bit is ...

Page 66: ...0 to R7 are banked registers with a different R0 R7 register bank R0_BANK0 R7_BANK0 or R0_BANK1 R7_BANK1 being accessed according to the processor mode For details see figures 2 1 and 2 2 The general register configuration is shown in figure 2 3 31 0 R0 1 2 General Registers Notes R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing...

Page 67: ... 4 31 0 31 0 31 0 System Registers Multiply and Accumulate High and Low Registers MACH L Store the results of multiply and accumulate operations Procedure Register PR Stores the return address for exiting a subroutine procedure Program Counter PC Indicates the address four addresses two instructions ahead of the currently executing instruction Initialized to H A0000000 by a reset PR PC MACH MACL F...

Page 68: ...and R8 R15 are general registers and R0_BANK0 R7_BANK0 can be accessed by LDC STC instructions RB 0 R0_BANK0 R7_BANK0 and R8 R15 are general registers and R0_BANK1 R7_BANK1 can be accessed by LDC STC instructions RB is set to 1 on generation of an exception or interrupt and is initialized to 1 by a reset Block bit BL 1 Exceptions and interrupts are suppressed See section 4 Exception Handling for d...

Page 69: ...ill result if this rule is not observed A byte operand can be accessed from any address Big endian or little endian byte order can be selected for the data format The endian mode should be set with the MD5 external pin in a power on reset Big endian mode is selected when the MD5 pin is low and little endian when high The endian mode cannot be changed dynamically Bit positions are numbered left to ...

Page 70: ...extended in logical operations TST AND OR and XOR instructions Load Store Architecture The SH7709S features a load store architecture in which basic operations are executed in registers Operations requiring memory access are executed in registers following register loading except for bit manipulation operations such as logical AND functions which are executed directly in memory Delayed Branching U...

Page 71: ... memory rather than inserted directly into the instruction code The memory table is accessed by the MOV instruction using PC relative addressing with displacement as follows MOV W disp PC R0 Absolute Addresses As with word and longword literals absolute addresses must also be stored in a table in main memory The value of the absolute address is transferred to a register and the operand access is s...

Page 72: ...ontents Rn Rn Rn Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand Rn Rn 1 2 4 Rn 1 2 4 Rn After instruction execution Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Register indirect with pre decrement Rn Effective address is register Rn contents de...

Page 73: ...p 1 2 4 Byte Rn disp Word Rn disp 2 Longword Rn disp 4 Indexed register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 GBR indirect with displacement disp 8 GBR Effective address is register GBR contents with 8 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to the operand size GBR 1 2 4 dis...

Page 74: ... longword operand the lower 2 bits of PC are masked PC H FFFFFFFC 2 4 x for longword disp zero extended PC disp 2 or PC H FFFFFFFC disp 4 Word PC disp 2 Longword PC H FFFF FFFC disp 4 PC relative disp 8 Effective address is register PC contents with 8 bit displacement disp added after being sign extended and multiplied by 2 PC 2 disp sign extended PC disp 2 PC disp 2 disp 12 Effective address is r...

Page 75: ... extended imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to the operand size This is done to clarify the operation of the IC Refer to the relevant assembler notation rules for the actual as...

Page 76: ...on Format Source Operand Destination Operand Instruction Example 0 format xxxx xxxx xxxx xxxx 15 0 NOP n format xxxx xxxx xxxx nnnn 15 0 nnnn register direct MOVT Rn Control register or system register nnnn register direct STS MACH Rn Control register or system register nnnn register indirect with pre decrement STC L SR Rn m format xxxx mmmm xxxx xxxx 15 0 mmmm register direct Control register or ...

Page 77: ...er indirect with post increment multiply and accumulate operation MACH MACL MAC W Rm Rn mmmm register indirect with post increment nnnn register direct MOV L Rm Rn mmmm register direct nnnn register indirect with pre decrement MOV L Rm Rn mmmm register direct nnnn indexed register indirect MOV L Rm R0 Rn md format xxxx dddd 15 0 mmmm xxxx mmmmdddd register indirect with displacement R0 register di...

Page 78: ...lacement MOV L R0 disp GBR dddddddd PC relative with displacement R0 register direct MOVA disp PC R0 dddddddd PC relative BF label d12 format dddd xxxx 15 0 dddd dddd dddddddddddd PC relative BRA label label disp PC nd8 format dddd nnnn xxxx 15 0 dddd dddddddd PC relative with displacement nnnn register direct MOV L disp PC Rn i format i i i i xxxx 15 0 xxxx i i i i iiiiiiii immediate Indexed GBR ...

Page 79: ...ransfer SWAP Swap of upper and lower bytes XTRCT Extraction of middle of linked registers Arithmetic 21 ADD Binary addition 33 operations ADDC Binary addition with carry ADDV Binary addition with overflow check CMP cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division DMULS Signed double precision multiplication DMULU Unsigned double precis...

Page 80: ...ion with underflow check 6 AND Logical AND 14 Logic operations NOT Bit inversion OR Logical OR TAS Memory test and bit set TST Logical AND and T bit set XOR Exclusive OR Shift 12 ROTL One bit left rotation 16 ROTR One bit right rotation ROTCL One bit left rotation with T bit ROTCR One bit right rotation with T bit SHAL One bit arithmetic left shift SHAR One bit arithmetic right shift SHLL One bit ...

Page 81: ...utine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure System 15 CLRMAC MAC register clear 75 control CLRT Clear T bit CLRS Clear S bit LDC Load to control register LDS Load to system register LDTLB Load PTE to TLB NOP No operation PREF Prefetch data to cache RTE Return from exception handling SETS Set S bit SETT Set T bit SLEEP Shift to po...

Page 82: ...erand Flag bits in SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n bit shift Privileged mode Indicates whether privileged mode applies Execution cycles Value when no wait states are inserted The execution cycles listed in the table are minimums The actual number of cycles may be increased in cases such as the followsing 1 When contention occurs ...

Page 83: ...W Rm Rn Rm Sign extension Rn 0110nnnnmmmm0001 1 MOV L Rm Rn Rm Rn 0110nnnnmmmm0010 1 MOV B Rm Rn Rn 1 Rn Rm Rn 0010nnnnmmmm0100 1 MOV W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 1 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 1 MOV B Rm Rn Rm Sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 1 MOV W Rm Rn Rm Sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 1 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 1 MOV B R0 disp R...

Page 84: ...00000dddddddd 1 MOV W R0 disp GBR R0 disp 2 GBR 11000001dddddddd 1 MOV L R0 disp GBR R0 disp 4 GBR 11000010dddddddd 1 MOV B disp GBR R0 disp GBR Sign extension R0 11000100dddddddd 1 MOV W disp GBR R0 disp 2 GBR Sign extension R0 11000101dddddddd 1 MOV L disp GBR R0 disp 4 GBR R0 11000110dddddddd 1 MOVA disp PC R0 disp 4 PC R0 11000111dddddddd 1 MOVT Rn T Rn 0000nnnn00101001 1 SWAP B Rm Rn Rm Swap ...

Page 85: ... Rn Rm with unsigned data 1 T 0011nnnnmmmm0010 1 Comparison result CMP GE Rm Rn If Rn Rm with signed data 1 T 0011nnnnmmmm0011 1 Comparison result CMP HI Rm Rn If Rn Rm with unsigned data 1 T 0011nnnnmmmm0110 1 Comparison result CMP GT Rm Rn If Rn Rm with signed data 1 T 0011nnnnmmmm0111 1 Comparison result CMP PZ Rn If Rn 0 1 T 0100nnnn00010001 1 Comparison result CMP PL Rn If Rn 0 1 T 0100nnnn00...

Page 86: ... A word in Rm is sign extended Rn 0110nnnnmmmm1111 1 EXTU B Rm Rn A byte in Rm is zero extended Rn 0110nnnnmmmm1100 1 EXTU W Rm Rn A word in Rm is zero extended Rn 0110nnnnmmmm1101 1 MAC L Rm Rn Signed operation of Rn Rm MAC MAC Rn 4 Rn Rm 4 Rm 32 32 64 64 bits 0000nnnnmmmm1111 2 to 5 MAC W Rm Rn Signed operation of Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 0100nnnnmmmm1111 2 to 5 MUL L Rm Rn...

Page 87: ...110nnnnmmmm1010 1 Borrow SUB Rm Rn Rn Rm Rn 0011nnnnmmmm1000 1 SUBC Rm Rn Rn Rm T Rn Borrow T 0011nnnnmmmm1010 1 Borrow SUBV Rm Rn Rn Rm Rn Underflow T 0011nnnnmmmm1011 1 Underflow Note The normal number of execution cycles is shown The value in parentheses is the number of cycles required in case of contention with the preceding or following instruction ...

Page 88: ...OR Rm Rn Rn Rm Rn 0010nnnnmmmm1011 1 OR imm R0 R0 imm R0 11001011iiiiiiii 1 OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii 3 TAS B Rn If Rn is 0 1 T 1 MSB of Rn 0100nnnn00011011 3 Test result TST Rm Rn Rn Rm if the result is 0 1 T 0010nnnnmmmm1000 1 Test result TST imm R0 R0 imm if the result is 0 1 T 11001000iiiiiiii 1 Test result TST B imm R0 GBR R0 GBR imm if the result is 0 1 T 11001100iii...

Page 89: ...100101 1 LSB SHAD Rm Rn Rn 0 Rn Rm Rn Rn 0 Rn Rm MSB Rn 0100nnnnmmmm1100 1 SHAL Rn T Rn 0 0100nnnn00100000 1 MSB SHAR Rn MSB Rn T 0100nnnn00100001 1 LSB SHLD Rm Rn Rn 0 Rn Rm Rn Rn 0 Rn Rm 0 Rn 0100nnnnmmmm1101 1 SHLL Rn T Rn 0 0100nnnn00000000 1 MSB SHLR Rn 0 Rn T 0100nnnn00000001 1 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 1 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 1 SHLL8 Rn Rn 8 Rn 0100nnnn00011000 1 SHL...

Page 90: ...2 PC PC if T 0 nop 10001001dddddddd 3 1 BT S label Delayed branch If T 1 disp 2 PC PC if T 0 nop 10001101dddddddd 2 1 BRA label Delayed branch disp 2 PC PC 1010dddddddddddd 2 BRAF Rm Delayed branch Rm PC PC 0000mmmm00100011 2 BSR label Delayed branch PC PR disp 2 PC PC 1011dddddddddddd 2 BSRF Rm Delayed branch PC PR Rm PC PC 0000mmmm00000011 2 JMP Rm Delayed branch Rm PC 0100mmmm00101011 2 JSR Rm ...

Page 91: ...10 3 LDC Rm R3_BANK Rm R3_BANK 0100mmmm10111110 3 LDC Rm R4_BANK Rm R4_BANK 0100mmmm11001110 3 LDC Rm R5_BANK Rm R5_BANK 0100mmmm11011110 3 LDC Rm R6_BANK Rm R6_BANK 0100mmmm11101110 3 LDC Rm R7_BANK Rm R7_BANK 0100mmmm11111110 3 LDC L Rm SR Rm SR Rm 4 Rm 0100mmmm00000111 7 LSB LDC L Rm GBR Rm GBR Rm 4 Rm 0100mmmm00010111 5 LDC L Rm VBR Rm VBR Rm 4 Rm 0100mmmm00100111 5 LDC L Rm SSR Rm SSR Rm 4 Rm...

Page 92: ... S 0000000001011000 1 SETT 1 T 0000000000011000 1 1 SLEEP Sleep 0000000000011011 4 STC SR Rn SR Rn 0000nnnn00000010 1 STC GBR Rn GBR Rn 0000nnnn00010010 1 STC VBR Rn VBR Rn 0000nnnn00100010 1 STC SSR Rn SSR Rn 0000nnnn00110010 1 STC SPC Rn SPC Rn 0000nnnn01000010 1 STC R0_BANK Rn R0_BANK Rn 0000nnnn10000010 1 STC R1_BANK Rn R1_BANK Rn 0000nnnn10010010 1 STC R2_BANK Rn R2_BANK Rn 0000nnnn10100010 1...

Page 93: ...MACH Rn 0100nnnn00000010 1 STS L MACL Rn Rn 4 Rn MACL Rn 0100nnnn00010010 1 STS L PR Rn Rn 4 Rn PR Rn 0100nnnn00100010 1 TRAPA imm PC SPC SR SSR imm TRA 11000011iiiiiiii 8 Notes 1 The table shows the minimum number of execution cycles The actual number of instruction execution cycles will increase in cases such as the following When there is contention between an instruction fetch and data access ...

Page 94: ...0000 0000 00MD 1000 CLRT SETT CLRMAC LDTLB 0000 0000 01MD 1000 CLRS SETS 0000 0000 Fx 1001 NOP DIV0U 0000 0000 Fx 1010 0000 0000 Fx 1011 RTS SLEEP RTE 0000 Rn Fx 1000 0000 Rn Fx 1001 MOVT Rn 0000 Rn Fx 1010 STS MACH Rn STS MACL Rn STS PR Rn 0000 Rn Fx 1011 0000 Rn Rm 11MD MOV B R0 Rm Rn MOV W R0 Rm Rn MOV L R0 Rm Rn MAC L Rm Rn 0001 Rn Rm disp MOV L Rm disp 4 Rn 0010 Rn Rm 00MD MOV B Rm Rn MOV W R...

Page 95: ... LDC L Rm R0_BANK LDC L Rm R1_BANK LDC L Rm R2_BANK LDC L Rm R3_BANK 0100 Rm 11MD 0111 LDC L Rm R4_BANK LDC L Rm R5_BANK LDC L Rm R6_BANK LDC L Rm R7_BANK 0100 Rn Fx 1000 SHLL2 Rn SHLL8 Rn SHLL16 Rn 0100 Rn Fx 1001 SHLR2 Rn SHLR8 Rn SHLR16 Rn 0100 Rm Fx 1010 LDS Rm MACH LDS Rm MACL LDS Rm PR 0100 Rm Rn Fx 1011 JSR Rm TAS B Rn JMP Rm 0100 Rn Rm 1100 SHAD Rm Rn 0100 Rn Rm 1101 SHLD Rm Rn 0100 Rm 00M...

Page 96: ...1 Rn disp MOV W DISP 8 PC RN 1010 disp BRA label 12 1011 disp BSR label 12 1100 00MD imm disp MOV B R0 disp 8 GBR MOV W R0 disp 8 GBR MOV L R0 disp 8 GBR TRAPA imm 8 1100 01MD disp MOV B disp 8 GBR R0 MOV W disp 8 GBR R0 MOV L disp 8 GBR R0 MOVA disp 8 PC R0 1100 10MD imm TST imm 8 R0 AND imm 8 R0 XOR imm 8 R0 OR imm 8 R0 1100 11MD imm TST B imm 8 R0 GBR AND B imm 8 R0 GBR XOR B imm 8 R0 GBR OR B ...

Page 97: ...s altered by a reset general exception or interrupt exception handling In the case of a reset the CPU branches to address H A0000000 and starts executing the user coded exception handling program In the case of a general exception or interrupt the program counter PC contents are saved in the saved program counter SPC and the status register SR contents are saved in the saved status register SSR Th...

Page 98: ...st Bus request clearance SLEEP instruction with STBY bit set Interrupt Reset state Power down state SLEEP instruction with STBY bit cleared Bus request Bus request clearance Figure 2 8 Processor State Transitions 2 5 2 Processor Modes There are two processor modes privileged mode and user mode The processor mode is determined by the processor mode bit MD in the status register SR User mode is sele...

Page 99: ...ystem substantially more virtual memory than physical memory is provided and the process is mapped onto this virtual memory Thus a process only has to consider operation in virtual memory Mapping from virtual memory to physical memory is handled by the MMU The MMU is normally controlled by the operating system switching physical memory to allow the virtual memory required by a process to be mapped...

Page 100: ...ranslation information Unlike cache memory however if address translation fails that is if an exception is generated switching of address translation information is normally performed by software This makes it possible for memory management to be performed flexibly by software The MMU has two methods of mapping from virtual memory to physical memory a paging method using fixed length address trans...

Page 101: ...ess 1 Physical memory MMU 1 2 3 4 Process 1 Physical memory Process 1 Virtual memory MMU Physical memory Process 1 Process 2 Process 3 Physical memory Process 1 Process 2 Process 3 Virtual memory Physical memory Figure 3 1 MMU Functions ...

Page 102: ...ical address space H 00000000 to H 1FFFFFFF In the P2 area setting the top three virtual address bits bits 31 30 and 29 to 0 generates the corresponding physical address P2 area access cannot be cached The P1 and P2 areas are not mapped by the address translation table so the TLB is not used and no exceptions such as TLB misses occur Initialization of MMU control registers exception handling routi...

Page 103: ...r 3 bits are actually ignored and treated as a shadow See section 10 Bus State Controller BSC for details Address Translation When the MMU is enabled the virtual address space is divided into units called pages Physical addresses are translated in page units Address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memor...

Page 104: ...Memory Mode and Multiple Virtual Memory Mode There are two virtual memory modes single virtual memory mode and multiple virtual memory mode In single virtual memory mode multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely In multiple virtual memory mode multiple processes run in paral...

Page 105: ...the virtual address at which the exception is generated in case of an MMU exception or address error exception When the page size is 4 kbytes the VPN is the upper 20 bits of the virtual address but in this case the upper 22 bits of the virtual address are set The VPN can also be modified by software As the ASID software sets the number of the currently executing process The VPN and ASID are record...

Page 106: ... following rules in the event of an MMU exception When a TLB miss exception occurs all TLB entry ways corresponding to the virtual address at which the exception occurred are checked and if all ways are valid 1 is added to RC if there is one or more invalid way they are set by priority from way 0 in the order way 0 way 1 way 2 way 3 In the event of an MMU exception other than a TLB miss exception ...

Page 107: ...e control information for the page which is the unit of address translation Figure 3 4 shows the overall TLB configuration The TLB is 4 way set associative with 128 entries There are 32 entries for each way Figure 3 5 shows the configuration of virtual addresses and TLB entries Entry 1 Address array Data array Entry 0 Entry 1 Entry 31 Ways 0 3 Ways 0 3 VPN 11 10 VPN 31 17 ASID 7 0 V Entry 0 Entry ...

Page 108: ...een processes SZ Page size bit 0 1 kbyte page 1 4 kbyte page V Valid bit Indicates whether entry is valid 0 Invalid 1 Valid Cleared to 0 by a power on reset Not affected by a manual reset PPN Physical page number Top 29 bits of physical address PPN bits 11 10 are not used in case of a 4 kbyte page Attention must be paid to the synonym problem in case of a 1 kbyte page see section 3 4 4 Avoiding Sy...

Page 109: ...n IX 1 VPN bits 16 12 are EX ORed with ASID bits 4 0 to generate a 5 bit index number The second method is used to prevent lowered TLB efficiency that results when multiple processes run simultaneously in the same virtual address space multiple virtual memory and a specific entry is selected by generating an index number for each process Figures 3 6 and 3 7 show the indexing schemes 31 16 11 12 17...

Page 110: ...ave software ensure that TLB hits do not occur simultaneously in more than one way as hardware operation is not guaranteed if this occurs For example if there are two identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a process with ASID H FF when one is in the shared state SH 1 and the other in the non shared state SH 0 then if the ASID in PTEH is se...

Page 111: ... mode is engaged SR MD 1 all process resources can be accessed This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged The objects of address comparison are shown in figure 3 8 Bits compared VPN 31 17 VPN 11 10 SZ 0 Yes No Yes 1 kbyte No 4 kbytes Bits compared VPN 31 17 Bits compared VPN 31 17 VPN 11 10 ASID 7 0 SZ 0 Yes 1 kbyte No 4 kbytes Bit...

Page 112: ...age in privileged and user modes and is used to protect memory Attempts at nonpermitted accesses result in TLB protection violation exceptions Access states designated by the D C and PR bits are shown in table 3 2 Table 3 2 Access States Designated by D C and PR Bits Privileged Mode User Mode Reading Writing Reading Writing D bit 0 Permitted Initial page write exception Permitted Initial page writ...

Page 113: ... generated in the MMU disabled state with the AT bit cleared to 0 use in the disabled state must be avoided with software that does not use the MMU 2 TLB entry recording deletion and reading TLB entry recording can be done in two ways by using the LDTLB instruction or by writing directly to the memory mapped TLB For TLB entry deletion and reading the memory allocation TLB can be accessed See secti...

Page 114: ...rtual address that caused the exception is set in PTEH by hardware The way is set in the RC bit of MMUCR for each exception see figure 3 3 Consequently if the LDTLB instruction is issued after setting only PTEL in the MMU exception handling routine TLB entry recording is possible Any TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR As the LDTLB instruction changes ad...

Page 115: ...D VPN 0 SV 0 0 RC 0 TF IX AT PPN 0 000 V 0 PR SZ C D SH 0 Write PPN 28 10 PR 1 0 SZ C D SH Write Data array Address array Way selection Ways 0 to 3 31 9 0 MMUCR Index 31 17 12 10 8 0 PTEH register 31 28 29 10 0 PTEL register 0 31 Figure 3 9 Operation of LDTLB Instruction ...

Page 116: ...t 11 10 Consequently the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache address array For example assume that with 1 kbyte page TLB entries TLB entries for which the following translation has been performed are recorded in two TLBs Virtual address 1 H 00000000 physical address H 00000400 Virtual address 2 H 00000400 ph...

Page 117: ...ess 31 PPN 0 Offset Virtual address 11 4 Physical address 28 10 Cache address array When using a 1 kbyte page Virtual address 31 VPN 0 10 11 Offset Physical address 31 PPN 000 000 0 10 11 Offset Virtual address 11 4 Physical address 28 10 Cache address array 9 9 29 28 29 28 12 1110 Figure 3 10 Synonym Problem ...

Page 118: ...R at the time of the exception are written to the save status register SSR 6 The mode MD bit in SR is set to 1 to place the SH7709S in the privileged mode 7 The block BL bit in SR is set to 1 to mask any further exception requests 8 The register bank RB bit in SR is set to 1 9 The random counter RC field in the MMU control register MMUCR is incremented by 1 when all ways are checked for the TLB en...

Page 119: ...register 2 The virtual address causing the exception is written to the TEA register 3 Either exception code H 0A0 for a load access or H 0C0 for a store access is written to the EXPEVT register 4 The PC value indicating the address of the instruction in which the exception occurred is written into SPC if the exception occurred in a delay slot the PC value indicating the address of the related dela...

Page 120: ... at the time of the exception are written into SSR 7 The mode MD bit in SR is set to 1 to place the SH7709S in the privileged mode 8 The block BL bit in SR is set to 1 to mask any further exception requests 9 The register bank RB bit in SR is set to 1 10 Execution branches to the address obtained by adding the value of the VBR contents and H 00000100 and the TLB protection violation exception hand...

Page 121: ...he contents of SR at the time of the exception are written to SSR 6 The MD bit in SR is set to 1 to place the SH7709S in the privileged mode 7 The BL bit in SR is set to 1 to mask any further exception requests 8 The register bank RB bit in SR is set to 1 9 The way that caused the exception is set in the RC field in MMUCR 10 Execution branches to the address obtained by adding the value of the VBR...

Page 122: ...IDs match VPNs match No Yes Yes Yes Yes User or privileged D 1 C 1 V 1 No No User mode Privileged mode No No TLB protection violation exception TLB protection violation Cache access W 00 01 10 01 11 00 10 11 W W W R R R R R W R W R W R W TLB invalid exception Memory access No noncacheable Yes cacheable Figure 3 11 MMU Exception Generation Flowchart ...

Page 123: ...tion signals in the instruction fetch mode ID EX MA WB ID EX MA WB ID EX MA WB NOP NOP IF ID EX MA WB Exception source stage IF ID EX MA WB NOP MMU exception handler Handler transition processing Instruction fetch Instruction decode Instruction execution Memory access Write back No operation IF Figure 3 12 MMU Exception Signals in Instruction Fetch ...

Page 124: ...ed in the privileged mode to read and write TLB contents The TLB is mapped to the P4 area of the virtual address space The TLB address array VPN V bit and ASID is mapped to H F2000000 to H F2FFFFFF and the TLB data array PPN PR SZ CD S and H bits is mapped to H F3000000 to H F3FFFFFF It is also possible to access the V bits in the address array from the data array Only longword access is possible ...

Page 125: ...ray The data array is assigned to H F3000000 to H F3FFFFFF To access a data array the 32 bit address field for read write operations and 32 bit data field for write operations must be specified These are specified in the general register The address section specifies information for selecting the entry to be accessed the data section specifies the longword data to be written to the data array figu...

Page 126: ...12 10 11 8 9 7 6 0 0 ASID 0 V VPN 0 0 17 VPN 16 12 10 11 VPN 31 ASID 8 9 7 0 V D C SH PR SZ VPN V W Virtual page number Valid bit Way 00 Way 0 01 Way 1 10 Way 2 11 Way 3 ASID Address space identifier Don t care bit PPN PR C SH VPN X W Physical page number Protection key field Cacheable bit Share status bit Virtual page number 0 for read don t care bit for write Way 00 Way 0 01 Way 1 10 Way 2 11 Wa...

Page 127: ...ade from the entry selected by the VPN 16 12 B 1 0011 index the V bit of the hit way is cleared to 0 achieving invalidation MOV L R0 R1 Reading the Data of a Specific Entry This example reads the data section of a specific TLB entry The bit order indicated in the data field in figure 3 14 2 is read R0 specifies the address and the data section of a selected entry is read to R1 R1 H F300 4300 VPN 1...

Page 128: ...Rev 5 00 09 03 page 84 of 760 ...

Page 129: ...alized by software Table 4 1 Register Configuration Register Abbr R W Size Initial Value Address TRAPA exception register TRA R W Longword Undefined H FFFFFFD0 Exception event register EXPEVT R W Longword Power on reset H 000 Manual reset H 020 1 H FFFFFFD4 Interrupt event register INTEVT R W Longword Undefined H FFFFFFD8 Interrupt event register2 INTEVT2 R Longword Undefined H 04000000 H A4000000...

Page 130: ...r address is fixed at H A0000000 The other three events are assigned offsets from the vector base address by software Translation look aside buffer TLB miss exceptions have an offset from the vector base address of H 00000400 The vector address offset for general exception events other than TLB miss exceptions is H 00000100 The interrupt vector address offset is H 00000600 The vector base address ...

Page 131: ...access not in repeat loop 2 7 H 00000400 TLB invalid data access 2 8 H 00000100 TLB protection violation data access 2 9 H 00000100 Initial page write 2 10 H 00000100 Completed Unconditional trap TRAPA instruction 2 5 H 00000100 User breakpoint trap 2 n 2 H 00000100 DMA address error 2 H 00000100 Completed Nonmaskable interrupt 3 H 00000600 General interrupt requests External hardware interrupt 4 ...

Page 132: ...n i e execution order but are handled at priority level 2 in instruction stream order i e program order where an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction Three general exception events reserved instruction code exception unconditional trap and slot illegal instruction exception are detected in the decode stage ID stage of ...

Page 133: ...mory access Write back Handling Order Program Order TLB miss instruction n 1 TLB miss instruction n and general illegal instruction exception instruction n 2 simultaneous detection Detection Order Figure 4 2 Example of Acceptance Order of General Exceptions All exceptions other than a reset are detected in the pipeline ID stage and accepted at instruction boundaries However an exception is not acc...

Page 134: ...fic exception event Table 4 3 Exception Codes Exception Type Exception Event Exception Code Reset Power on reset H 000 Manual reset H 020 UDI reset H 000 General exception events TLB miss invalid read H 040 TLB miss invalid write H 060 Initial page write H 080 TLB protection violation read H 0A0 TLB protection violation write H 0C0 CPU address error read H 0E0 CPU address error write H 100 Uncondi...

Page 135: ...ters are set to their post reset state other module registers retain their contents prior to the general exception and a branch is made to the same address H A0000000 as for a reset If a general interrupt occurs when BL 1 the request is masked held pending and not accepted until the BL bit is cleared to 0 by software For reentrant exception handling SPC and SSR must be saved and the BL bit in SR c...

Page 136: ...bles 6 4 and 6 5 The exception code or interrupt priority code is set automatically by hardware when an exception occurs INTEVT can also be modified by software 3 Interrupt event register 2 INTEVT2 resides at address H 04000000 and contains a 12 bit exception code The exception code set in INTEVT2 is that for an interrupt request The exception code is set automatically by hardware when an exceptio...

Page 137: ...o 1 4 An encoded value of H 000 in a power on reset or H 020 in a manual reset is written to bits 11 0 of the EXPEVT register to identify the exception event 5 Instruction execution jumps to the user written exception handler at address H A0000000 4 4 2 Interrupts An interrupt handling request is accepted on completion of the current instruction The interrupt acceptance sequence consists of the fo...

Page 138: ...ling and this LSI operations 4 5 1 Resets Power On Reset Conditions RESETP low Operations EXPEVT set to H 000 VBR and SR initialized branch to PC H A0000000 Initialization sets the VBR register to H 0000000 In SR the MD RB and BL bits are set to 1 and the interrupt mask bits I3 to I0 are set to B 1111 The CPU and on chip peripheral modules are initialized See the register descriptions in the relev...

Page 139: ...zed UDI reset UDI reset command input Initialized 4 5 2 General Exceptions TLB miss exception Conditions Comparison of TLB addresses shows no address match Operations The virtual address 32 bits that caused the exception is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 The ASID of PTEH indicates the ASID at the time the exception occurred If all ways are valid 1...

Page 140: ...r 22 bits is set in PTEH 31 10 The ASID of PTEH indicates the ASID at the time the exception occurred The way that generated the exception is set in the RC bit in MMUCR PC and SR of the instruction that generated the exception are saved to SPC and SSR respectively H 080 is set in EXPEVT The BL MD and RB bits in SR are set to 1 and a branch occurs to PC VBR H 0100 TLB protection exception Condition...

Page 141: ... is a processing completion type so PC of the instruction after the TRAPA instruction is saved to SPC SR from the time when the TRAPA instruction was executing is saved to SSR The 8 bit immediate value in the TRAPA instruction is quadrupled and set in TRA 9 0 H 160 is set in EXPEVT The BL MD and RB bits in SR are set to 1 and a branch occurs to PC VBR H 0100 Illegal general instruction exception C...

Page 142: ...nstruction other than H Fxxx is decoded operation cannot be guaranteed User break point trap Conditions When a break condition set in the user break controller is satisfied Operations When a post execution break occurs PC of the instruction immediately after the instruction that set the break point is set in SPC If a pre execution break occurs PC of the instruction that set the break point is set ...

Page 143: ... received level is not set in SR IMASK See section 6 Interrupt Controller INTC for more information 3 IRQ Pin Interrupts Conditions The IRQ pin is asserted SR IMASK is lower than the IRQ priority level and the BL bit in SR is 0 The interrupt is accepted at an instruction boundary Operations The PC value after the instruction at which the interrupt is accepted is saved to SPC SR at the point the in...

Page 144: ...B bits in SR are set to 1 and a branch occurs to VBR H 0600 See section 6 Interrupt Controller INTC for more information 4 6 Cautions Return from exception handling Check the BL bit in SR with software When SPC and SSR have been saved to external memory set the BL bit in SR to 1 before restoring them Issue an RTE instruction which sets SPC in PC and SSR in SR and causes a branch to the SPC address...

Page 145: ... a conditional delayed branch instruction however the branch destination PC is set in SPC If the condition of the conditional delayed branch instruction is not satisfied the delay slot PC is set in SPC Initial register values after reset Undefined registers R0_BANK0 1 R7_BANK0 1 R8 R15 GBR SPC SSR MACH MACL PR Initialized registers VBR H 00000000 SR MD 1 SR BL 1 SR RB 1 SR I3 SR I0 H F Other SR bi...

Page 146: ...Rev 5 00 09 03 page 102 of 760 ...

Page 147: ...te through selectable Replacement method Least recently used LRU algorithm 5 1 2 Cache Structure The cache mixes data and instructions and uses a 4 way set associative system It is composed of four ways banks each of which is divided into an address section and a data section Each of the address and data sections is divided into 256 entries The data section of the entry is called a line Each line ...

Page 148: ...ower on reset but are not initialized by a manual reset The tag address is not initialized by either a power on or manual reset Data Array Holds a 16 byte instruction or data Entries are registered in the cache in line units 16 bytes The data array is not initialized by a power on or manual reset LRU With the 4 way set associative system up to four instructions or data with the same entry address ...

Page 149: ...ddress Access Size Cache control register CCR R W H 00000000 H FFFFFFEC 32 bit Cache control register 2 CCR2 R W H 00000000 H 040000B0 H A40000B0 32 bit Note When address translation by the MMU does not apply the address in parentheses should be used 5 2 Register Description 5 2 1 Cache Control Register CCR The cache is enabled or disabled using the CE bit of the cache control register CCR CCR als...

Page 150: ...n a prefetch instruction PREF is executed in cache locking mode and a cache miss occurs one line size of data pointed to by Rn is brought to cache according to the setting of bits 9 and 8 W3LOAD and W3LOCK and bits 1 and 0 W2LOAD and W2LOCK in CCR2 Table 5 4 shows the relationship between the bit setting and way to be replaced when a prefetch instruction is executed When a prefetch instruction is ...

Page 151: ...ot be set to high at the same time Reserved bits Figure 5 3 CCR2 Register Configuration Whenever CCR2 bit 8 W3LOCK or bit 0 W2LOCK is high the cache is locked The locked data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF condition during DSP mode matched During cache locking mode the LRU in table 5 2 will be replaced by tables 5 4 to 5 8 Table 5 4 Way Replacement w...

Page 152: ...001 000100 010100 100000 100001 110000 110100 3 000011 000110 000111 001011 001111 010110 011110 011111 1 101001 101011 111000 111001 111011 111100 111110 111111 0 Table 5 7 LRU and Way Replacement when W3LOCK 1 LRU 5 0 Way to be Replaced 000000 000001 000011 001011 100000 100001 101001 101011 2 000100 000110 000111 001111 010100 010110 011110 011111 1 110000 110100 111000 111001 111011 111100 111...

Page 153: ...re selected using bits 11 4 of the address virtual of the access to memory and the address tag of that entry is read In parallel to reading of the address tag the virtual address is translated to a physical address in the MMU The physical address after translation and the physical address read from the address section are compared The address comparison uses all four ways When the comparison shows...

Page 154: ...Ways 0 3 31 12 11 4 3 2 1 0 Virtual address CMP0 CMP1 CMP2 CMP3 Physical address CMP0 Comparison circuit 0 CMP1 Comparison circuit 1 CMP2 Comparison circuit 2 CMP3 Comparison circuit 3 Hit signal 1 Entry selection Longword LW selection MMU Figure 5 4 Cache Search Scheme Normal Mode ...

Page 155: ...he entry written is set to 1 Writing occurs only to the cache no external memory write cycle is issued In the write through mode the data is written to the cache and an external memory write cycle is issued Write Miss In the write back mode an external write cycle starts when a write miss occurs and the entry is updated The way to be replaced is shown in table 5 5 When the U bit of the entry to be...

Page 156: ...00000 to H F0FFFFFF and the data array onto addresses H F1000000 to H F1FFFFFF Only longword can be used as the access size for the address array and data array and instruction fetches cannot be performed 5 4 1 Address Array The address array is mapped to H F0000000 to H F0FFFFFF The 32 bit address field for read write accessed and 32 bit data field for write access must be specified to access an ...

Page 157: ...or a match The values of the U bit and V bit specified in the data field will be written to the way that has a hit However the tag address and the LRU will not be changed If no way receives a hit writing does not take place and the result is no operation This operation is used to invalidate the address specification for a cache Write back will take place when the U bit of the entry that received a...

Page 158: ...fied in the address field The longword data will be written to the entry at the position selected by the L bits 3 2 of the address field 1 Address array access Address specification Read access Write access Data specification both read and write accesses 2 Data array access both read and write accesses Address specification 31 24 23 14 13 12 11 4 3 0 1111 0000 W Entry address 31 24 23 14 13 12 11 ...

Page 159: ... A 0 MOV L R0 R1 To invalidate all entries and ways write 0 to the following addresses Addresses F000 0000 F000 0010 F000 0020 F000 3FF0 This involves a total of 1 024 writes The above operation should be performed using a non cacheable area 2 Invalidating a Specific Address A specific address can be invalidated by writing a 0 to the entry s U and V bits When the A bit is 1 the tag address specifi...

Page 160: ...MOV L H 1FFFFC00 R3 AND R0 R3 The tag address is fetched U V 0 MOV L R3 R2 Associative purge The above operation should be performed using a non cacheable area 3 Reading Data from a Specific Entry This example reads the data section of a specific entry The longword in the data field of the data array in figure 5 6 is read to the register R0 H F100 004C Data array access Entry H 04 Way 0 Longword a...

Page 161: ...errupt priority registers the priorities of on chip peripheral module IRQ and PINT interrupts can be selected from 16 levels for individual request sources NMI noise canceler function An NMI input level bit indicates the NMI pin state By reading this bit in the interrupt exception service routine the pin state can be checked enabling it to be used as a noise canceler External devices can be notifi...

Page 162: ...hdog timer Refresh requests in the bus state controller Interrupt control register Interrupt priority registers A E Status register Direct memory access controller Analog to digital converter User debugging interface Legend TMU RTC SCI IrDA SCIF WDT REF ICR IPRA IPRE SR DMAC ADC UDI Interrupt request SCIF TMU Interrupt request Interrupt request IPR CPU Internal bus Bus interface 2 1 0 Interrupt re...

Page 163: ...askable by the interrupt mask bits in SR Interrupt input pins IRQ5 IRQ0 IRL3 IRL0 IRLS3 IRLS0 I Input of interrupt request signals maskable by the interrupt mask bits in SR Port interrupt input pins PINT0 PINT15 I Input of port interrupt request signals maskable by the interrupt mask bits in SR Bus request output pin IRQOUT O Output of signal that notifies external devices that an interrupt source...

Page 164: ... H FFFFFEE2 16 Interrupt priority register B IPRB R W H 0000 H FFFFFEE4 16 Interrupt priority register C IPRC R W H 0000 H 04000016 H A4000016 3 16 Interrupt priority register D IPRD R W H 0000 H 04000018 H A4000018 3 16 Interrupt priority register E IPRE R W H 0000 H 0400001A H A400001A 3 16 Interrupt request register 0 IRR0 R W H 00 H 04000004 H A4000004 3 8 Interrupt request register 1 IRR1 R H...

Page 165: ...et to 1 and only NMI interrupts are accepted the SPC register and SSR register are updated by the NMI interrupt handler making it impossible to return to the original processing from exception handling initiated prior to the NMI interrupt Use should therefore be restricted to cases where return is not necessary It is possible to wake the chip up from the standby state with an NMI interrupt except ...

Page 166: ...cted if the IRQ edge is input during frequency change processing WDT count 6 2 3 IRL Interrupts IRL interrupts are input by level at pins IRL3 IRL0 and IRLS3 IRLS0 IRLS3 IRLS0 are enabled when the IRQLVL bit and IRLSEN bit in interrupt control register 1 ICR1 are both 1 The priority level is the higher level indicated by pins IRL3 IRL0 and IRLS3 IRLS0 An IRL3 IRL0 IRLS3 IRLS0 value of 0 0000 indic...

Page 167: ...0 1 2 Level 2 interrupt request 1 1 1 0 1 Level 1 interrupt request 1 1 1 1 0 No interrupt request A noise cancellation feature is built in and the IRL interrupt is not detected unless the levels sampled at every peripheral module clock cycle remain unchanged for two consecutive cycles so that no transient level on the IRL IRLS pin change is detected In standby mode as the peripheral clock is stop...

Page 168: ...ated by the following ten modules Timer unit TMU Realtime clock RTC Serial communication interfaces SCI IrDA SCIF Bus state controller BSC Watchdog timer WDT Direct memory access controller DMAC Analog to digital converter ADC User debugging interface UDI Not every interrupt source is assigned a different interrupt vector Sources are reflected in the interrupt event registers INTEVT and INTEVT2 It...

Page 169: ...EVT2 is used as offset at the start of the interrupt service routine and branched to in order to identify the interrupt source The priority of the on chip peripheral module IRQ and PINT interrupts is set within priority levels 0 15 as required by using interrupt priority registers A E IPRA IPRE The priority of the on chip peripheral module IRQ and PINT interrupts is set to 0 by a reset When the pr...

Page 170: ...PRD 3 0 IRQ5 H 200 3C0 H 6A0 0 15 0 IPRD 7 4 PINT PINT0 7 H 200 3C0 H 700 0 15 0 IPRD 15 12 PINT8 15 H 200 3C0 H 720 0 15 0 IPRD 11 8 DMAC DEI0 H 200 3C0 H 800 0 15 0 IPRE 15 12 High DEI1 H 200 3C0 H 820 DEI2 H 200 3C0 H 840 DEI3 H 200 3C0 H 860 Low IrDA ERI1 H 200 3C0 H 880 0 15 0 IPRE 11 8 High RXI1 H 200 3C0 H 8A0 BRI1 H 200 3C0 H 8C0 TXI1 H 200 3C0 H 8E0 Low SCIF ERI2 H 200 3C0 H 900 0 15 0 IP...

Page 171: ...Priority RTC ATI H 480 H 480 0 15 0 IPRA 3 0 High High PRI H 4A0 H 4A0 CUI H 4C0 H 4C0 Low SCI ERI H 4E0 H 4E0 0 15 0 IPRB 7 4 High RXI H 500 H 500 TXI H 520 H 520 TEI H 540 H 540 Low WDT ITI H 560 H 560 0 15 0 IPRB 15 12 REF RCMI H 580 H 580 0 15 0 IPRB 11 8 High ROVI H 5A0 H 5A0 Low Low Note The code corresponding to an interrupt level shown in table 6 6 is set ...

Page 172: ...2 0110 H 2C0 H 2C0 9 IRL 3 0 2 0111 H 2E0 H 2E0 8 IRL 3 0 2 1000 H 300 H 300 7 IRL 3 0 2 1001 H 320 H 320 6 IRL 3 0 2 1010 H 340 H 340 5 IRL 3 0 2 1011 H 360 H 360 4 IRL 3 0 2 1100 H 380 H 380 3 IRL 3 0 2 1101 H 3A0 H 3A0 2 IRL 3 0 2 1110 H 3C0 H 3C0 1 IRQ IRQ4 H 200 3C0 1 H 680 0 15 0 IPRD 3 0 IRQ5 H 200 3C0 1 H 6A0 0 15 0 IPRD 7 4 PINT PINT0 7 H 200 3C0 1 H 700 0 15 0 IPRD 15 12 PINT8 15 H 200 3...

Page 173: ... 0 15 0 IPRA 15 12 TMU1 TUNI1 H 420 H 420 0 15 0 IPRA 11 8 TMU2 TUNI2 H 440 H 440 0 15 0 IPRA 7 4 High TICPI2 H 460 H 460 Low RTC ATI H 480 H 480 0 15 0 IPRA 3 0 High PRI H 4A0 H 4A0 CUI H 4C0 H 4C0 Low SCI ERI H 4E0 H 4E0 0 15 0 IPRB 7 4 High RXI H 500 H 500 TXI H 520 H 520 TEI H 540 H 540 Low WDT ITI H 560 H 560 0 15 0 IPRB 15 12 REF RCMI H 580 H 580 0 15 0 IPRB 11 8 High ROVI H 5A0 H 5A0 Low Lo...

Page 174: ...3 page 130 of 760 Table 6 6 Interrupt Levels and INTEVT Codes Interrupt level INTEVT Code 15 H 200 14 H 220 13 H 240 12 H 260 11 H 280 10 H 2A0 9 H 2C0 8 H 2E0 7 H 300 6 H 320 5 H 340 4 H 360 3 H 380 2 H 3A0 1 H 3C0 ...

Page 175: ... R W R W Table 6 7 lists the relationship between the interrupt sources and the IPRA IPRE bits Table 6 7 Interrupt Request Sources and IPRA IPRE Register Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPRA TMU0 TMU1 TMU2 RTC IPRB WDT REF SCI0 Reserved IPRC IRQ3 IRQ2 IRQ1 IRQ0 IPRD PINT0 to PINT7 PINT8 to PINT15 IRQ5 IRQ4 IPRE DMAC IrDA SCIF ADC Note Always read as 0 Only 0 should be written As...

Page 176: ... 0 R W R R R R R R R R Note 1 when NMI input is high 0 when NMI input is low Bit 15 NMI Input Level NMIL Sets the level of the signal input at the NMI pin This bit can be read to determine the NMI pin level This bit cannot be modified Bit 15 NMIL Description 0 NMI input level is low 1 NMI input level is high Bit 8 NMI Edge Select NMIE Selects whether the falling or rising edge of the interrupt req...

Page 177: ...to 1 all interrupt requests are masked while a low level is being input to the NMI pin Masks NMI interrupts in standby mode Bit 15 MAI Description 0 All interrupt requests are not masked when NMI pin is low level Initial value 1 All interrupt requests are masked when NMI pin is low level Bit 14 Interrupt Request Level Detect IRQLVL Selects whether the IRQ3 IRQ0 pins are used as four independent in...

Page 178: ...w level 1 Reserved Bits 9 and 8 IRQ4 Sense Select IRQ41S IRQ40S Select whether the interrupt signal to the IRQ4 pin is detected at the rising edge at the falling edge or at the low level Bit 9 IRQ41S Bit 8 IRQ40S Description 0 0 An interrupt request is detected at IRQ4 input falling edge Initial value 1 An interrupt request is detected at IRQ4 input rising edge 1 0 An interrupt request is detected...

Page 179: ... pin is detected at the rising edge at the falling edge or at the low level Bit 3 IRQ11S Bit 2 IRQ10S Description 0 0 An interrupt request is detected at IRQ1 input falling edge Initial value 1 An interrupt request is detected at IRQ1 input rising edge 1 0 An interrupt request is detected at IRQ1 input low level 1 Reserved Bits 1 and 0 IRQ0 Sense Select IRQ01S IRQ00S Select whether the interrupt s...

Page 180: ...0S PINT9S PINT8S Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 0 PINT15 to PINT0 Sense Select PINT15S to PINT0S Select whether interrupt request signals to PINT15 to PINT0 are detected at the low level or high level Bits 15 0 P...

Page 181: ...value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 0 PINT15 to PINT0 Interrupt Enable PINT15E to PINT0E Enable or diable interrupt request input to pins PINT15 to PINT0 Bits 15 0 PINT15E to PINT0E Description 0 PINT input interrupt requests...

Page 182: ...is written do not change Bit 7 PINT0 to PINT7 Interrupt Request PINT0R Indicates whether there is interrupt request input to pins PINT0 to PINT7 Bit 7 PINT0R Description 0 No interrupt request to pins PINT0 to PINT7 Initial value 1 Interrupt to pins PINT0 to PINT7 Bit 6 PINT8 to PINT15 Interrupt Request PINT1R Indicates whether there is interrupt request input to pins PINT8 to PINT15 Bit 6 PINT1R ...

Page 183: ...es whether there is interrupt request input to the IRQ2 pin When edge detection mode is set for IRQ2 an interrupt request is cleared by clearing the IRQ2R bit Bit 2 IRQ2R Description 0 No interrupt request input to IRQ2 pin Initial value 1 Interrupt request input to IRQ2 pin Bit 1 IRQ1 Interrupt Request IRQ1R Indicates whether there is interrupt request input to the IRQ1 pin When edge detection mo...

Page 184: ...ion 0 TXI1 interrupt request not generated Initial value 1 TXI1 interrupt request generated Bit 6 BRI1 Interrupt Request BRI1R Indicates whether a BRI1 IrDA interrupt request has been generated Bit 6 BRI1R Description 0 BRI1 interrupt request not generated Initial value 1 BRI1 interrupt request generated Bit 5 RXI1 Interrupt Request RXI1R Indicates whether an RXI1 IrDA interrupt request has been g...

Page 185: ...rrupt request has been generated Bit 1 DEI1R Description 0 DEI1 interrupt request not generated Initial value 1 DEI1 interrupt request generated Bit 0 DEI0 Interrupt Request DEI0R Indicates whether a DEI0 DMAC interrupt request has been generated Bit 0 DEI0R Description 0 DEI0 interrupt request not generated Initial value 1 DEI0 interrupt request generated 6 3 8 Interrupt Request Register 2 IRR2 I...

Page 186: ... Initial value 1 TXI2 interrupt request generated Bit 2 BRI2 Interrupt Request BRI2R Indicates whether a BRI2 SCIF interrupt request has been generated Bit 2 BRI2R Description 0 BRI2 interrupt request not generated Initial value 1 BRI2 interrupt request generated Bit 1 RXI2 Interrupt Request RXI2R Indicates whether an RXI2 SCIF interrupt request has been generated Bit 1 RXI2R Description 0 RXI2 in...

Page 187: ...ation with the peripheral clock Pφ The CPU receives an interrupt at a break in instructions 5 The interrupt source code is set in the interrupt event registers INTEVT and INTEVT2 6 The status register SR and program counter PC are saved to SSR and SPC respectively 7 The block bit BL mode bit MD and register bank bit RB in SR are set to 1 8 The CPU jumps to the start address of the interrupt handle...

Page 188: ...rupt generated NMI low SR BL 0 or sleep mode Yes Yes Yes Yes Yes Yes No No No No No No No ICR1 BLMSK 1 NMI NMI IRQOUT low Set interrupt cause in INTEVT INTEVT2 Save SR to SSR save PC to SPC Set BL MD RB bits in SR to 1 Branch to exception handler I3 I0 level 14 or lower Level 14 interrupt I3 I0 level 13 or lower Level 1 interrupt I3 I0 level 0 Figure 6 3 Interrupt Operation Flowchart ...

Page 189: ...n SR 5 Handle the interrupt 6 Execute the RTE instruction When these procedures are followed in order an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4 Figure 6 3 shows a sample interrupt operation flowchart 6 5 Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching o...

Page 190: ...terrupt exception handling is kept waiting until the executing instruc tion ends If the number of instruc tion execution states is S 1 the maximum wait time is X S 1 However if BL is set to 1 by instru ction execution or by an exception interrupt exception handling is deferred until completion of an instruction that clears BL to 0 If the following instruction masks interrupt exception handling the...

Page 191: ...upplied to CPU Bcyc Duration of one CKIO cycle Pcyc Duration of one cycle of peripheral clock supplied to peripheral modules Notes 1 S also includes the memory access wait time The processing requiring the maximum execution time is LDC L Rm SR When the memory access is a cache hit this requires seven instruction execution cycles When the external access is performed the corresponding number of cyc...

Page 192: ...X 5 Icyc Start of interrupt handling IF Instruction fetch Instruction is fetched from memory in which program is stored ID Instruction decode Fetched instruction is decoded EX Instruction execution Data operation and address calculation are performed Overrun fetch First instruction of interrupt handler Figure 6 4 Example of Pipeline Operations when IRL Interrupt is Accepted ...

Page 193: ...nnel B match with logical AND but not in the same bus cycle Address Compares 40 bits comprised of a 32 bit logical address prefixed with an ASID address Comparison bits are maskable in 32 bit units user can easily program it to mask addresses at bottom 12 bits 4 k page bottom 10 bits 1 k page or any size of page etc One of two address buses CPU address bus LAB cache address bus IAB can be selected...

Page 194: ... break request UBC Location CCN Location LDB IDB XDB YDB Access Control Legend BBRA Break bus cycle register A BARA Break address register A BAMRA Break address mask register A BASRA Break ASID register A BBRB Break bus cycle register B BARB Break address register B BAMRB Break address mask register B BASRB Break ASID register B BDRB Break data register B BDMRB Break data mask register B BETR Brea...

Page 195: ...0 H FFFFFFA8 16 UBC Break data register B BDRB R W H 00000000 H FFFFFF90 32 UBC Break data mask register B BDMRB R W H 00000000 H FFFFFF94 32 UBC Break control register BRCR R W H 00000000 H FFFFFF98 32 UBC Execution count break register BETR R W H 0000 H FFFFFF9C 16 UBC Branch source register BRSR R Undefined 2 H FFFFFFAC 32 UBC Branch destination register BRDR R Undefined 2 H FFFFFFBC 32 UBC Bre...

Page 196: ... W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Initial value 0 0 0 0 0 0 0 0 R W...

Page 197: ...0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 31 to 0 Break Address Mask Register A31 to A0 BAMA31 to BAMA0 Specifies bits ...

Page 198: ... write value should always be 0 Bits 7 and 6 CPU Cycle DMAC Cycle Select A CDA1 CDA0 Selects the CPU cycle or DMAC cycle as the bus cycle of the channel A break condition Bit 7 CDA1 Bit 6 CDA0 Description 0 0 Condition comparison is not performed Initial value 1 The break condition is the CPU cycle 1 0 The break condition is the DMAC cycle Don t care Bits 5 and 4 Instruction Fetch Data Access Sele...

Page 199: ...condition is the read cycle 1 0 The break condition is the write cycle 1 The break condition is the read cycle or write cycle Bits 1 and 0 Operand Size Select A SZA1 SZA0 Selects the operand size of the bus cycle for the channel A break condition Bit 1 SZA1 Bit 0 SZA0 Description 0 0 The break condition does not include operand size Initial value 1 The break condition is byte access 1 0 The break ...

Page 200: ...BAB25 BAB24 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAB7 BAB6 BAB5 BAB4 BA...

Page 201: ...0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 31 to 0 Break Address Mask Register B31 to B0 BAMB31 to BAMB0 Specifies b...

Page 202: ...ial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB...

Page 203: ...B9 BDMB8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 31 to 0 Break Data Mask Register B31 to B0 BDMB31 to BDMB0 Specifies bits in the channel B break data bits specified by BDRB BDB31 BDB0 Bits 31 to 0 BDMBn Description 0 Break data BDBn o...

Page 204: ...ese bits are always read as 0 Bits 7 and 6 CPU Cycle DMAC Cycle Select B CDB1 CDB0 Select the CPU cycle or DMAC cycle as the bus cycle of the channel B break condition Bit 7 CDB1 Bit 6 CDB0 Description 0 0 Condition comparison is not performed Initial value 1 The break condition is the CPU cycle 1 0 The break condition is the DMAC cycle Don t care Bits 5 and 4 Instruction Fetch Data Access Select ...

Page 205: ...condition is the read cycle 1 0 The break condition is the write cycle 1 The break condition is the read cycle or write cycle Bits 1 and 0 Operand Size Select B SZB1 SZB0 Select the operand size of the bus cycle for the channel B break condition Bit 1 SZB1 Bit 0 SZB0 Description 0 0 The break condition does not include operand size Initial value 1 The break condition is byte access 1 0 The break c...

Page 206: ...CR is a 32 bit read write register that has break conditions match flags and bits for setting a variety of break conditions A power on reset initializes BRCR to H 00000000 Bit 31 30 29 28 27 26 25 24 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 BASMA BASMB Initial value 0 0 0 0 0 0 0 0 R W R R R W R W R R R R Bit 15 14 13 12 11 10 9 8 SCMFCA SCMFCB SCMFDA SCMFDB PC...

Page 207: ...ASID is not checked Bits 19 to 16 Reserved These bits are always read as 0 The write value should always be 0 Bit 15 CPU Condition Match Flag A SCMFCA When the CPU bus cycle condition in the break conditions set for channel A is satisfied this flag is set to 1 not cleared to 0 In order to clear this flag write 0 into this bit Bit 15 SCMFCA Description 0 The CPU cycle condition for channel A does n...

Page 208: ...channel B does not match Initial value 1 The DMAC cycle condition for channel B matches Bit 11 PC Trace Enable PCTE Enables PC trace Bit 11 PCTE Description 0 Disables PC trace Initial value 1 Enables PC trace Bit 10 PC Break Select A PCBA Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution Bit 10 PCBA Description 0 PC break of channel A i...

Page 209: ...l Bit 3 SEQ Description 0 Channels A and B are compared under the independent condition Initial value 1 Channels A and B are compared under the sequential condition channel A then channel B Bits 2 and 1 Reserved These bits are always read as 0 The write value should always be 0 Bit 0 The Number of Execution Times Break Enable ETBE Enable the execution times break condition only on channel B If thi...

Page 210: ...times A power on reset initializes BETR to H 0000 When a break condition is satisfied it decreases the BETR A break is issued when the break condition is satisfied after the BETR becomes H 0001 Bits 15 12 are always read as 0 and 0 should always be written in these bits Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0...

Page 211: ...1 30 29 28 27 26 25 24 SVF PID2 PID1 PID0 BSA27 BSA26 BSA25 BSA24 Initial value 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 Initial value R W R R R R R R R R Bit 15 14 13 12 11 10 9 8 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 Initial value R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 Initial value R W R R ...

Page 212: ... branch destination fetch address BRDR has the flag bit that is set to 1 when branch occurs This flag bit is cleared to 0 when BRDR is read and also initialized by power on resets or manual resets Other bits are not initialized by resets Eight BRDR registers have queue structure and a stored register is shifted every branch Bit 31 30 29 28 27 26 25 24 DVF BDA27 BDA26 BDA25 BDA24 Initial value 0 R ...

Page 213: ... specifies the ASID that serves as the break condition for channel A It is not initialized by resets Bit 7 6 5 4 3 2 1 0 BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined value Bits 7 to 0 Break ASID A7 to 0 BASA7 to BASA0 These bits store the ASID bits 7 to 0 that is the channel A break condition 7 2 14 Break ASID Register B BASRB Bre...

Page 214: ...ppropriate condition match flags SCMFCA SCMFDA SCMFCB and SCMFDB can be used to check if the set conditions match or not The matching of the conditions sets flags but they are not reset 0 must first be written to them before they can be used again 4 There is a chance that the data access break and its following instruction fetch break occur around the same time there will be only one break request...

Page 215: ... bits 31 1 to address bus bits 31 1 Byte Compares break address register bits 31 0 to address bus bits 31 0 This means that when address H 00001003 is set without specifying the size condition for example the bus cycle in which the break condition is satisfied is as follows where other conditions are met Longword access at H 00001000 Word access at H 00001002 Byte access at H 00001003 3 When the d...

Page 216: ...unter PC saved is the address of the instruction that matches the break condition The fetched instruction is not executed and a break occurs before it 2 When instruction fetch after instruction execution is specified as a break condition The PC value saved is the address of the instruction to be executed following the instruction in which the break condition matches The fetched instruction is exec...

Page 217: ... only to this case and then some cases are classified as follows Exec branch Dest Dest instr not executed interrupt Int interrupt routine If the PID value is odd instruction buffer indicates PID 2 buffer However these expressions in this table are accounted for it Therefore the true branch source address is calculated with BSA and PID values stored in BRSR 3 The branch address before branch occurr...

Page 218: ...B H 00000000 BDMRB H 00000000 BRCR H 00300400 Specified conditions Channel A channel B independent mode Channel A Address H 00000404 Address mask H 00000000 Bus cycle CPU instruction fetch after instruction execution read operand size is not included in the condition No ASID check is included Channel B Address H 00008010 Address mask H 00000006 Data H 00000000 Data mask H 00000000 Bus cycle CPU in...

Page 219: ...break occurs before an instruction with ASID H 70 and address H 0003722E is executed 3 Register specifications BARA H 00027128 BAMRA H 00000000 BBRA H 005A BARB H 00031415 BAMRB H 00000000 BBRB H 0054 BDRB H 00000000 BDMRB H 00000000 BRCR H 00300000 Specified conditions Channel A channel B independent mode Channel A Address H 00027128 Address mask H 00000000 Bus cycle CPU instruction fetch before ...

Page 220: ...tion does not match Therefore no user break occurs 5 Register specifications BARA H 00000500 BAMRA H 00000000 BBRA H 0057 BARB H 00001000 BAMRB H 00000000 BBRB H 0057 BDRB H 00000000 BDMRB H 00000000 BRCR H 00300001 BETR H 0005 Specified conditions Channel A channel B independent mode Channel A Address H 00000500 Address mask H 00000000 Bus cycle CPU instruction fetch before instruction execution ...

Page 221: ...00008FFE is executed or before instructions with ASID H 70 and addresses H 00008010 to H 00008016 are executed Break Condition Specified to a CPU Data Access Cycle 1 Register specifications BARA H 00123456 BAMRA H 00000000 BBRA H 0064 BARB H 000ABCDE BAMRB H 000000FF BBRB H 006A BDRB H 0000A512 BDMRB H 00000000 BRCR H 00000080 BASRA H 80 BASRB H 70 Specified conditions Channel A channel B independ...

Page 222: ...A channel B independent mode Channel A Address H 00314156 Address mask H 00000000 ASID H 80 Bus cycle DMAC instruction fetch read operand size is not included in the condition Channel B Address H 00055555 Address mask H 00000000 ASID H 70 Data H 00000078 Data mask H 0000000F Bus cycle DMAC data access write byte On channel A no user break occurs since instruction fetch is not performed in DMAC cyc...

Page 223: ...tch cycle in BBRA the attention is as follows A break is issued and condition match flags in BRCR are set to 1 when the bus cycle conditions both for channels A and B match simultaneously 4 The change of a UBC register value is executed in MA memory access stage Therefore even if the break condition matches in the instruction fetch address following the instruction in which the pre execution break...

Page 224: ...Rev 5 00 09 03 page 180 of 760 ...

Page 225: ...s The SH7709S has the following power down modes and function 1 Sleep mode 2 Standby mode 3 Module standby function TMU RTC SCI UBC DMAC DAC ADC SCIF and IrDA on chip peripheral modules 4 Hardware standby mode Table 8 1 shows the transition conditions for entering the modes from the program execution state as well as the CPU and peripheral module states in each mode and the procedures for cancelin...

Page 226: ...f refresh 1 Interrupt 2 Reset Module standby function Set MSTP bit to 1 in STBCR Runs Runs or halts Held Held Specified module halts 2 Refresh 1 Clear MSTP bit to 0 2 Reset Hardware standby mode Drive CA pin low Halts Halts Held Held Halt 3 Held Self refresh Power on reset Notes 1 The RTC still runs if the START bit in RCR2 is set to 1 see section 13 Realtime Clock RTC The TMU still runs when outp...

Page 227: ...Configuration Table 8 3 shows the control register configuration for the power down modes Table 8 3 Register Configuration Name Abbreviation R W Initial Value Access Size Address Standby control register STBCR R W H 00 H FFFFFF82 8 Standby control register 2 STBCR2 R W H 00 H FFFFFF88 8 Note Initialized by a power on reset This value is not initialized by a manual reset the current value is retain...

Page 228: ...s in standby mode Bit 2 Module Standby 2 MSTP2 Specifies halting of the clock supply to the timer unit TMU an on chip peripheral module When the MSTP2 bit is set to 1 the supply of the clock to the TMU is halted Bit 2 MSTP2 Description 0 TMU runs Initial value 1 Clock supply to TMU is halted Bit 1 Module Standby 1 MSTP1 Specifies halting of the clock supply to the realtime clock RTC an on chip per...

Page 229: ...3 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 Reserved The write value set in the program should always be 1 Bit 6 Pin MD5 to MD0 Control MDCHG Specifies whether or not pins MD5 to MD0 are changed in standby mode When this bit is set to 1 the MD5 to MD0 pin values are latched when returning from standby mode by means of a reset or interrupt Bit 6 MDCHG Description 0 Pin...

Page 230: ...en the MSTP5 bit is set to 1 the supply of the clock to the ADC is halted and all registers are initialized Bit 2 MSTP5 Description 0 ADC runs Initial value 1 Clock supply to ADC halted and all registers initialized Bit 1 Module Stop 4 MSTP4 Specifies halting of the clock supply to the SCI2 SCIF serial communication interface with FIFO an on chip peripheral module When the MSTP1 bit is set to 1 th...

Page 231: ... is canceled by an interrupt NMI IRQ IRL on chip peripheral module PINT or reset Interrupts are accepted in sleep mode even when the BL bit in the SR register is 1 If necessary save SPC and SSR to the stack before executing the SLEEP instruction Canceling with an Interrupt When an NMI IRQ IRL or on chip peripheral module interrupt occurs sleep mode is canceled and interrupt exception handling is e...

Page 232: ...rs Retaining Data Interrupt controller INTC All registers On chip clock pulse generator OSC All registers User break controller UBC All registers Bus state controller BSC All registers Timer unit TMU TSTR register Registers other than TSTR Realtime clock RTC All registers A D converter ADC All registers D A converter DAC All registers The procedure for moving to standby mode is as follows 1 Clear ...

Page 233: ...prevents the data from being destroyed due to a rise in voltage with an unstable power supply etc Interrupts are accepted in standby mode even when the BL bit in the SR register is 1 If necessary save SPC and SSR to the stack before executing the SLEEP instruction Immediately after an interrupt is detected the phase of the CKIO pin clock output may be unstable until the processor starts interrupt ...

Page 234: ...Once standby mode is entered and the clock stopped within the chip the STATUS1 pin output is low and the STATUS0 pin output is high 3 Once the STATUS1 pin goes low and the STATUS0 pin goes high the input clock is stopped or the frequency is changed 4 When the frequency is changed an NMI IRL IRQ PINT or on chip peripheral module except interval timer interrupt is input after the change When the clo...

Page 235: ...d MSTP7 0 DMAC runs 1 Supply of clock to DMAC halted MSTP6 0 DAC runs 1 Supply of clock to DAC halted MSTP5 0 ADC runs 1 Supply of clock to ADC halted and all registers initialized MSTP4 0 SCIF runs 1 Supply of clock to SCIF halted MSTP3 0 IrDA runs 1 Supply of clock to IrDA halted MSTP2 0 TMU runs 1 Supply of clock to TMU halted Registers initialized 1 MSTP1 0 RTC runs 1 Supply of clock to RTC ha...

Page 236: ... Resets Power On Reset CKIO CKIO2 4 RESETP STATUS Normal 2 Normal 2 Reset 1 PLL settling time 0 to 5 Bcyc 3 0 to 30 Bcyc 3 RESETOUT Notes 1 Reset HH STATUS1 high STATUS0 high 2 Normal LL STATUS1 low STATUS0 low 3 Bcyc Bus clock cycle 4 The CKIO2 output is available only in clock modes 0 1 and 2 Figure 8 2 Power On Reset Clock Modes 0 1 2 and 7 STATUS Output ...

Page 237: ...ESETOUT Notes 1 In a manual reset STATUS becomes HH reset and the internal reset begins after waiting for the executing bus cycle to end 2 Reset HH STATUS1 high STATUS0 high 3 Normal LL STATUS1 low STATUS0 low 4 Bcyc Bus clock cycle 5 The CKIO2 output is available only in clock modes 0 1 and 2 Figure 8 3 Manual Reset STATUS Output ...

Page 238: ...KIO2 3 STATUS Normal 2 Normal 2 WDT count Oscillation stops Standby 1 Interrupt request WDT overflow WAKEUP Notes 1 Standby LH STATUS1 low STATUS0 high 2 Normal LL STATUS1 low STATUS0 low 3 The CKIO2 output is available only in clock modes 0 1 and 2 Figure 8 4 Standby to Interrupt STATUS Output ...

Page 239: ...en standby mode is cleared with a power on reset the WDT does not count Keep RESETP low during the PLL s oscillation settling time 2 Undefined 3 Reset HH STATUS1 high STATUS0 high 4 Standby LH STATUS1 low STATUS0 high 5 Normal LL STATUS1 low STATUS0 low 6 Bcyc Bus clock cycle 7 The CKIO2 output is available only in clock modes 0 1 and 2 Figure 8 5 Standby to Power On Reset STATUS Output ...

Page 240: ...TATUS0 high 3 Standby LH STATUS1 low STATUS0 high 4 Normal LL STATUS1 low STATUS0 low 5 Bcyc Bus clock cycle 6 The CKIO2 output is available only in clock modes 0 1 and 2 Figure 8 6 Standby to Manual Reset STATUS Output 8 6 3 Timing for Canceling Sleep Mode Sleep to Interrupt CKIO CKIO2 3 STATUS Normal 2 Normal 2 Sleep 1 Interrupt request Notes 1 Sleep HL STATUS1 high STATUS0 low 2 Normal LL STATU...

Page 241: ... PLL1 s multiplication ratio is changed by a power on reset keep RESETP low during the PLL s oscillation settling time 2 Undefined 3 Reset HH STATUS1 high STATUS0 high 4 Sleep HL STATUS1 high STATUS0 low 5 Normal LL STATUS1 low STATUS0 low 6 Bcyc Bus clock cycle 7 The CKIO2 output is available only in clock modes 0 1 and 2 Figure 8 8 Sleep to Power On Reset STATUS Output ...

Page 242: ...mal 4 Sleep 3 Reset 2 RESETM 1 Notes 1 Keep RESETM low until STATUS becomes reset 2 Reset HH STATUS1 high STATUS0 high 3 Sleep HL STATUS1 high STATUS0 low 4 Normal LL STATUS1 low STATUS0 low 5 Bcyc Bus clock cycle 6 The CKIO2 output is available only in clock modes 0 1 and 2 Figure 8 9 Sleep to Manual Reset STATUS Output ...

Page 243: ...he hardware standby state Acceptance of interrupts and manual resets is disabled TCLK output is fixed low and the TMU halts 2 During WDT operation when standby mode is canceled by an interrupt The chip enters hardware standby mode after standby mode is canceled and the CPU resumes operation 3 In sleep mode The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes opera...

Page 244: ...hardware standby mode Clock oscillation starts when the CA pin is driven high after the RESETP pin is driven low Normal 3 STATUS CA CKIO CKIO2 6 Standby 2 Reset 1 RESETP Undefined Rcyc EXTAL2 32 768 kHz cycle 2 Rcyc or more 5 0 10Bcyc 4 Notes 1 Reset HH STATUS1 high STATUS0 high 2 Standby LH STATUS1 low STATUS0 high 3 Normal LL STATUS1 low STATUS0 low 4 Bcyc Bus clock cycle 5 Rcyc EXTAL2 32 768 kH...

Page 245: ...tion Notes 1 Reset HH STATUS1 high STATUS0 high 2 Standby LH STATUS1 low STATUS0 high 3 Normal LL STATUS1 low STATUS0 low 4 Bcyc Bus clock cycle 5 Rcyc EXTAL2 32 768 kHz cycle 6 The CKIO2 output is available only in clock modes 0 1 and 2 Figure 8 11 Hardware Standby Mode Timing When CA Goes Low during WDT Operation on Standby Mode Cancellation ...

Page 246: ...Rev 5 00 09 03 page 202 of 760 ...

Page 247: ...rface Frequency change function Internal and peripheral clock frequencies can be changed independently using the PLL circuit and divider circuit within the CPG Frequencies are changed by software using frequency control register FRQCR settings Power down mode control The clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function The W...

Page 248: ...interface STBCR PLL circuit 1 1 2 3 4 6 Divider 1 Internal clock Iφ Cycle Icyc Peripheral clock Pφ Cycle Pcyc Standby control Divider 2 Clock pulse generator PLL circuit 2 1 4 Crystal oscillator CPG control unit Clock frequency control circuit Standby control circuit 1 1 2 1 3 1 4 1 6 1 1 2 1 3 1 4 1 6 Legend FRQCR Frequency control register STBCR Standby control register Figure 9 1 Block Diagram ...

Page 249: ...uency can be 1 1 2 1 3 1 4 or 1 6 times the output frequency of PLL circuit 1 as long as it is not lower than the CKIO pin clock frequency The division ratio is set in the frequency control register 5 Divider 2 Divider 2 generates a clock at the operating frequency used by the peripheral clock The operating frequency can be 1 1 2 1 3 1 4 or 1 6 times the output frequency of PLL circuit 1 or the CK...

Page 250: ...rystal oscillator Also used to input an external clock Clock I O pin CKIO I O Inputs or outputs an external clock CAP1 I Connects capacitor for PLL circuit 1 operation recommended value 470 pF Capacitor connection pins for PLL CAP2 I Connects capacitor for PLL circuit 2 operation recommended value 470 pF 9 2 3 CPG Register Configuration Table 9 2 shows the CPG register configuration Table 9 2 CPG ...

Page 251: ...e 0 An external clock is input from the EXTAL pin and undergoes waveform shaping by PLL circuit 2 before being supplied inside the chip PLL circuit 1 is constantly on An input clock frequency of 25 MHz to 66 67 MHz can be used and the CKIO frequency range is 25 MHz to 66 67 MHz Mode 1 An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by PLL circuit 2 before being s...

Page 252: ...of Clock Mode and FRQCR Values Clock Mode FRQCR PLL1 PLL2 Clock Rate I B P Input Frequency Range CKIO Frequency Range 0 H 0100 ON 1 ON 1 1 1 1 25 MHz to 33 34 MHz 25 MHz to 33 34 MHz H 0101 ON 1 ON 1 1 1 1 2 25 MHz to 66 67 MHz 25 MHz to 66 67 MHz H 0102 ON 1 ON 1 1 1 1 4 25 MHz to 66 67 MHz 25 MHz to 66 67 MHz H 0111 ON 2 ON 1 2 1 1 25 MHz to 33 34 MHz 25 MHz to 33 34 MHz H 0112 ON 2 ON 1 2 1 1 2...

Page 253: ...ON 3 ON 4 4 4 2 6 25 MHz to 16 67 MHz 25 MHz to 66 67 MHz H A111 ON 6 ON 4 24 4 4 6 25 MHz to 8 34 MHz 25 MHz to 33 34 MHz 7 H 0100 ON 1 OFF 1 1 1 25 MHz to 33 34 MHz 25 MHz to 33 34 MHz H 0101 ON 1 OFF 1 1 1 2 25 MHz to 66 67 MHz 25 MHz to 66 67 MHz H 0102 ON 1 OFF 1 1 1 4 25 MHz to 66 67 MHz 25 MHz to 66 67 MHz H 0111 ON 2 OFF 2 1 1 25 MHz to 33 34 MHz 25 MHz to 33 34 MHz H 0112 ON 2 OFF 2 1 1 2...

Page 254: ... pin the frequency multiplication ratio of PLL circuit 1 and the division ratio of divider 2 The peripheral clock frequency should not be set higher than the frequency of the CKIO pin higher than 33 34 MHz 3 The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1 4 1 2 3 4 or 6 can be used as the multiplication ratio of PLL circuit 1...

Page 255: ...RQCR is initialized to H 0102 by a power on reset but retains its value in a manual reset and in standby mode FRQCR Bit 15 14 13 12 11 10 9 8 STC2 IFC2 PFC2 Initial value 0 0 0 0 0 0 0 1 R W R W R W R W R R R R R Bit 7 6 5 4 3 2 1 0 STC1 STC0 IFC1 IFC0 PFC1 PFC0 Initial value 0 0 0 0 0 0 1 0 R W R R R W R W R W R W R W R W Bits 15 5 and 4 Frequency Multiplication Ratio STC These bits specify the f...

Page 256: ...13 1 and 0 Peripheral Clock Frequency Division Ratio PFC These bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO pin Bit 13 PFC2 Bit 1 PFC1 Bit 0 PFC0 Description 0 0 0 1 0 0 1 1 2 1 0 0 1 3 0 1 0 1 4 Initial value 1 0 1 1 6 Except above value Reserved Setting prohibited Note Do not ...

Page 257: ...e STC2 to STC0 bits The division ratio can also be set in the IFC2 IFC0 bits and PFC2 PFC0 bits 4 The processor pauses internally and the WDT starts incrementing In clock modes 0 2 and 7 the internal and peripheral clocks both stop except for the peripheral clock supplied to the WDT 5 Supply of the clock that has been set begins at WDT count overflow and the processor begins operating again The WD...

Page 258: ...s register Watchdog timer counter Figure 9 2 Block Diagram of WDT 9 6 2 Register Configuration The WDT has two registers that select the clock switch the timer mode and perform other functions Table 9 5 shows the WDT registers Table 9 5 Register Configuration Name Abbreviation R W Initial Value Address Access Size Watchdog timer counter WTCNT R W H 00 H FFFFFF84 R 8 W 16 Watchdog timer control sta...

Page 259: ... readable writable register composed of bits to select the clock used for the count bits to select the timer mode and overflow flags WTCSR differs from other registers in that it is more difficult to write to See section 9 7 3 Notes on Register Access for details Its address is H FFFFFF86 The WTCSR register is initialized to H 00 only by a power on reset through the RESETP pin When a WDT overflow ...

Page 260: ... Note RESETOUT is output Bit 4 Watchdog Timer Overflow WOVF Indicates that the WTCNT has overflowed in watchdog timer mode This bit is not set in interval timer mode Bit 4 WOVF Description 0 No overflow Initial value 1 WTCNT has overflowed in watchdog timer mode Bit 3 Interval Timer Overflow IOVF Indicates that WTCNT has overflowed in interval timer mode This bit is not set in watchdog timer mode ...

Page 261: ...tatus register WTCSR are more difficult to write to than other registers The procedure for writing to these registers is given below Writing to WTCNT and WTCSR These registers must be written to using a word transfer instruction They cannot be written to with a byte or longword transfer instruction When writing to WTCNT set the upper byte to H 5A and transfer the lower byte as the write data as sh...

Page 262: ...ontinues counting from H 00 set the STBY bit in the STBCR register to 0 in the interrupt handling routine and this will stop the WDT When the STBY bit remains at 1 the SH7709S again enters standby mode when the WDT has counted up to H 80 This standby mode can be canceled by a power on reset 9 8 2 Changing the Frequency To change the frequency used by the PLL use the WDT When changing the frequency...

Page 263: ...CSR to 1 and generates the type of reset specified by the RSTS bit The counter then resumes counting When a reset is generated a low level is output at the RESETOUT pin and a high level at the STATUS0 and STATUS1 pins The output period is approximately 1 count clock cycle in the case of a power on reset and approximately 5 peripheral clock cycles in the case of a manual reset 9 8 4 Using Interval ...

Page 264: ... the passive capacitors close to the SH7709S power supply pins and use components with a frequency characteristic suitable for the chip s operating frequency as well as a suitable capacitance value Digital system VSS VCC pairs 19 21 27 29 33 35 45 47 57 59 69 71 79 81 83 85 95 97 109 111 132 134 153 154 161 163 173 175 181 183 205 208 On chip oscillator VSS VCC pairs 3 6 145 147 148 150 Note The p...

Page 265: ...age 221 of 760 CAP2 VCC PLL2 VCC PLL1 VCC C1 470 pF C2 470 pF VSS CAP1 VSS PLL2 VSS PLL1 Avoid crossing signal lines Power supply Reference values C2 C1 Figure 9 5 Points for Attention when Using PLL Oscillator Circuit ...

Page 266: ...Rev 5 00 09 03 page 222 of 760 ...

Page 267: ...ftware Register settings can be used to specify the insertion of 1 10 cycles independently for each area 1 38 cycles for areas 5 and 6 and the PCMCIA interface only The type of memory connected can be specified for each area and control signals are output for direct memory connection Wait cycles are automatically inserted to avoid data bus conflict for continuous memory accesses to different areas...

Page 268: ... counter enables the refresh function immediately after a self refresh operation using low power consumption DRAM The refresh counter can be used as an interval timer Outputs an interrupt request signal using the compare match function Outputs an interrupt request signal when the refresh counter overflows ...

Page 269: ...AIT CS0 CS6 to CS2 CE2A CE2B MCS0 to MCS7 BS RD RD WR WE3 to WE0 RASxx CASx CKE ICIORD ICIOWR IOIS16 WCR BCR MCR PCR Legend Bus interface RTCSR RTCOR BCR2 PCR MCSCRn Wait state control register Bus control register Memory control register PCMCIA control register RFCR RTCNT RTCOR RTCSR MCSCRn Refresh count register Refresh timer count register Refresh time constant register Refresh timer control st...

Page 270: ...S3L O When synchronous DRAM is used RAS3L for lower 32 Mbyte address and 64 Mbyte address Row address strobe 3U RAS3U O When synchronous DRAM is used RAS3U for upper 32 Mbyte address Column address strobe CASL O When synchronous DRAM is used CASL signal for lower 32 Mbyte address and 64 Mbyte address Column address strobe LH CASU O When synchronous DRAM is used CASU signal for upper 32 Mbyte addre...

Page 271: ...dicating I O write Read RD O Strobe signal indicating read cycle Wait WAIT I Wait state request signal Clock enable CKE O Clock enable control signal for synchronous DRAM IOIS16 IOIS16 I Signal indicating PCMCIA 16 bit I O Valid only in little endian mode Bus release request BREQ I Bus release request signal Bus release acknowledgment BACK O Bus release acknowledge signal Mask ROM chip select MCS ...

Page 272: ...r control status register RTCSR R W H 0000 H FFFFFF6E 16 Refresh timer counter RTCNT R W H 0000 H FFFFFF70 16 Refresh time constant register RTCOR R W H 0000 H FFFFFF72 16 Refresh count register RFCR R W H 0000 H FFFFFF74 16 Synchronous DRAM mode register area 2 SDMR W H FFFFD000 H FFFFDFFF 8 Synchronous DRAM mode register area 3 H FFFFE000 H FFFFEFFF MCS0 control register MCSCR0 R W H 0000 H FFFF...

Page 273: ...When PCMCIA interface is selected in area 5 or 6 in addition to CS5 CS6 CE2A CE2B are asserted for the corresponding bytes accessed Area 0 CS0 Internal I O Area 2 CS2 Area 3 CS3 Area 4 CS4 Area 5 CS5 Area 6 CS6 H 00000000 H 20000000 H 40000000 H 60000000 H 80000000 H A0000000 H C0000000 H E0000000 H 00000000 H 04000000 H 08000000 H 0C000000 H 10000000 H 14000000 H 18000000 Reserved area Physical a...

Page 274: ...000 n Shadow n 1 6 5 H 14000000 to H 15FFFFFF 32 Mbytes 8 16 32 3 5 H 16000000 to H 17FFFFFF 32 Mbytes Ordinary memory 1 PCMCIA burst ROM Ordinary memory burst ROM H 14000000 H 20000000 n to H 17FFFFFF H 20000000 n Shadow n 1 6 6 H 18000000 to H 19FFFFFF 32 Mbytes 8 16 32 3 5 H 1A000000 to H 1BFFFFFF Ordinary memory 1 PCMCIA burst ROM H 18000000 H 20000000 n to H 1BFFFFFF H 20000000 n Shadow n 1 6...

Page 275: ...word 32 bits on power on reset The correspondence between the external pins MD4 and MD3 and the memory size is shown in table below Table 10 4 Correspondence between External Pins MD4 and MD3 and Memory Size MD4 MD3 Memory Size 0 0 Reserved Do not set 0 1 8 bits 1 0 16 bits 1 1 32 bits For areas 2 6 byte word and longword can be chosen for the bus width using bus control register 2 BCR2 whenever o...

Page 276: ...face specifications in physical space areas 5 and 6 The interfaces supported are basically the IC memory card interface and I O card interface stipulated in JEIDA Specifications Ver 4 2 PCMCIA2 1 Table 10 5 PCMCIA Interface Characteristics Item Feature Access Random access Data bus 8 16 bits Memory type Mask ROM OTPROM EPROM EEPROM flash memory SRAM Memory capacity Maximum 32 Mbytes I O space capa...

Page 277: ... I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 WE PGM I Write enable WE PGM I Write enable WE 16 RDY BSY O Ready Busy IREQ O Ready Busy 17 VCC Operation power VCC Operation power 18 VPP1 Program power VPP1 Program peripheral power 19 A16 I Address A16 I Address A16 20 A15 I Address A15 I Address A15 21 A12 I Addre...

Page 278: ...e CE2 I Card enable CE2A or CE2B 43 VS1 I Voltage sense 1 VS1 I Voltage sense 1 44 RFU Reserved IORD I I O read ICIORD 45 RFU Reserved IOWR I I O write ICIOWR 46 A17 I Address A17 I Address A17 47 A18 I Address A18 I Address A18 48 A19 I Address A19 I Address A19 49 A20 I Address A20 I Address A20 50 A21 I Address A21 I Address A21 51 VCC Power supply VCC Power supply 52 VPP2 Program power VPP2 Pr...

Page 279: ...ontrol Register 1 BCR1 Bus control register 1 BCR1 is a 16 bit readable writable register that sets the functions and bus cycle state for each area It is initialized to H 0000 by a power on reset but is not initialized by a manual reset or in standby mode Do not access external memory outside area 0 until BCR1 register initialization is complete Bit 15 14 13 12 11 10 9 8 PULA PULD HIZMEM HIZCNT EN...

Page 280: ...dby mode Initial value 1 A25 A0 BS CS RD WR WE DQM RD CE2A CE2B and DRAK0 1 are high in standby mode Bit 12 High Z Control HIZCNT Specifies the state of the RAS and CAS signals in standby mode and when the bus is released Bit 12 HIZCNT Description 0 RAS and CAS signals are high impedance High Z in standby mode and when bus is released Initial value 1 RAS and CAS signals are driven in standby mode ...

Page 281: ...s 16 or 32 Bits 8 and 7 Area 5 Burst Enable A5BST1 A5BST0 Specify whether to use burst ROM and PCMCIA burst mode in physical space area 5 When burst ROM and PCMCIA burst mode are used these bits set the number of burst transfers Bit 8 A5BST1 Bit 7 A5BST0 Description 0 0 Access area 5 accessed as ordinary memory Initial value 1 Burst access of area 5 4 consecutive accesses Can be used when bus widt...

Page 282: ...ry such as ROM SRAM or flash ROM can be directly connected Synchronous DRAM can also be directly connected Bit 4 DRAMTP2 Bit 3 DRAMTP1 Bit 2 DRAMTP0 Description 0 0 0 Areas 2 and 3 are ordinary memory Initial value 1 Reserved Setting prohibited 1 0 Area 2 ordinary memory area 3 synchronous DRAM 2 1 Areas 2 and 3 are synchronous DRAM 1 2 1 0 0 Reserved Setting prohibited 1 Reserved Setting prohibit...

Page 283: ... not It is initialized to H 3FF0 by a power on reset but is not initialized by a manual reset or in standby mode Do not access external memory outside area 0 until BCR2 register initialization is complete Bit 15 14 13 12 11 10 9 8 A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 Initial value 0 0 1 1 1 1 1 1 R W R R R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 A3SZ1 A3SZ0 A2SZ1 A2SZ0 Initial value 1 1 1 1 0 0 0...

Page 284: ...not be turned off quickly even when the read signal from the external device is turned off This can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read This LSI automatically inserts the number of idle states set in WCR1 in those cases WCR1 is initialized to H 3FF3 by a power on reset It is not initiali...

Page 285: ... 1 AnIW1 Bit 2n AnIW0 Description 0 0 1 idle cycle inserted 1 1 idle cycle inserted 1 0 2 idle cycles inserted 1 3 idle cycles inserted Initial value 10 2 4 Wait State Control Register 2 WCR2 Wait state control register 2 WCR2 is a 16 bit readable writable register that specifies the number of wait state cycles inserted for each area It also specifies the data access pitch for burst memory accesse...

Page 286: ...nabled 1 0 0 4 Enabled 4 Enabled 1 6 Enabled 6 Enabled 1 0 8 Enabled 8 Enabled 1 10 Initial value Enabled 10 Enabled Bits 12 to 10 Area 5 Wait Control A5W2 A5W1 A5W0 Specify the number of wait states inserted in physical space area 5 Also specify the number of states for burst transfer Description First Cycle Burst Cycle Excluding First Cycle Bit 12 A5W2 Bit 11 A5W1 Bit 10 A5W0 Inserted Wait State...

Page 287: ...d 1 3 Enabled 1 0 0 4 Enabled 1 6 Enabled 1 0 8 Enabled 1 10 Enabled Initial value Bits 6 and 5 Area 3 Wait Control A3W1 A3W0 Specify the number of wait states inserted in physical space area 3 For Ordinary Memory Description Bit 6 A3W1 Bit 5 A3W0 Inserted Wait States W W W WA A A AI I I IT T T T Pin 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled Initial value For Synchronous DRAM Description...

Page 288: ...1 1 1 0 2 1 3 Initial value Bits 2 to 0 Area 0 Wait Control A0W2 A0W1 A0W0 Specify the number of wait states inserted in physical space area 0 Also specify the burst pitch for burst transfer Description First Cycle Burst Cycle Excluding First Cycle Bit 2 A0W2 Bit 1 A0W1 Bit 0 A0W0 Inserted Wait States W W W WA A A AI I I IT T T T Pin Number of States Per Data Transfer W W W WA A A AI I I IT T T T ...

Page 289: ...tial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 RASD AMX3 AMX2 AMX1 AMX0 RFSH RMODE Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R Bits 15 and 14 RAS Precharge Time TPC1 TPC0 When synchronous DRAM interface is selected as connected memory they set the minimum number of cycles until output of the next bank active command after precharge However th...

Page 290: ...1 TRWL1 Bit 10 TRWL0 Description 0 0 1 cycle Initial value 1 2 cycles 1 0 3 cycles 1 Reserved Setting prohibited Bits 9 and 8 C C C CA A A AS S S S Before R R R RA A A AS S S S Refresh R R R RA A A AS S S S Assert Time TRAS1 TRAS0 When synchronous DRAM interface is selected no bank active command is issued during the period TPC TRAS after an auto refresh command Bit 9 TRAS1 Bit 8 TRAS0 Description...

Page 291: ... row address begins with A10 The A10 value is output at A1 when the row address is output 2M 8 bit 4 bank products 2M 16 bit 4 bank products 1 1 The row address begins with A9 The A9 value is output at A1 when the row address is output 512k 32 bit 4 bank products 2 0 0 0 0 Begin synchronous DRAM access after setting AMX3 to 0 1 Initial value Except above value Reserved Setting prohibited Notes 1 C...

Page 292: ... Auto refresh RFSH must be 1 Initial value 1 Self refresh RFSH must be 1 Bit 0 Reserved This bit is always read as 0 The write value should always be 0 10 2 6 PCMCIA Control Register PCR The PCMCIA control register PCR is a 16 bit readable writable register that specifies the assertion and negation timing of the OE and WE signals for the PCMCIA interface connected to areas 5 and 6 The OE and WE si...

Page 293: ...ed 5 Enabled 0 1 0 1 6 Enabled 7 Enabled 0 1 1 0 8 Enabled 9 Enabled 0 1 1 1 10 Initial value Enabled 11 Enabled 1 0 0 0 12 Enabled 13 Enabled 1 0 0 1 14 Enabled 15 Enabled 1 0 1 0 18 Enabled 19 Enabled 1 0 1 1 22 Enabled 23 Enabled 1 1 0 0 26 Enabled 27 Enabled 1 1 0 1 30 Enabled 31 Enabled 1 1 1 0 34 Enabled 35 Enabled 1 1 1 1 38 Enabled 39 Enabled Bit 14 Area 5 Wait Control A5W3 Specifies the n...

Page 294: ... cycle delay 1 3 5 cycle delay 1 0 0 4 5 cycle delay 1 5 5 cycle delay 1 0 6 5 cycle delay 1 7 5 cycle delay Bits 10 5 and 4 Area 6 Address O O O OE E E E W W W WE E E E Assert Delay A6TED2 A6TED1 A6TED0 The A6TED bits specify the delay time from address output to OE WE assertion for the PCMCIA interface connected to area 6 Bit 10 A6TED2 Bit 5 A6TED1 Bit 4 A6TED0 Description 0 0 0 0 5 cycle delay ...

Page 295: ... 1 0 2 5 cycle delay 1 3 5 cycle delay 1 0 0 4 5 cycle delay 1 5 5 cycle delay 1 0 6 5 cycle delay 1 7 5 cycle delay Bits 8 1 and 0 Area 6 O O O OE E E E W W W WE E E E Negate Address Delay A6TEH2 A6TEH1 A6TEH0 Specify the address hold delay time from OE WE negation for the PCMCIA interface connected to area 6 Bit 8 A6TEH2 Bit 1 A6TEH1 Bit 0 A6TEH0 Description 0 0 0 0 5 cycle delay Initial value 1...

Page 296: ... connected to A3 of the chip the value actually written to the synchronous DRAM is the X value shifted two bits right With a 16 bit bus width the value written is the X value shifted one bit right For example with a 32 bit bus width when H 0230 is written to the SDMR register of area 2 random data is written to the address H FFFFD000 address Y H 08C0 value X or H FFFFD8C0 As a result H 0230 is wri...

Page 297: ...13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 8 Reserved These bits are always read as 0 The write value should always be 0 Bit 7 Compare Match Flag CMF Indicates that the values of RTCNT and RTCOR match Bit 7 CMF Description 0 The values of RTC...

Page 298: ...r of refresh requests indicated in the refresh count register RFCR exceeds the limit set in the LMTS bit in RTCSR Bit 2 OVF Description 0 RFCR has not exceeded the count limit value set in LMTS Initial value Clearing condition When 0 is written to OVF 1 RFCR has exceeded the count limit value set in LMTS Setting condition When the RFCR value has exceeded the count limit value set in LMTS Note Cont...

Page 299: ...S2 CKS0 in RTCSR select the input clock When RTCNT matches RTCOR the CMF bit in RTCSR is set and RTCNT is cleared RTCNT is initialized to H 00 by a power on reset but continues incrementing after a manual reset It is not initialized in standby mode but holds its contents Note The method of writing to RTCNT differs from that for general registers to ensure that RTCNT is not rewritten incorrectly Us...

Page 300: ...ion to set the upper byte as B 10100101 and the lower byte as the write data For details see section 10 2 12 Cautions on Accessing Refresh Control Related Registers Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 10 2 11 Refresh Count Register RFCR The refresh count register RFCR counts the number of ...

Page 301: ...erform reads and writes using the following methods 1 When writing to RFCR RTCSR RTCNT and RTCOR use only word transfer instructions Byte transfer instructions cannot be used When writing to RTCNT RTCSR or RTCOR place B 10100101 in the upper byte and the write data in the lower byte When writing to RFCR place B 101001 in the upper 6 bits and the write data in the remaining bits as shown in figure ...

Page 302: ... A22 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 to 7 Reserved These bits are always read as 0 The write value should always be 0 Bit 6 CS2 CS0 Select CS2 0 Selects whether an area 2 or area 0 address is to be decoded Bit 6 CS2 0 Description 0 Area 0 is selected 1 Area 2 is selected Only 0 should be used for the CS2 0 bit in MCSCR0 Either 0 or 1 may be used for MCSCR1 t...

Page 303: ...he same as those of MCSCR0 10 2 17 MCS4 Control Register MCSCR4 The MCS4 control register MCSCR4 specifies the MCS 4 pin output conditions The bit configuration and functions are the same as those of MCSCR0 10 2 18 MCS5 Control Register MCSCR5 The MCS5 control register MCSCR5 specifies the MCS 5 pin output conditions The bit configuration and functions are the same as those of MCSCR0 10 2 19 MCS6 ...

Page 304: ...ust also be matched to the device s bus width This also means that when longword data is read from a byte width device four read operations must be performed In the SH7709S data alignment and conversion of data length is performed automatically between the respective interfaces Tables 10 7 to 10 12 show the relationship between endian device data width and access unit Table 10 7 32 Bit External De...

Page 305: ... W WE E E E1 1 1 1 DQMLU W W W WE E E E0 0 0 0 DQMLL Byte access at 0 Data 7 0 Asserted Byte access at 1 Data 7 0 Asserted Byte access at 2 Data 7 0 Asserted Byte access at 3 Data 7 0 Asserted Word access at 0 Data 15 8 Data 7 0 Asserted Asserted Word access at 2 Data 15 8 Data 7 0 Asserted Asserted 1st time at 0 Data 31 24 Data 23 16 Asserted Asserted Longword access at 0 2nd time at 2 Data 15 8 ...

Page 306: ...0 0 DQMLL Byte access at 0 Data 7 0 Asserted Byte access at 1 Data 7 0 Asserted Byte access at 2 Data 7 0 Asserted Byte access at 3 Data 7 0 Asserted Word access at 0 1st time at 0 Data 15 8 Asserted 2nd time at 1 Data 7 0 Asserted Word access at 2 1st time at 2 Data 15 8 Asserted 2nd time at 3 Data 7 0 Asserted Longword access at 0 1st time at 0 Data 31 24 Asserted 2nd time at 1 Data 23 16 Assert...

Page 307: ...rted Longword access at 0 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Asserted Asserted Asserted Table 10 11 16 Bit External Device Little Endian Access and Data Alignment Data Bus Strobe Signals Operation D31 D24 D23 D16 D15 D8 D7 D0 W W W WE E E E3 3 3 3 DQMUU W W W WE E E E2 2 2 2 DQMUL W W W WE E E E1 1 1 1 DQMLU W W W WE E E E0 0 0 0 DQMLL Byte access at 0 Data 7 0 Asserted Byte access ...

Page 308: ...0 0 0 DQMLL Byte access at 0 Data 7 0 Asserted Byte access at 1 Data 7 0 Asserted Byte access at 2 Data 7 0 Asserted Byte access at 3 Data 7 0 Asserted Word access at 0 1st time at 0 Data 7 0 Asserted 2nd time at 1 Data 15 8 Asserted Word access at 2 1st time at 2 Data 7 0 Asserted 2nd time at 3 Data 15 8 Asserted Longword access at 0 1st time at 0 Data 7 0 Asserted 2nd time at 1 Data 15 8 Asserte...

Page 309: ...wn below are mapped to this area 1 Their addresses are physical addresses to which logical addresses can be mapped when the MMU is enabled DMAC PORT IrDA SCIF ADC DAC INTC except INTEVT IPRA IPRB These registers must be set not to be cached by using software Area 2 Area 2 physical address bits A28 A26 are 010 Address bits A31 A29 are ignored and the address range is H 08000000 H 20000000 n H 0BFFF...

Page 310: ...connected to this space Byte word or longword can be selected as the bus width using bits A4SZ1 and A4SZ0 in BCR2 When the area 4 space is accessed the CS4 signal is asserted The RD signal that can be used as OE and the WE0 WE3 signals for write control are also asserted The number of bus cycles is selected between 0 and 10 wait cycles using the A4W2 A4W0 bits in WCR2 Any wait can be inserted in e...

Page 311: ...an be connected to this space When the PCMCIA interface is used the IC memory card interface address range is 32 Mbytes at H 18000000 H 20000000 n H 19FFFFFF H 20000000 n and the I O card interface address range is 32 Mbytes at H 1A000000 H 20000000 n H 1BFFFFFF H 20000000 n n 0 6 and n 1 6 are the shadow spaces For ordinary memory and burst ROM byte word or longword can be selected as the bus wid...

Page 312: ...ng The correct access start address is output in the least significant bit of the address but since there is no access size specification 32 bits are always read in case of a 32 bit device and 16 bits in case of a 16 bit device When writing only the WE signal for the byte to be written is asserted For details see section 10 3 1 Endian Access Size and Data Alignment Read write for cache fill or wri...

Page 313: ...Rev 5 00 09 03 page 269 of 760 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...

Page 314: ... and 8 bit data width static RAM respectively A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 SH7709S 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 10 7 Example of 32 Bit Data Width Static RAM Connection ...

Page 315: ...ev 5 00 09 03 page 271 of 760 A16 A0 CS OE I O7 I O0 WE A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 SH7709S 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 10 8 Example of 16 Bit Data Width Static RAM Connection ...

Page 316: ...Rev 5 00 09 03 page 272 of 760 A16 A0 CSn RD D7 D0 WE0 SH7709S 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 10 9 Example of 8 Bit Data Width Static RAM Connection ...

Page 317: ...a are not zero a software wait is inserted in accordance with that specification For details see section 10 2 4 Wait State Control Register 2 WCR2 The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 10 10 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS Tw T2 Read Write Figure 10 10 Basic Interface Wait Timing Software Wait O...

Page 318: ...or the first Tw cycle When the WAITSEL bit in the WCR1 register is set to 1 the WAIT signal is sampled at the falling edge of the clock If the setup time and hold times with respect to the falling edge of the clock are not satisfied the value sampled at the next falling edge is used However the WAIT signal is ignored in the following three cases A write to external address space in dual address mo...

Page 319: ...CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 WAIT Tw Tw Tw T2 Read Write BS Wait states inserted by WAIT signal Figure 10 11 Basic Interface Wait State Timing Wait State Insertion by W W W WA A A AI I I IT T T T Signal WAITSEL 1 ...

Page 320: ... common to all areas and signals other than CKE are valid and fetched to the synchronous DRAM only when CS2 or CS3 is asserted Synchronous DRAM can therefore be connected in parallel to a number of areas CKE is negated low only when self refreshing is performed and is always asserted high at other times In the refresh cycle and mode register write cycle RAS3U and RAS3L or CASU and CASL are output ...

Page 321: ...1 D16 DQMUU DQMUL D15 D0 DQMLU DQMLL SH7709S 64M synchronous DRAM 1M 16 bit 4 bank A13 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML A13 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML Note x is U or L Figure 10 12 Example of 64 Mbit Synchronous DRAM Connection 32 Bit Bus Width ...

Page 322: ...AMX0 in MCR Table 10 13 shows the relationship between the address multiplex specification bits and the bits output at the address pins A25 A17 and A0 are not multiplexed the original values are always output at these pins When A0 the LSB of the synchronous DRAM address is connected to the SH7709S it performs longword address specification Connection should therefore be made in the following order...

Page 323: ...1 A22 A23 4 A24 4 1M 16bits 4banks 2 0 1 0 0 Column address A1 to A8 A9 A10 A11 L H 3 A13 A22 4 A23 4 Row address A9 to A16 A17 A18 A19 A20 A21 A22 4 A23 4 2M 8bits 4banks 2 0 1 0 1 Column address A1 to A8 A9 A10 A11 L H 3 A13 A23 4 A24 4 Row address A10 to A17 A18 A19 A20 A21 A22 A23 4 A24 4 512k 32bits 4banks 2 0 1 1 1 Column address A1 to A8 A9 A10 A11 L H 3 A21 4 A22 4 A15 Row address A9 to A1...

Page 324: ...umn address A1 to A8 A9 A10 L H 3 A12 A21 4 A22 4 A15 Row address A 9 to A16 A17 A18 A19 A20 A21 4 A22 4 A23 2M 8bits 4banks 2 0 1 0 1 Column address A1 to A8 A9 A10 L H 3 A12 A22 4 A23 4 A24 Row address A10 to A17 A18 A19 A20 A21 A22 4 A23 4 A24 Notes 1 Only RAL3L or CASL is output 2 When addresses are upper 32 Mbytes RAS3U or CASU is output When addresses are lower 32 Mbytes RAS3L or CASL is out...

Page 325: ...the external command clock CKIO from cycle Td1 to cycle Td4 The Tpc cycle is used to wait for completion of auto precharge based on the READA command inside the synchronous DRAM no new access command can be issued to the same bank during this cycle but access to synchronous DRAM for another area is possible In the SH7709S the number of Tpc cycles is determined by the TPC bit specification in MCR a...

Page 326: ...r A3W1 and A3W0 in WCR2 This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles CKIO A25 to A16 A13 A12 A15 A14 A11 to A0 CS2 or CS3 RAS3x CASx RD WR DQMxx D31 to D0 BS Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tpc Figure 10 14 Basic Timing for Synchronous DRAM Burst Read ...

Page 327: ... is asserted As the unit of burst transfer is 16 bytes address updating is performed for A3 and A2 only when the bus width is 16 bits address updating is performed for A3 A2 and A1 The order of access is as follows in a fill operation in the event of a cache miss the missed data is read first then 16 byte boundary data including the missed data is read in wraparound mode CKIO A25 to A16 A13 A12 A1...

Page 328: ... 1 in synchronous DRAM burst read single write mode only the required data is output Consequently no unnecessary bus cycles are generated even when a cache through area is accessed CKIO A25 to A16 A13 A12 A15 A14 A11 to A0 CS2 or CS3 RAS3x CASx RD WR DQMxx D31 to D0 BS Tr Tc1 Td1 Tpc Figure 10 16 Basic Timing for Synchronous DRAM Single Read ...

Page 329: ... cycle the write data is output at the same time as the write command In case of the write with auto precharge command precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command and therefore no command can be issued for the same bank until precharging is completed Consequently in addition to the precharge wait cycle Tpc used in a read access cycle ...

Page 330: ... 03 page 286 of 760 CKIO CSn RD WR RAS3x CASx DQMxx D31 to D0 read BS Tr Tc1 Tc2 Tc3 Tc4 Trwl Tpc Address upper bits A12 A11 A10 or A9 Address lower bits Figure 10 17 Basic Timing for Synchronous DRAM Burst Write ...

Page 331: ...se of the write with auto precharge command precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command and therefore no command can be issued for the same bank until precharging is completed Consequently in addition to the precharge wait cycle Tpc used in a read access cycle Trwl is also added as a wait interval until precharging is started followin...

Page 332: ...ev 5 00 09 03 page 288 of 760 CKIO CSn RD WR RAS3x CASx DQMxx D31 to D0 BS Address upper bits A12 or A10 Address lower bits CKE Tr Tc1 Trwl Tpc Figure 10 18 Basic Timing for Synchronous DRAM Single Write ...

Page 333: ...ommand and the row address strobe command is determined by the TPC bits in MCR Whether faster execution speed is achieved by use of bank active mode or by use of basic access is determined by the probability of accessing the same row address P1 and the average number of cycles from completion of one access to the next access Ta If Ta is greater than Tpc the delay due to the precharge wait when wri...

Page 334: ... be met even if the DQMxx signal is set after the Tc cycle When bank active mode is set if only accesses to the respective banks in the area 3 space are considered as long as accesses to the same row address continue the operation starts with the cycle in figure 10 19 or 10 22 followed by repetition of the cycle in figure 10 20 or 10 23 An access to a different area 3 space during this time has no...

Page 335: ...e 291 of 760 CKIO A25 to A16 A13 A25 to A16 A11 A12 A10 A15 A14 A11 to A0 A15 to A12 A9 to A0 CS2 or CS3 RAS3x CASx RD WR DQMxx D31 to D0 BS Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Figure 10 19 Burst Read Timing No Precharge ...

Page 336: ...92 of 760 CKIO A25 to A16 A13 A25 to A16 A11 A12 A10 A15 A14 A11 to A0 A15 to A12 A9 to A0 CS2 or CS3 RAS3x CASx RD WR DQMxx D31 to D0 BS Tnop Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Figure 10 20 Burst Read Timing Same Row Address ...

Page 337: ...f 760 CKIO A25 to A16 A13 A25 to A16 A11 A12 A10 A15 A14 A11 to A0 A15 to A12 A9 to A0 CS2 or CS3 RAS3x CASx RD WR DQMxx D31 to D0 BS Tp Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Figure 10 21 Burst Read Timing Different Row Addresses ...

Page 338: ...9 03 page 294 of 760 CKIO A25 to A16 A13 A25 to A16 A11 A12 A10 A15 A14 A11 to A0 A15 to A12 A9 to A0 CS2 or CS3 RAS3x CASx RD WR DQMxx D31 to D0 BS Tr Tc1 Tc2 Tc3 Tc4 Figure 10 22 Burst Write Timing No Precharge ...

Page 339: ... 03 page 295 of 760 CKIO A25 to A16 A13 A25 to A16 A11 A12 A10 A15 A14 A11 to A0 A15 to A12 A9 to A0 CS2 or CS3 RAS3x CASx RD WR DQMxx D31 to D0 BS Tc1 Tc2 Tc3 Tc4 Figure 10 23 Burst Write Timing Same Row Address ...

Page 340: ...ge 296 of 760 CKIO A25 to A16 A13 A25 to A16 A11 A12 A10 A15 A14 A11 to A0 A15 to A12 A9 to A0 CS2 or CS3 RAS3x CASx RD WR DQMxx D31 to D0 BS Tp Tr Tc1 Tc2 Tc3 Td4 Figure 10 24 Burst Write Timing Different Row Addresses ...

Page 341: ...CR then make the CKS2 CKS0 setting When the clock is selected by CKS2 CKS0 RTCNT starts counting up from the value at that time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh request is generated and an auto refresh is performed At the same time RTCNT is cleared to zero and the count up is restarted Figure 10 25 shows the auto refresh cycle...

Page 342: ... 298 of 760 RTCOR value RTCNT H 00000000 RTCSR CKS 2 to 0 CMF External bus CMF flag cleared by start of refresh cycle 000 000 RTCNT cleared to 0 when RTCNT RTCOR Auto refresh cycle Time Figure 10 25 Auto Refresh Operation ...

Page 343: ...Rev 5 00 09 03 page 299 of 760 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 26 Synchronous DRAM Auto Refresh Timing ...

Page 344: ... through a power on reset auto refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self refresh mode is cleared If the transition from clearing of self refresh mode to the start of auto refreshing takes time this time should be taken into consideration when setting the initial value of RTCNT Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be star...

Page 345: ...tween RTCNT and RTCOR occurs while a refresh is waiting to be executed so that a new refresh request is generated the previous refresh request is eliminated In order for refreshing to be performed normally care must be taken to ensure that no bus cycle or bus right occurs that is longer than the refresh interval When a refresh request is generated the IRQOUT pin is asserted driven low Therefore no...

Page 346: ...write CAS latency 1 to 3 wrap type sequential and burst length 1 supported by the SH7709S arbitrary data is written in a byte size access to the following addresses With 32 bit bus width Area 2 Area 3 CAS latency 1 FFFFD840 FFFFE840 CAS latency 2 FFFFD880 FFFFE880 CAS latency 3 FFFFD8C0 FFFFE8C0 With 16 bit bus width Area 2 Area 3 CAS latency 1 FFFFD420 FFFFE420 CAS latency 2 FFFFD440 FFFFE440 CAS...

Page 347: ...ally achieved automatically while various kinds of initialization are being performed after auto refresh setting but a way of carrying this out more dependably is to set a short refresh request generation interval just while these dummy cycles are being executed With simple read or write access the address counter in the synchronous DRAM used for auto refreshing is not initialized and so the cycle...

Page 348: ...nsecutive accesses can be set as 4 8 or 16 by bits A0BST1 0 A5BST1 0 or A6BST1 0 When 16 bit ROM is connected 4 or 8 can be set in the same way When 32 bit ROM is connected only 4 can be set WAIT pin sampling is performed in the first access if one or more wait states are set and is always performed in the second and subsequent accesses The second and subsequent access cycles also comprise two cyc...

Page 349: ... 03 page 305 of 760 T1 TW TW TB2 TB1 TW TB2 CKIO A25 to A4 A3 to A0 CSn RD WR RD D31 to D0 BS WAIT T2 Note For a write cycle a basic bus cycle write cycle is performed TB1 Figure 10 29 Burst ROM Wait Access Timing ...

Page 350: ... 03 page 306 of 760 T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO A25 to A4 A3 to A0 CSn RD WR RD D31 to D0 BS WAIT Note For a write cycle a basic bus cycle write cycle is performed Figure 10 30 Burst ROM Basic Access Timing ...

Page 351: ...31 shows an example of PCMCIA card connection to the SH7709S To enable active insertion of the PCMCIA cards i e insertion or removal while system power is being supplied a 3 state buffer must be connected between the SH7709S s bus interface and the PCMCIA cards As operation in big endian mode is not explicitly stipulated in the JEIDA PCMCIA specifications the PCMCIA interface for the SH7709S in bi...

Page 352: ...0 D15 to D0 CE2 OE WE PGM IORD IOWR WAIT IOIS16 CD1 CD2 CE1 PC card memory IO G G G DIR DIR G D7 to D0 D15 to D8 A25 to A0 D15 to D0 CE2 OE WE PGM WAIT CD1 CD2 CE1 PC card memory IO G G G DIR DIR G D7 to D0 D15 to D8 CE2B CE2A Output port Card detection circuit Card detection circuit Figure 10 31 Example of PCMCIA Interface ...

Page 353: ...CKIO the setup and hold times for the address A24 A0 card enable CS5 CE2A CS6 CE2B and write data D15 D0 in a write cycle become insufficient with respect to RD and WR the WE pin in the SH7709S The SH7709S provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register Also software waits by means of a WCR2 register setting and hardware waits by me...

Page 354: ...Rev 5 00 09 03 page 310 of 760 CKIO Tpcm1 Tpcm2 A25 to A0 CExx RD WR D15 to D0 read D15 to D0 write RD read WE write BS Figure 10 32 Basic Timing for PCMCIA Memory Card Interface ...

Page 355: ...0 09 03 page 311 of 760 CKIO Tpcm0 A25 to A0 RD WR CExx RD read D15 to D0 read D15 to D0 write WE write BS WAIT Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w Figure 10 33 Wait Timing for PCMCIA Memory Card Interface ...

Page 356: ...pace area 5 or bits A6BST1 and A6BST0 in BCR1 for area 6 This burst access mode is not stipulated in JEIDA version 4 2 PCMCIA2 1 but allows high speed data access using ROM provided with a burst mode etc Burst access mode timing is shown in figures 10 34 and 10 35 CKIO Tpcm1 A25 to A4 CExx A3 to A0 RD WR RD read D15 to D0 read BS Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Figure 10 34 Basic Timing ...

Page 357: ...page 313 of 760 CKIO Tpcm0 A25 to A4 CExx A3 to A0 RD WR RD read D15 to D0 read BS WAIT Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w Figure 10 35 Wait Timing for PCMCIA Memory Card Interface Burst Access ...

Page 358: ...e memory space enables the A24 pin to be used for the REG signal I O space I O space I O space Area 5 H 14000000 Area 5 H 16000000 Area 6 H 18000000 Area 6 H 1A000000 Area 5 H 14000000 Area 5 H 15000000 Area 5 H 16000000 H 17000000 Area 6 H 18000000 Area 6 H 19000000 Area 6 H 1A000000 H 1B000000 Attribute memory Common memory Attribute memory Common memory I O space Up to 16 Mbyte capacity REG A24...

Page 359: ...0 to H 1BFFFFFF is accessed When accessing a PCMCIA I O card the access should be performed using a non cacheable area in virtual space P2 or P3 space or an area specified as non cacheable by the MMU When an I O card interface access is made to a PCMCIA card in little endian mode dynamic sizing of the I O bus width is possible using the IOIS16 pin When a 16 bit bus width is set for are 5 or area 6...

Page 360: ...Rev 5 00 09 03 page 316 of 760 CKIO Tpci1 Tpci2 A25 to A0 RD WR CExx ICIORD read D15 to D0 read ICIOWR write D15 to D0 write BS Figure 10 37 Basic Timing for PCMCIA I O Card Interface ...

Page 361: ...3 page 317 of 760 CKIO A25 to A0 RD WR CExx ICIORD read ICIOWR write D15 to D0 read D15 to D0 write BS WAIT IOIS16 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w Figure 10 38 Wait Timing for PCMCIA I O Card Interface ...

Page 362: ...of 760 CKIO Tpci0 A25 to A1 CExx A0 RD WR ICIORD read D15 to D0 read ICIOWR write D15 to D0 write BS WAIT IOIS16 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w Figure 10 39 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 363: ... access to a different area and when a read access is followed by a write access from the SH7709S When the SH7709S performs consecutive write cycles the data transfer direction is fixed from the SH7709S to other memory and there is no problem With read accesses to the same area in principle data is output from the same data buffer and wait cycle insertion is not performed Bits AnIW1 and AnIW0 n 0 ...

Page 364: ...executed in multiple bus cycles that are generated when the data bus width is shorter than the access size i e in the bus cycles when longword access is executed for the 8 bit memory At the negation of BREQ BACK is negated and bus use is restarted See Appendix A 1 Pin States for the pin states when the bus is released The SH7709S sometimes needs to retrieve a bus it has released For example when m...

Page 365: ...Up With the SH7709S address pin pull up can be performed when the bus is released by setting the PULA bit in BCR1 to 1 The address pins are pulled up for a 4 clock period after BACK is asserted Figure 10 41 shows the address pin pull up timing Similarly data pin pull up can be performed by setting the PULD bit in BCR1 to 1 The data pins should be pulled up when the data bus is not in use The data ...

Page 366: ... 03 page 322 of 760 Pull up CKIO D31 to D0 RD CSn Pull up Figure 10 42 Pull Up Timing for Pins D31 to D0 Read Cycle Pull up CKIO D31 to D0 WEn CSn Pull up Figure 10 43 Pull Up Timing for Pins D31 to D0 Write Cycle ...

Page 367: ...efore if an instruction that accesses MCS 1 to MCS 7 is located several instructions after an instruction that switches port C to MCS the switch from PTC n to MCSn and from CS0 to MCS 0 may not be performed correctly To prevent this problem the following switching procedure should be used When the program runs with cache on 1 To switch port C to MCS set the corresponding bits in the PCCR register ...

Page 368: ...0FFFFFF 0 1 0 L H H 1000000 to H 17FFFFF 0 1 1 L H H 1800000 to H 1FFFFFF 1 0 0 L H H 2000000 to H 27FFFFF 1 0 1 L H H 2800000 to H 2FFFFFF 1 1 0 L H H 3000000 to H 37FFFFF 1 1 1 L H H 3800000 to H 3FFFFFF 0 0 0 0 0 0 L H H 0000000 to H 03FFFFF 32 Mbit ROM 0 0 0 1 L H H 0400000 to H 07FFFFF 0 0 1 0 L H H 0800000 to H 0BFFFFF 0 0 1 1 L H H 0C00000 to H 0FFFFFF 0 1 0 0 L H H 1000000 to H 13FFFFF 0 1...

Page 369: ... 1 H L H 1800000 to H 1FFFFFF 1 0 0 H L H 2000000 to H 27FFFFF 1 0 1 H L H 2800000 to H 2FFFFFF 1 1 0 H L H 3000000 to H 37FFFFF 1 1 1 H L H 3800000 to H 3FFFFFF 0 0 0 0 0 0 H L H 0000000 to H 03FFFFF 32 Mbit ROM 0 0 0 1 H L H 0400000 to H 07FFFFF 0 0 1 0 H L H 0800000 to H 0BFFFFF 0 0 1 1 H L H 0C00000 to H 0FFFFFF 0 1 0 0 H L H 1000000 to H 13FFFFF 0 1 0 1 H L H 1400000 to H 17FFFFF 0 1 1 0 H L ...

Page 370: ...Rev 5 00 09 03 page 326 of 760 ...

Page 371: ...mode transfer Both the transfer source and transfer destination are accessed by address Dual address mode has direct address transfer mode and indirect address transfer mode Direct address transfer mode The values specified in the DMAC registers indicates the transfer source and transfer destination Two bus cycles are required for one data transfer Indirect address transfer mode Data is transferre...

Page 372: ...by low level On chip module request Requests from on chip peripheral modules such as serial communications interface IrDA and SCIF A D converter A D and a timer CMT This request can be accepted in all the channels Auto request The transfer request is generated automatically within the DMAC Selectable bus modes Cycle steal mode or burst mode Selectable channel priority levels Fixed mode The channel...

Page 373: ...er On chip peripheral module DARn DMATCRn CHCRn DMAOR IrDA SCIF A D converter CMT DEIn External RAM External ROM External I O memory mapped External I O with acknowledge DACK0 DACK1 DRAK0 DRAK1 Legend DMAOR SARn DARn DMATCRn CHCRn DEIn n 0 to 3 DMAC operation register DMAC source address register DMAC destination address register DMAC transfer count register DMAC channel control register DMA trans...

Page 374: ... O Strobe output to an external I O upon DMA transfer request from external device to channel 0 DMA request acknowledge DRAK0 O Output showing that DREQ0 has been accepted 1 DMA transfer request DREQ1 I DMA transfer request input from external device to channel 1 DMA transfer request acceptance DACK1 O Strobe output to an external I O upon DMA transfer request from external device to channel 1 DMA...

Page 375: ...el control register 0 CHCR0 R W 1 H 00000000 H 0400002C H A400002C 4 32 8 16 32 2 1 DMA source address register 1 SAR1 R W Undefined H 04000030 H A4000030 4 32 16 32 2 DMA destination address register 1 DAR1 R W Undefined H 04000034 H A4000034 4 32 16 32 2 DMA transfer count register 1 DMATCR1 R W Undefined H 04000038 H A4000038 4 24 16 32 3 DMA channel control register 1 CHCR1 R W 1 H 00000000 H ...

Page 376: ...0 4 16 8 16 2 Notes These registers are located in area 1 of physical space Therefore when the cache is on either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached 1 Only 0 can be written to bit 1 of CHCR0 to CHCR3 and bits 1 and 2 of DMAOR to clear the flag after 1 is read 2 If 16 bit access is used on...

Page 377: ... address To transfer data in 16 bits or in 32 bits specify a 16 bit or 32 bit address boundary address When transferring data in 16 byte units a 16 byte boundary address 16n must be set for the source address value Operation is not guaranteed if other addresses are specified An undefined value will be returned in a reset The previous value is retained in standby mode Bit 31 30 29 28 27 26 25 24 In...

Page 378: ...ude a count function and during a DMA transfer these registers indicate the next destination address To transfer data in 16 bit or 32 bit units make sure to specify a destination address with a 16 byte boundary 16n address An undefined value will be returned in a reset The previous value is retained in standby mode Bit 31 30 29 28 27 26 25 24 Initial value R W R W R W R W R W R W R W R W R W Bit 2...

Page 379: ...he maximum when H 000000 is set During a DMA transfer these registers indicate the remaining number of transfers In 16 byte transfer one 16 byte transfer 128 bits is counted as one Writing to upper eight bits in DMATCR is invalid 0s are read if these bits are read The write value should always be 0 An undefined value will be returned in a reset The previous value is retained in standby mode Bit 31...

Page 380: ...d Bits 6 and 16 to 18 are only used in CHCR0 and CHCR1 they are not used in CHCR2 and CHCR3 Consequently writing to these bits is invalid in CHCR2 and CHCR3 0s are read if these bits are read These register values are initialized to 0 in a reset The previous value is retained in standby mode Bit 31 21 20 19 18 17 16 DI RO RL AM AL Initial value 0 0 0 0 0 0 0 R W R R R W 2 R W 2 R W 2 R W 2 R W 2 B...

Page 381: ... Address Reload Bit RO Selects whether the source address initial value is reloaded in channel 2 This bit is only valid in CHCR2 Writing to this bit is invalid in CHCR0 CHCR1 and CHCR3 0 is read if this bit is read The write value should always be 0 When using 16 byte transfer this bit must be cleared to 0 specifying non reloading Operation is not guaranteed if reloading is specified Bit 19 RO Des...

Page 382: ...s active high or active low This bit is only valid in CHCR0 and CHCR1 Writing to this bit is invalid in CHCR2 and CHCR3 0 is read if this bit is read The write value should always be 0 Bit 16 AL Description 0 Active low DACK output Initial value 1 Active high DACK output Bits 15 and 14 Destination Address Mode Bits 1 and 0 DM1 DM0 Select whether the DMA destination address is incremented decrement...

Page 383: ...ed 1 in 8 bit transfer 2 in 16 bit transfer 4 in 32 bit transfer illegal setting in 16 byte transfer 1 1 Setting prohibited If the transfer source is specified by indirect address specify the address holding the value of the address in which the data to be transferred is stored i e the indirect address in source address register 3 SAR3 Specification of SAR3 incrementing or decrementing in indirect...

Page 384: ...ace 0 1 0 0 Auto request 0 1 0 1 Setting prohibited 0 1 1 0 Setting prohibited 0 1 1 1 Setting prohibited 1 0 0 0 Setting prohibited 1 0 0 1 Setting prohibited 1 0 1 0 IrDA transmission 1 0 1 1 IrDA reception 1 1 0 0 SCIF transmission 1 1 0 1 SCIF reception 1 1 1 0 A D converter 1 1 1 1 CMT Notes When using 16 byte transfer the following settings must not be made 1010 IrDA transmission 1011 IrDA r...

Page 385: ...ected by low level Initial value 1 DREQ detected at falling edge Bit 5 Transmit Mode TM Specifies the bus mode when transferring data Bit 5 TM Description 0 Cycle steal mode Initial value 1 Burst mode Bits 4 and 3 Transmit Size Bits 1 and 0 TS1 TS0 Specify the size of data to be transferred Bit 4 TS1 Bit 3 TS0 Description 0 0 Byte size 8 bits Initial value 0 1 Word size 16 bits 1 0 Longword size 3...

Page 386: ... completed Initial value Clearing conditions Writing 0 to TE after reading TE 1 Power on reset manual reset 1 Data transfers specified in DMATCR completed Bit 0 DMAC Enable Bit DE Enables operation of the corresponding channel Bit 0 DE Description 0 Channel operation disabled Initial value 1 Channel operation enabled If an auto request is specified RS3 to RS0 transfer starts when this bit is set t...

Page 387: ...NMIF DME Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W Note Only 0 can be written to the AE and NMIF bits after 1 is read Bits 15 to 10 Reserved These bits are always read as 0 The write value should always be 0 Bits 9 and 8 Priority Mode Bits 1 and 0 PR1 PR0 Select the priority level between channels when there are simultaneous transfer requests for multiple channels Bit 9 PR1 Bit 8 PR0...

Page 388: ...state The CPU cannot write 1 to this bit Only 0 can be written to clear this bit after 1 is read Bit 1 NMIF Description 0 No NMI input DMA transfer is enabled Initial value Clearing conditions Writing 0 to NMIF after reading NMIF 1 Power on reset manual reset 1 NMI input DMA transfer is disabled This bit is set by occurrence of an NMI interrupt Bit 0 DMA Master Enable Bit DME Enables or disables t...

Page 389: ...HCR and DMA operation register DMAOR are set the DMAC transfers data according to the following procedure 1 Checks to see if transfer is enabled DE 1 DME 1 TE 0 AE 0 NMIF 0 2 When a transfer request comes and transfer is enabled the DMAC transfers 1 transfer unit of data according to the TS0 and TS1 settings For an auto request the transfer begins automatically when the DE bit and DME bit are set ...

Page 390: ...o Yes No Yes No Yes Yes No Yes No 3 2 Start Transfer aborted DMATCR 0 Transfer request 1 DE DME 1 and AE NMIF TE 0 Does AE 1 or NMIF 1 or DE 0 or DME 0 Transfer end Notes 1 In auto request mode transfer begins when AE NMIF and TE are both 0 and the DE and DME bits are set to 1 2 DREQ level detection in burst mode external request or cycle steal mode 3 DREQ edge detection in burst mode external req...

Page 391: ... NMIF 0 a transfer is performed upon a request at the DREQ input Choose DREQ detection by either a falling edge or low level of the signal input with the DS bit in CHCR0 and CHCR1 DS 0 for level detection DS 1 for edge detection The source of the transfer request does not have to be the data transfer source or destination Table 11 3 Selecting External Request Modes with RS Bits RS3 RS2 RS1 RS0 Add...

Page 392: ...TXI2 SCIF transmit data empty interrupt transfer request Any TDR2 Cycle steal 1 1 0 1 SCIF receiver RXI2 SCIF receive data full interrupt transfer request RDR1 Any Cycle steal 1 1 1 0 A D converter ADI A D conversion end interrupt ADDR Any Cycle steal 1 1 1 1 CMT CMI Compare match timer interrupt Any Any Burst cycle steal ADDR A D data register of A D converter Note External memory memory mapped e...

Page 393: ...es the priority order of the channels remain fixed There are three kinds of fixed modes as follows CH0 CH1 CH2 CH3 CH0 CH2 CH3 CH1 CH2 CH0 CH1 CH3 These are selected by the PR1 and PR0 bits in DMAOR Round Robin Mode Each time one word byte or longword is transferred on one channel the priority order is rotated The channel on which the transfer was just finished rotates to the bottom of the priorit...

Page 394: ...han channel 2 are also shifted If immediately after there is a request to transfer channel 1 only channel 1 becomes lowest priority and the priority of channels 3 and 0 which were higher than channel 1 is also shifted Channel 1 becomes lowest priority The priority of channel 0 which was higher than channel 1 is also shifted Channel 0 becomes lowest priority Priority order after transfer Priority o...

Page 395: ...t priority 5 At this point channel 1 has a higher priority than channel 3 so the channel 1 transfer begins channel 3 waits for transfer 6 When the channel 1 transfer ends channel 1 becomes lowest priority 7 The channel 3 transfer begins 8 When the channel 3 transfer ends channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority Transfer request Waiting channel s DMA...

Page 396: ...Memory Mapped External Device On Chip Peripheral Module External device with DACK Not available Dual single Dual single Not available External memory Dual single Dual Dual Dual Memory mapped external device Dual single Dual Dual Dual On chip peripheral module Not available Dual Dual Dual Notes 1 Dual Dual address mode 2 Single Single address mode 3 Dual address mode includes direct address mode an...

Page 397: ...en to the other external memory in a write cycle Figure 11 6 shows an example of the timing at this time Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer source module Transfer destination module SAR DAR Data buffer SAR DAR The SAR value is an address data is read from the transfer source module and the data is temporar...

Page 398: ...cified in the transfer source address register SAR3 in the DMAC Consequently in this mode the address value specified in the transfer source address register in the DMAC is read first This value is temporarily stored in the DMAC Next the read value is output as an address and the value stored in that address is stored in the DMAC again Then the value read afterwards is written to the address speci...

Page 399: ...ary buffer D M A C Memory Transfer source module Data bus Address bus Transfer destination module SAR3 DAR3 Data buffer Temporary buffer D M A C First and second bus cycles When the value in the temporary buffer is an address the data is read from the transfer source module to the data buffer Third bus cycle Fourth bus cycle When the value in SAR3 is an address the value in the data buffer is writ...

Page 400: ...dress read cycle 1st 2nd 3rd NOP cycle Data read cycle 4th Data write cycle CKIO A25 to A0 CSn D31 to D0 Internal address bus Internal data bus DMAC indirect address buffer DMAC data buffer RD WEn Notes 1 2 The internal address bus value does not change and is controlled by the port The DMAC does not fetch the value until 32 bit data is output to the internal data bus External memory space externa...

Page 401: ...ween external memory and an external device with DACK shown in figure 11 9 when the external device outputs data to the data bus that data is written to the external memory in the same bus cycle DMAC SH7709S DACK DREQ External address bus External data bus External memory External device with DACK Data flow Figure 11 9 Data Flow in Single Address Mode Two kinds of transfer are possible in single a...

Page 402: ...ernal memory space Data output from external memory space DACK signal active low to external device with DACK Read strobe signal to external memory space a External device with DACK external memory space ordinary memory b External memory space ordinary memory external device with DACK CKIO A25 to A0 D31 to D0 DACKn CSn WE BS CKIO A25 to A0 D31 to D0 DACKn CSn RD BS Figure 11 10 Example of DMA Tran...

Page 403: ...after a one transfer unit byte word longword or 16 byte unit DMAC When another transfer request occurs the bus is obtained from the other bus master and transfer is performed for one transfer unit When that transfer ends the bus is passed to the other bus master This is repeated until the transfer end conditions are satisfied In the cycle steal mode transfer areas are not affected regardless of th...

Page 404: ...el detection of the DREQ pin however when the DREQ pin is driven high the bus passes to the other bus master after the DMAC transfer request that has already been accepted ends even if the transfer end conditions have not been satisfied Burst mode cannot be used when a serial communication interface IrDA SCI or A D converter is the transfer request source Figure 11 13 shows an example of burst mod...

Page 405: ... 32 4 0 3 5 Memory mapped external device and on chip peripheral module All 2 B C 3 8 16 32 4 0 3 5 On chip peripheral module and on chip peripheral module All 2 B C 3 8 16 32 4 0 3 5 Single External device with DACK and external memory External B C 8 16 32 128 0 1 External device with DACK and memory mapped external device External B C 8 16 32 128 0 1 B Burst C Cycle steal Notes 1 External reques...

Page 406: ...l 1 will begin operating again after channel 0 completes the transfer of one transfer unit even if channel 0 is in cycle steal mode or burst mode The bus will then switch between the two in the order channel 1 channel 0 channel 1 channel 0 Even if the priority is set in fixed mode or in round robin mode the bus will not be given to the CPU since channel 1 is in burst mode This example is illustrat...

Page 407: ... is the same regardless of whether level or edge detection is used For example in figure 11 15 cycle steal mode level input DMAC transfer begins at the earliest three cycles after the first sampling is performed The second sampling is started two cycles after the first If DREQ is not detected at this time sampling is performed in each subsequent cycle Thus DREQ sampling is performed one step in ad...

Page 408: ... burst mode also the DACK output period is the same as in cycle steal mode Burst Mode Edge Detection In the case of burst mode with edge detection DREQ sampling is only performed once For example in figure 11 21 DMAC transfer begins at the earliest three cycles after the first sampling is performed After this DMAC transfer is executed continuously until the number of data transfers set in the DMAT...

Page 409: ...Rev 5 00 09 03 page 365 of 760 CKIO DRAK DREQ DACK Bus cycle DMAC R CPU DMAC W DMAC R CPU DMAC W 1st sampling 2nd sampling 3rd sampling Figure 11 15 Cycle Steal Mode Level Input CPU Access 2 Cycles ...

Page 410: ...Rev 5 00 09 03 page 366 of 760 CPU CPU CKIO DRAK DREQ DACK DMAC R DMAC W DMAC R 1st sampling 2nd sampling 3rd sampling Bus cycle Figure 11 16 Cycle Steal Mode Level Input CPU Access 3 Cycles ...

Page 411: ...ge 367 of 760 CKIO DRAK High output Bus cycle DREQ DACK RD output DMAC W CPU DMAC W DMAC R CPU 1st sampling 2nd sampling 3rd sampling Figure 11 17 Cycle Steal Mode Level input CPU Access 2 Cycles DMA RD Access 4 Cycles ...

Page 412: ...MAC R CPU 3rd sampling is performed but since DREQ is high per cycle sampling starts 2nd sampling is performed but since DREQ is high per cycle sampling starts 1st sampling 2nd sampling 3rd sampling Figure 11 18 Cycle Steal Mode Level input CPU Access 2 Cycles D D D DR R R RE E E EQ Q Q Q Input Delayed ...

Page 413: ...since there is no DREQ falling edge per cycle sampling starts 2nd sampling is performed but since there is no DREQ falling edge per cycle sampling starts 1st sampling 2nd sampling 3rd sampling Note When a DREQ falling edge is detected DREQ must be high for at least one cycle before the sampling point Figure 11 19 Cycle Steal Mode Edge input CPU Access 2 Cycles ...

Page 414: ...Rev 5 00 09 03 page 370 of 760 CKIO DRAK DREQ DACK Bus cycle DMAC R DMAC W DMAC R DMAC W DMAC R CPU 1st sampling 2nd sampling 3rd sampling Figure 11 20 Burst Mode Level Input ...

Page 415: ...Rev 5 00 09 03 page 371 of 760 CKIO DRAK DREQ DACK Bus cycle CPU DMAC R DMAC W DMAC R DMAC W DMAC R 1st sampling Figure 11 21 Burst Mode Edge Input ...

Page 416: ...ed Figure 11 22 shows this operation Figure 11 23 shows a timing chart for the source address reload function under the following conditions burst mode auto request 16 bit transfer data size SAR2 incremented DAR2 fixed reload function on and use of channel 2 only SAR2 initial value DMAC Transfer request DMAC control Reload control 4 time count CHCR2 DMATCR2 SAR2 RO bit 1 Count signal Reload signal...

Page 417: ...he reload function is on or off Consequently a multiple of four must be specified in DMATCR2 when the reload function is on Operation is not guaranteed if other values are specified The counter that counts the execution of four transfers for the address reload function is reset by clearing the DME bit in DMAOR or the DE bit in CHCR2 by setting the transfer end flag TE bit in CHCR2 by DMAC address ...

Page 418: ...er request sampling in cycle steal mode As a result the period when a stop request is not sampled is regarded as the period when a transfer request is generated and after performing the DMA transfer for this period the DMAC stops operating c Burst mode level detection external request Same as in a d Bus timing when transfer is suspended Transfer is suspended when one transfer ends Even if transfer...

Page 419: ...aster Consequently even if the AE or NMI bit is set to 1 during transfer SAR DAR DMATCR are updated The TE bit is not set To resume transfer after NMI interrupt exception handling clear the NMIF bit to 0 At this time if there are channels that should not be restarted clear the corresponding DE bit in CHCR Transfer ending when DME is cleared to 0 in DMAOR Clearing the DME bit to 0 in DMAOR forcibly...

Page 420: ...cks Pφ 4 Pφ 8 Pφ 16 Pφ 64 can be selected Generates a DMA transfer request when compare match occurs Block Diagram Figure 11 24 shows a block diagram of the CMT Internal bus Bus interface Control circuit Clock selection CMSTR CMCSR0 CMCOR0 Comparator CMCNT0 Module bus CMT Pφ 4 Pφ 8 Pφ 16 Pφ 64 CMSTR CMCSR0 CMCOR0 CMCNT0 Compare match timer start register Compare match timer control status register...

Page 421: ... be written to the CMF bit in CMCSR0 is 0 to clear the flag 2 When address translation by the MMU does not apply the address in parentheses should be used 11 4 2 Register Descriptions Compare Match Timer Start Register CMSTR The compare match timer start register CMSTR is a 16 bit register that selects whether compare match counter 0 CMCNT0 is operated or halted It is initialized to H 0000 by a re...

Page 422: ... a reset but retains its previous value in standby mode Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 CMF CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R R R R R W R W Note The only value that can be written is 0 to clear the flag Bits 15 to 8 and 5 to 2 Reserved These bits are always read as 0 The write value should always be 0 Bit 7 Compare...

Page 423: ... Counter 0 CMCNT0 Compare match counter 0 CMCNT0 is a 16 bit register used as an up counter When an internal clock is selected with the CKS1 and CKS0 bits in the CMCSR0 register and the STR bit in CMSTR is set to 1 CMCNT0 begins incrementing on that clock When the CMCNT0 value matches that of compare match constant register 0 CMCOR0 CMCNT0 is cleared to H 0000 and the CMF flag in CMCSR0 is set to ...

Page 424: ...1 R W R W R W R W R W R W R W R W R W 11 4 3 Operation Period Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in the CMCSR0 register and the STR bit in CMSTR is set to 1 CMCNT0 begins incrementing on the selected clock When the CMCNT counter value matches that of CMCOR0 the CMCNT0 counter is cleared to H 0000 and the CMF flag in the CMCSR0 register is set to 1 The CM...

Page 425: ... Compare Match Flag Setting Timing The CMF bit in the CMCSR0 register is set to 1 by the compare match signal generated when the CMCOR0 register and the CMCNT0 counter match The compare match signal is generated in the final state of the match timing at which the CMCNT0 counter matching count value is updated Consequently after the CMCOR0 register and the CMCNT0 counter match a compare match signa...

Page 426: ...N 0 Figure 11 27 CMF Setting Timing Compare Match Flag Clearing Timing The CMF bit in the CMCSR0 register is cleared by writing 0 to it after reading 1 Figure 11 28 shows the timing when the CMF bit is cleared by the CPU CK CMF CMCSR0 write cycle T1 T2 Figure 11 28 Timing of CMF Clearing by the CPU ...

Page 427: ... IrDA be set to 1 RTRG1 RTRG0 0 in SCFCR Table 11 8 Transfer Conditions and Register Settings for Transfer between On Chip SCI and External Memory Transfer Conditions Register Setting Transfer source RDR1 of on chip IrDA SAR3 H 0400014A Transfer destination External memory DAR3 H 00400000 Number of transfers 64 DMATCR3 H 00000040 Transfer source address Fixed CHCR3 H 00004B05 Transfer destination ...

Page 428: ...1 DMAOR H 0101 When the address reload function is on the value set in SAR returns to the initially set value every four transfers In this example when a transfer request is generated from the A D converter byte data is read from the register at address H 04000080 in the A D converter and is written to external memory address H 00400000 Since longword data has been transferred the values in SAR an...

Page 429: ...R has been set to 1 2 The transfer request source flag is cleared regardless of whether the address reload function is on or off if transfers are executed until the value in DMATCR reaches 0 3 Specify burst mode when using the address reload function This function may not be correctly executed in cycle steal mode 4 Set a multiple of four in DMATCR when using the address reload function This functi...

Page 430: ... used as an address again and the value stored in that address is read and stored in the address set in DAR In the example shown in table 11 11 when an SCIF transfer request is generated the DMAC reads the value in address H 00400000 set in SAR3 Since the value H 00450000 is stored in that address the DMAC reads the value H 00450000 Next the DMAC uses that read value as an address again and reads ...

Page 431: ...mally write 0 to DMATCR Otherwise normal DMA transfer may not be performed 8 When using the address reload function specify burst mode as the transfer mode In cycle steal mode normal DMA transfer may not be performed 9 When using the address reload function set a multiple of four in DMATCR Normal operation is not guaranteed if other values are specified 10 When detecting an external request at the...

Page 432: ...Rev 5 00 09 03 page 388 of 760 ...

Page 433: ...n Circuits for more information on the clock pulse generator All channels can operate when the SH7709S is in standby mode When the RTC output clock is being used as the counter input clock the SH7709S is still able to count in standby mode Synchronized read TCNT is a sequentially changing 32 bit register Since the peripheral module used has an internal bus width of 16 bits a time lag can occur bet...

Page 434: ...us interface Ch 0 Interrupt controller Interrupt controller Interrupt controller Counter controller Counter controller TUNI1 TUNI2 TICPI2 TCR2 TCPR2 TCNT2 TCOR2 TMU Ch 1 Ch 2 Clock controller TOCR TSTR TCR Legend Timer output control register Timer start register TCNT TCOR TCPR2 32 bit timer counter 32 bit timer constant register 32 bit input capture register Timer control register Figure 12 1 Blo...

Page 435: ...R R W H 00 H FFFFFE90 8 Timer start register TSTR R W H 00 H FFFFFE92 8 0 Timer constant register 0 TCOR0 R W H FFFFFFFF H FFFFFE94 32 Timer counter 0 TCNT0 R W H FFFFFFFF H FFFFFE98 32 Timer control register 0 TCR0 R W H 0000 H FFFFFE9C 16 1 Timer constant register 1 TCOR1 R W H FFFFFFFF H FFFFFEA0 32 Timer counter 1 TCNT1 R W H FFFFFFFF H FFFFFEA4 32 Timer control register 1 TCR1 R W H 0000 H FF...

Page 436: ... multiplexed as the PTH7 pin when the pin is used as TCLK bits PH7MD1 and PH7MD0 in the PHCR register should be set to 00 the other function setting Bit 0 TCOE Description 0 Timer clock pin TCLK used as external clock input or input capture control input pin for the on chip timer Initial value 1 Timer clock pin TCLK used as output pin for on chip RTC output clock 12 2 2 Timer Start Register TSTR T...

Page 437: ...alted Initial value 1 TCNT0 counts 12 2 3 Timer Control Registers TCR The timer control registers TCR control the timer counters TCNT and interrupts The TMU has three TCR registers one for each channel The TCR registers are 16 bit readable writable registers that control the issuance of interrupts when the flag indicating timer counter TCNT underflow has been set to 1 and also carry out counter cl...

Page 438: ... TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 10 9 except TCR2 7 and 6 except TCR2 Reserved These bits are always read as 0 The write value should always be 0 Bit 9 Input Capture Interrupt Flag ICPF A function of channel 2 only the flag is set when input capture is requested via the TCLK pin Bit 9 ICPF Description 0 No input capture request has bee...

Page 439: ... to set the TCLK pin to input mode with the TCOE bit in the TOCR register Additionally use the CKEG bit to designate use of either the rising or falling edge of the TCLK pin to set the value in TCNT2 in the input capture register TCPR2 Bit 7 ICPE1 Bit 6 ICPE0 Description 0 0 Input capture function is not used Initial value 1 Reserved Setting prohibited 1 0 Input capture function is used Interrupt ...

Page 440: ...ge 1 X Count capture register set on both rising and falling edge Note X means 0 1 or Don t care Bits 2 to 0 Timer Prescaler 2 to 0 TPSC2 to TPSC0 Select the TCNT count clock Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock count on Pφ 4 Initial value 1 Internal clock count on Pφ 16 1 0 Internal clock count on Pφ 64 1 Internal clock count on Pφ 256 1 0 0 Internal clock count on...

Page 441: ...1 1 1 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W 12 2 5 Timer Counters TCNT The timer counters are 32 bit readable writable registers The TMU has three timer counters one for each channel TCNT counts down upon input of a clock Th...

Page 442: ...pper and lower halves are not read separately The entire 32 bit data in TCNT can thus be read at once TCNT is initialized to H FFFFFFFF by a power on reset or manual reset but is not initialized and retains its contents in standby mode Bit 31 30 29 28 27 26 25 24 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Initial value 1 1 1 1 1 1 1 1 R W R W R W ...

Page 443: ... CKEG0 in TCR2 When a TCPR2 setting indication due to the TCLK pin occurs the value of TCNT2 is copied into TCPR2 TCNT2 is not initialized by a power on reset or manual reset but is not initialized and retains its contents or in standby mode Bit 31 30 29 28 27 26 25 24 Initial value R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 Initial value R W R R R R R R R R Bit 15 14 13 12 11 10 9 8 Initial ...

Page 444: ...s time the value is copied from TCOR to TCNT and the down count operation is continued The count operation is set as follows figure 12 2 1 Select the counter clock with the TPSC2 TPSC0 bits in the timer control register TCR If the external clock is selected set the TCLK pin to input mode with the TOCE bit in TOCR and select its edge with the CKEG1 and CKEG0 bits in TCR 2 Use the UNIE bit in TCR to...

Page 445: ...nitialize timer counter Start counting 1 2 4 5 6 Set interrupt generation When using input capture function 3 Note When an interrupt has been generated clear the flag in the interrupt handler that caused it If interrupts are enabled without clearing the flag another interrupt will be generated Figure 12 2 Setting the Count Operation ...

Page 446: ...Time Figure 12 3 Auto Reload Count Operation TCNT Count Timing Internal Clock Operation Set the TPSC2 TPSC0 bits in TCR to select whether peripheral module clock Pφ or one of the four internal clocks created by dividing it is used Pφ 4 Pφ 16 Pφ 64 Pφ 256 Figure 12 4 shows the timing Pφ Internal clock TCNT input clock TCNT N 1 N N 1 Figure 12 4 Count Timing when Operating on Internal Clock ...

Page 447: ...in TCR to select the on chip RTC clock as the timer clock Figure 12 6 shows the timing RTC output clock TCNT TCNT input clock N 1 N N 1 Figure 12 6 Count Timing when Operating on On Chip RTC Clock 12 3 2 Input Capture Function Channel 2 has an input capture function figure 12 7 When using the input capture function set the TCLK pin to input mode with the TCOE bit in the timer output control regist...

Page 448: ...nput Capture Function Using TCLK Rising Edge 12 4 Interrupts There are two sources of TMU interrupts underflow interrupts TUNI and interrupts when using the input capture function TICPI2 12 4 1 Status Flag Setting Timing UNF is set to 1 when the TCNT underflows Figure 12 8 shows the timing Pφ TCNT Underflow signal UNF TUNI TCOR value H 00000000 Figure 12 8 UNF Setting Timing ...

Page 449: ...rupt enable bit are both set to 1 an interrupt is requested Codes are set in the interrupt event registers INTEVT INTEVT2 for these interrupts and interrupt handling occurs according to the codes The relative priorities of channels can be changed using the interrupt controller see section 4 Exception Handling and section 6 Interrupt Controller INTC Table 12 3 lists TMU interrupt sources Table 12 3...

Page 450: ...always clear the appropriate start bits for the channel STR2 STR0 in the timer start register TSTR to halt timer counting 12 5 2 Reading Registers Synchronization processing is performed for timer counting during register reads When timer counting and register read processing are performed simultaneously the register value before TCNT counting down with synchronization processing is read ...

Page 451: ...year 1 Hz to 64 Hz timer binary display Start stop function 30 second adjust function Alarm interrupt Frame comparison of seconds minutes hours date day of the week and month can be used as conditions for the alarm interrupt Cyclic interrupts The interrupt cycle may be 1 256 second 1 64 second 1 16 second 1 4 second 1 2 second 1 second or 2 seconds Carry interrupt A carry interrupt indicates when ...

Page 452: ...counter RMONCNT Month counter RYRCNT Year counter RSECAR Second alarm register RMINAR Minute alarm register RHRAR Hour alarm register RWKAR Day of week alarm register RDAYAR Day alarm register RMONAR Month alarm register RCR1 RTC control register 1 RCR2 RTC control register 2 R64CNT Reset RSECCNT RMINCNT RHRCNT RWKCNT 16 384 kHz RDAYCNT RMONCNT RYRCNT Comparator RSECAR RMINAR RHRAR RWKAR RDAYAR RC...

Page 453: ...ut clock output TCLK I O External clock input pin input capture control input pin realtime clock RTC output pin shared by TMU Dedicated power supply pin for RTC Vcc RTC Dedicated power supply pin for RTC 1 Dedicated GND pin for RTC Vss RTC Dedicated GND pin for RTC 1 Notes 1 Except in hardware standby mode power must be supplied to all power supply pins including these even when only the RTC is us...

Page 454: ...C8 8 Date counter RDAYCNT R W Undefined H FFFFFECA 8 Month counter RMONCNT R W Undefined H FFFFFECC 8 Year counter RYRCNT R W Undefined H FFFFFECE 8 Second alarm register RSECAR R W Undefined H FFFFFED0 8 Minute alarm register RMINAR R W Undefined H FFFFFED2 8 Hour alarm register RHRAR R W Undefined H FFFFFED4 8 Day of week alarm register RWKAR R W Undefined H FFFFFED6 8 Date alarm register RDAYAR...

Page 455: ...1 0 1Hz 2Hz 4Hz 8Hz 16Hz 32Hz 64Hz Initial value 0 R W R R R R R R R R 13 2 2 Second Counter RSECCNT The second counter RSECCNT is an 8 bit readable writable register used for setting counting in the BCD coded second section of the RTC The count operation is performed by a carry for each second of the 64 Hz counter The range that can be set is 00 59 decimal Errant operation will result if any othe...

Page 456: ...ndby mode Bit 7 6 5 4 3 2 1 0 10 minutes 1 minute Initial value 0 R W R R W R W R W R W R W R W R W 13 2 4 Hour Counter RHRCNT The hour counter RHRCNT is an 8 bit readable writable register used for setting counting in the BCD coded hour section of the RTC The count operation is performed by a carry for each 1 hour of the minute counter The range that can be set is 00 23 decimal Errant operation w...

Page 457: ...an be set is 0 6 decimal Errant operation will result if any other value is set Carry out write processing after halting the count operation with the START bit in RCR2 RWKCNT is not initialized by a power on reset or manual reset or in standby mode Bit 7 6 5 4 3 2 1 0 Day of week Initial value 0 0 0 0 0 R W R R R R R R W R W R W Days of the week are coded as shown in table 13 3 Table 13 3 Day of W...

Page 458: ...be set changes with each month and in leap years Please confirm the correct setting Bit 7 6 5 4 3 2 1 0 10 days 1 day Initial value 0 0 R W R R R W R W R W R W R W R W 13 2 7 Month Counter RMONCNT The month counter RMONCNT is an 8 bit readable writable register used for setting counting in the BCD coded month section of the RTC The count operation is performed by a carry for each month of the date...

Page 459: ... Bit 7 6 5 4 3 2 1 0 10 years 1 year Initial value R W R W R W R W R W R W R W R W R W 13 2 9 Second Alarm Register RSECAR The second alarm register RSECAR is an 8 bit readable writable register and an alarm register corresponding to the BCD coded second section counter RSECCNT of the RTC When the ENB bit is set to 1 a comparison with the RSECCNT value is performed From among the RSECAR RMINAR RHR...

Page 460: ...ual reset or in standby mode Bit 7 6 5 4 3 2 1 0 ENB 10 minutes 1 minute Initial value 0 R W R W R W R W R W R W R W R W R W 13 2 11 Hour Alarm Register RHRAR The hour alarm register RHRAR is an 8 bit readable writable register and an alarm register corresponding to the BCD coded hour section counter RHRCNT of the RTC When the ENB bit is set to 1 a comparison with the RHRCNT value is performed Fro...

Page 461: ...ormed only on those with ENB bits set to 1 and if each of those coincide an RTC alarm interrupt is generated The range that can be set is 0 6 decimal ENB bit Errant operation will result if any other value is set The ENB bit in RWKAR is initialized by a power on reset The remaining RWKAR fields are not initialized and retain their contents by a manual reset or in standby mode Bit 7 6 5 4 3 2 1 0 E...

Page 462: ...not initialized and retain their contents by a manual reset or in standby mode Bit 7 6 5 4 3 2 1 0 ENB 10 days 1 day Initial value 0 0 R W R W R R W R W R W R W R W R W 13 2 14 Month Alarm Register RMONAR The month alarm register RMONAR is an 8 bit readable writable register and an alarm register corresponding to the BCD coded month section counter RMONCNT of the RTC When the ENB bit is set to 1 a...

Page 463: ...R W R W R R R W R W R R R W Bit 7 Carry Flag CF Status flag that indicates that a carry has occurred Setting CF to 1 indicates reading of a counter register value has occurred when 1 the second counter is carried or 2 the 64 Hz counter is carried A count register value read at this time cannot be guaranteed another read is required Bit 7 CF Description 0 No count up of R64CNT or RSECCNT Clearing c...

Page 464: ...h ENB set Note Contents do not change when 1 is written to AF 13 2 16 RTC Control Register 2 RCR2 The RTC control register 2 RCR2 is an 8 bit readable writable register for periodic interrupt control 30 second adjustment ADJ divider circuit RESET and RTC count start stop control It is initialized to H 09 by a power on reset It is initialized except for RTCEN and START by a manual reset It is not i...

Page 465: ...llator for RTC is halted 1 Crystal oscillator for RTC runs Initial value Bit 2 30 Second Adjustment ADJ When 1 is written to the ADJ bit times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute The divider circuit RTC prescaler and R64CNT will be simultaneously reset This bit is always read as 0 The maximum duration between when the ADJ bit is set to 1 and when ...

Page 466: ...ter Power On All the registers should be set after the power is turned on 13 3 2 Setting the Time Figure 13 2 shows how to set the time when the clock is stopped This works when the entire calendar or clock is to be set Programming can be easily performed Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Write 1 to START in the RCR2 register Set seconds minutes hour day day ...

Page 467: ...should normally be used Write 0 to CF in RCR1 Note Set AF to 1 so that alarm flag is not cleared Clear CIE in RCR1 to 0 Read RCR1 and check CF Write 0 to CIE in RCR1 Carry flag 1 No Yes Clear the carry flag Disable the carry interrupt Read counter register Write 1 to CIE in RCR1 and write 0 to CF in RCR1 Note Set AF in RCR1 to 1 so that alarm flag is not cleared Interrupt generated No Yes Enable t...

Page 468: ...match 1 is set in the AF bit bit 0 in RCR1 Alarm detection can be checked by reading this bit but normally it is done by interrupt If 1 is placed in the AIE bit bit 3 in RCR1 an interrupt is generated when an alarm occurs Disable interrupts for preventing error interrupts clear the AIE bit in RCR1 to 0 Then write 1 to the AIE bit in RCR1 Clock running Set alarm time Set whether to use alarm interr...

Page 469: ...ue Rf Typ value 10 MΩ RD Typ value 400 kΩ 3 Cin and Cout values include floating capacitance due to the wiring Take care when using a ground plane 4 The crystal oscillation settling time depends on the mounted circuit constants floating capacitance etc and should be decided after consultation with the crystal resonator manufacturer 5 Place the crystal resonator and load capacitors Cin and Cout as ...

Page 470: ...odic interrupt enable flag PES in RTC control register 2 RCR2 When the time set by the periodic interrupt enable flag PES has elapsed the periodic interrupt flag PEF is set to 1 The periodic interrupt flag PEF is cleared to 0 upon periodic interrupt generation when the periodic interrupt enable flag PES is set Periodic interrupt generation can be confirmed by reading this bit but normally the inte...

Page 471: ...other communications chip that employs a standard asynchronous serial system It can also communicate with two or more other processors using the multiprocessor communication function There are 12 selectable serial data communication formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd or none Multiprocessor bit 1 or 0 Receive error detection Parity overrun and framing errors...

Page 472: ... a block diagram of the SCI RxD TxD SCK SCI SCBRR SCSSR SCSCR SCTSR SCRDR SCRSR SCSMR SCPCR SCPDR Parity generation Parity check Clock External clock Module data bus Internal data bus Pφ Pφ 4 Pφ 16 Pφ 64 TXI TEI RXI ERI Bus interface Baud rate generator Transmit receive control SCRSR SCRDR SCTSR SCTDR SCSMR Legend Receive shift register Receive data register Transmit shift register Transmit data r...

Page 473: ...nternal data bus Output enable Clock input enable SCI Serial clock output Serial clock input R SCP1MD0 PCRW Reset C Q Q D R SCP1MD1 PCRW Reset C Q D R SCP1DT1 PDRW Reset SCPT 1 SCK0 C D PDRW SCPDR write PDRR PCRW SCPDR read SCPCR write PDRR Note Legend When reading the SCK0 pin clear the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0 and set the SCP1MD1 bit in SCPCR to 1 see section 14 ...

Page 474: ...760 Internal data bus Output enable SCI Serial transmission output R SCP0MD0 PCRW Reset C Q Q D R SCP0MD1 PCRW Reset C Q D R SCP0DT1 PDRW Reset SCPT 0 TxD0 C D PCRW PDRW SCPCR write SCPDR write Legend Figure 14 3 SCPT 0 TxD0 Pin ...

Page 475: ...rized in table 14 1 Table 14 1 SCI Pins Pin Name Abbreviation I O Function Serial clock pin SCK0 I O Clock I O Receive data pin RxD0 Input Receive data input Transmit data pin TxD0 Output Transmit data output Note These pins are made to function as serial pins by performing SCI operation settings with the TE RE CKEI and CKE0 bits in SCSCR and the C A bit in SCSMR Break state transmission and detec...

Page 476: ... 00 H 04000136 H A4000136 2 8 SC port control register SCPCR R W H A888 H 04000116 H A4000116 2 16 Notes These registers are located in area 1 of physical space Therefore when the cache is on either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached 1 The only value that can be written is 0 to clear the ...

Page 477: ...0 by a reset and in standby or module standby mode Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R 14 2 3 Transmit Shift Register SCTSR The transmit shift register SCTSR transmits serial data The SCI loads transmit data from the transmit data register SCTDR into SCTSR then transmits the data serially from the TxD pin LSB bit 0 first After transmitting one byte data the SCI au...

Page 478: ...ndby or module standby mode Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W 14 2 5 Serial Mode Register SCSMR The serial mode register SCSMR is an 8 bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator The CPU can always read and write to SCSMR SCSMR is initialized to H 00 by a reset and in st...

Page 479: ...ata parity is checked according to the even odd O E mode setting Bit 4 Parity Mode O E E E E Selects even or odd parity when parity bits are added and checked The O E setting is used only in asynchronous mode and only when the parity enable bit PE is set to 1 to enable parity addition and checking The O E setting is ignored in synchronous mode or in asynchronous mode when parity addition and check...

Page 480: ...r Bit 2 Multiprocessor Mode MP Selects multiprocessor format When multiprocessor format is selected settings of the parity enable PE and parity mode O E bits are ignored The MP bit setting is used only in asynchronous mode it is ignored in synchronous mode For the multiprocessor communication function see section 14 3 3 Multiprocessor Communication Bit 2 MP Description 0 Multiprocessor function di...

Page 481: ...Description 0 Transmit data empty interrupt request TXI is disabled Initial value 1 Transmit data empty interrupt request TXI is enabled Note The TXI interrupt request can be cleared by reading TDRE after it has been set to 1 then clearing TDRE to 0 or by clearing TIE to 0 Bit 6 Receive Interrupt Enable RIE Enables or disables the receive data full interrupt RXI requested when the receive data reg...

Page 482: ...ble MPIE Enables or disables multiprocessor interrupts The MPIE setting is used only in asynchronous mode and only if the multiprocessor mode bit MP in the serial mode register SCSMR is set to 1 during reception The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0 Bit 3 MPIE Description 0 Multiprocessor interrupts are disabled normal receive operation Initial value Cl...

Page 483: ... is internally clocked CKE1 0 The CKE0 setting is ignored in synchronous mode or when an external clock source is selected CKE1 1 Before selecting the SCI operating mode in the serial mode register SCSMR set CKE1 and CKE0 For further details on selection of the SCI clock source see table 14 10 in section 14 3 Operation Bit 1 CKE1 Bit 0 CKE0 Description 0 0 Asynchronous mode Internal clock SCK pin ...

Page 484: ...2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 R W R W R W R W R W R W R R R W Note The only value that can be written is 0 to clear the flag Bit 7 Transmit Data Register Empty TDRE Indicates that the SCI has loaded transmit data from SCTDR into SCTSR and new serial transmit data can be written in SCTDR Bit 7 TDRE Description 0 SCTDR contains valid transmit data Clearing ...

Page 485: ...ption of the next data ends an overrun error ORER occurs and the receive data is lost Bit 5 Overrun Error ORER Indicates that data reception aborted due to an overrun error Bit 5 ORER Description 0 Receiving is in progress or has ended normally 1 Initial value Clearing conditions 1 ORER is cleared to 0 when the chip is reset or enters standby mode 2 When software reads ORER after it has been set t...

Page 486: ...DRF Serial receiving cannot continue while FER is set to 1 In synchronous mode serial transmitting is also disabled Bit 3 Parity Error PER Indicates that data reception with parity aborted due to a parity error in asynchronous mode Bit 3 PER Description 0 Receiving is in progress or has ended normally 1 Initial value Clearing conditions 1 PER is cleared to 0 when the chip is reset or enters standb...

Page 487: ...ocessor Bit MPB Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode MPB is a read only bit and cannot be written to Bit 1 MPB Description 0 Multiprocessor bit value in receive data is 0 Initial value 1 Multiprocessor bit value in receive data is 1 Note If RE is cleared to 0 when a multiprocessor format is selected M...

Page 488: ...CP4 MD1 SCP4 MD0 SCP3 MD1 SCP3 MD0 SCP2 MD1 SCP2 MD0 SCP1 MD1 SCP1 MD0 SCP0 MD1 SCP0 MD0 Initial value 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W SCPDR Bit 7 6 5 4 3 2 1 0 SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W SCI pin I O and data control are performed by bits ...

Page 489: ... SCP0MD1 Bit 0 SCP0MD0 Description 0 0 SCP0DT bit value is not output to TxD pin Initial value 0 1 SCP0DT bit value is output to TxD pin SCPDR Bit 0 Serial Port Break Data SCP0DT Specifies the serial port RxD pin input data and TxD pin output data The TxD pin output condition is specified by the SCP0MD1 and SCP0MD0 bits When the TxD pin is set to output mode the value of the SCP0DT bit is output t...

Page 490: ...nt values can be set in two channels Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W The SCBRR setting is calculated as follows Asynchronous mode N Pφ 64 22n 1 B 106 1 Synchronous mode N Pφ 8 22n 1 B 106 1 B Bit rate bits s N SCBRR setting for baud rate generator 0 N 255 Pφ Operating frequency for peripheral modules MHz n Baud rate generator clock source n 0 1...

Page 491: ... 16 0 54 0 70 0 63 0 00 2400 0 25 0 16 0 26 1 14 0 31 0 00 4800 0 12 0 16 0 13 2 48 0 15 0 00 9600 0 6 6 99 0 6 2 48 0 7 0 00 19200 0 2 8 51 0 2 13 78 0 3 0 00 31250 0 1 0 00 0 1 4 86 0 1 22 88 38400 0 1 18 62 0 1 14 67 0 1 0 00 Pφ φ φ φ MHz 3 3 6864 4 Bit Rate bits s n N Error n N Error n N Error 110 1 212 0 03 2 64 0 70 2 70 0 03 150 1 155 0 16 1 191 0 00 1 207 0 16 300 1 77 0 16 1 95 0 00 1 103...

Page 492: ...73 0 19 2 34 19200 0 7 0 00 0 7 1 73 0 9 2 34 31250 0 4 1 70 0 4 0 00 0 5 0 00 38400 0 3 0 00 0 3 1 73 0 4 2 34 Pφ φ φ φ MHz 6 144 7 3728 8 Bit Rate bits s n N Error n N Error n N Error 110 2 108 0 08 2 130 0 07 2 141 0 03 150 2 79 0 00 2 95 0 00 2 103 0 16 300 1 159 0 00 1 191 0 00 1 207 0 16 600 1 79 0 00 1 95 0 00 1 103 0 16 1200 0 159 0 00 0 191 0 00 0 207 0 16 2400 0 79 0 00 0 95 0 00 0 103 0...

Page 493: ...25 0 16 0 31 0 00 0 32 1 36 31250 0 14 1 70 0 15 0 00 0 19 1 70 0 19 0 00 38400 0 11 0 00 0 12 0 16 0 15 0 00 0 15 1 73 Pφ φ φ φ MHz 24 24 576 28 7 30 Bit Rate bits s n N Error n N Error n N Error n N Error 110 3 106 0 44 3 108 0 08 3 126 0 31 3 132 0 13 150 3 77 0 16 3 79 0 00 3 92 0 46 3 97 0 35 300 2 155 0 16 2 159 0 00 2 186 0 08 2 194 0 16 600 2 77 0 16 2 79 0 00 2 92 0 46 2 97 0 35 1200 1 15...

Page 494: ... 3 111 3 116 2 5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 0 29 500k 0 1 0 3 0 7 0 14 1M 0 0 0 1 0 3 2M 0 0 0 1 Notes Settings with an error of 1 or less are recommended Blank No setting possible Setting possible but error occurs Continuous tr...

Page 495: ...aximum Bit Rates for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings Pφ φ φ φ MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 8 250000 0 0 9 8304 307200 0 0 12 375000 0 0 14 7456 460800 0 0 16 500000 0 0 19 6608 614400 0 0 20 625000 0 0 24 750000 0 0 24 576 768000 0 0 28 7 896875 0 ...

Page 496: ... 62500 4 9152 1 2288 76800 8 2 0000 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 19 6608 4 9152 307200 20 5 0000 312500 24 6 0000 375000 24 576 6 1440 384000 28 7 7 1750 448436 30 7 5000 468750 Table 14 8 Maximum Bit Rates with External Clock Input Synchronous Mode Pφ φ φ φ MHz External Input Clock MHz Maximum Bit Rate bits s 8 1 3333 1333333 3 16 2 6667 2666...

Page 497: ...t and character length In receiving it is possible to detect framing errors FER parity errors PER overrun errors ORER and breaks An internal or external clock can be selected as the SCI clock source When an internal clock is selected the SCI operates using the on chip baud rate generator and can output a serial clock signal with a frequency matching the bit rate When an external clock is selected ...

Page 498: ...1 bit 1 2 bits 1 0 7 bit 1 bit 1 Asynchronous multiprocessor format 2 bits 1 Synchronous 8 bit Not set None Note Asterisks indicate don t care bits Table 14 10 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR SCSCR Settings SCI Transmit Receive Clock Bit 7 C A A A A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Internal SCI does not use the SCK pin 1 Outputs a clock w...

Page 499: ...lly held in the mark high state The SCI monitors the line and starts serial communication when the line goes to the space low state indicating a start bit One serial character consists of a start bit low data LSB first starting from the lowerest bit parity bit high or low and stop bit high in that order When receiving in asynchronous mode the SCI synchronizes at the falling edge of the start bit T...

Page 500: ... START 7 bit data STOP STOP 1 1 0 0 START 7 bit data P STOP 1 1 0 1 START 7 bit data P STOP STOP 0 1 0 START 8 bit data MPB STOP 0 1 1 START 8 bit data MPB STOP STOP 1 1 0 START 7 bit data MPB STOP 1 1 1 START 7 bit data MPB STOP STOP Notes Don t care bits START Start bit STOP Stop bit P Parity bit MPB Multiprocessor bit Clock An internal clock generated by the on chip baud rate generator or an ex...

Page 501: ...lags or receive data register SCRDR which retain their previous contents When an external clock is used the clock should not be stopped during initialization or subsequent operation SCI operation becomes unreliable if the clock is stopped Figure 14 7 shows a sample flowchart for initializing the SCI The procedure for initializing the SCI is 1 Select the clock source in the serial control register ...

Page 502: ...hart for transmitting serial data The procedure for transmitting serial data is 1 SCI status check and transmit data write Read the serial status register SCSSR check that the TDRE bit is 1 then write transmit data in the transmit data register SCTDR and clear TDRE to 0 2 To continue transmitting serial data Read the TDRE bit to check whether it is safe to write if it reads 1 if so write data in S...

Page 503: ... TEND 1 Read TEND bit in SCSSR Break output Yes Clear TE bit in SCSCR to 0 End of transmission Yes Read TDRE bit in SCSSR No No Yes No No 1 2 3 Start of transmission Set SCPDR and SCPCR Note Numbers in parentheses refer to steps in the preceding procedure description Figure 14 8 Sample Flowchart for Transmitting Serial Data ...

Page 504: ... One 0 bit is output b Transmit data Seven or eight bits of data are output LSB first c Parity bit or multiprocessor bit One parity bit even or odd parity or one multiprocessor bit is output Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit One or two 1 bits stop bits are output e Marking Output of 1 bits continues until the start bit of the n...

Page 505: ... The procedure for receiving serial data after enabling the SCI for reception is 1 Receive error handling and break detection If a receive error occurs read the ORER PER and FER bits in SCSSR to identify the error After executing the necessary error handling clear ORER PER and FER to 0 Receiving cannot resume if ORER PER or FER remains set to 1 When a framing error occurs the RxD pin can be read t...

Page 506: ...tion No Yes PER FER ORER 1 RDRF 1 Yes Yes Clear RE bit in SCSCR to 0 No No Read RDRF bit in SCSSR Error handling Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 1 2 3 Note Numbers in parentheses refer to steps in the preceding procedure description Figure 14 10 Sample Flowchart for Receiving Serial Data ...

Page 507: ...R 1 Overrun error handling FER 1 Yes Break No Framing error handling PER 1 Yes Parity error handling Clear ORER PER and FER bits in SCSSR to 0 End No No No Yes Yes Clear RE bit in SCSCR to 0 Figure 14 10 Sample Flowchart for Receiving Serial Data cont ...

Page 508: ...he checks fails receive error the SCI operates as indicated in table 14 12 Note When a receive error flag is set further receiving is disabled The RDRF bit is not set to 1 Be sure to clear the error flags 4 After setting RDRF to 1 if the receive data full interrupt enable bit RIE is set to 1 in SCSCR the SCI requests a receive data full interrupt RXI If one of the error flags ORER PER or FER is se...

Page 509: ...al communication cycle consists of an ID sending cycle that identifies the receiving processor and a data sending cycle The multiprocessor bit distinguishes ID sending cycles from data sending cycles The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1 Next the transmitting processor sends tra...

Page 510: ...ransmitting Multiprocessor Serial Data Figure 14 13 shows a sample flowchart for transmitting multiprocessor serial data The procedure for transmitting multiprocessor serial data is 1 SCI status check and transmit data write Read the serial status register SCSSR check that the TDRE bit is 1 then write transmit data in the transmit data register SCTDR Also set MPBT multiprocessor bit transfer to 0 ...

Page 511: ... in SCSSR Clear TDRE bit to 0 Break output Yes Clear TE bit SCSCR to 0 End of transmission Yes Read TDRE bit in SCSSR No No Yes No No 1 2 3 Start of transmission Set SCPDR and SCPCR Note Numbers in parentheses refer to steps in the preceding procedure description Figure 14 13 Sample Flowchart for Transmitting Multiprocessor Serial Data ...

Page 512: ...tput of 1 bits continues until the start bit of the next transmit data 3 The SCI checks the TDRE bit when it outputs the stop bit If TDRE is 0 the SCI transfers data from SCTDR into SCTSR outputs the stop bit then begins serial transmission of the next frame If TDRE is 1 the SCI sets the TEND bit in SCSSR to 1 outputs the stop bit then continues output of 1 bits in the mark state If the transmit e...

Page 513: ...SCRDR and compare with the processor s own ID If the ID does not match the receive data set MPIE to 1 again and clear RDRF to 0 If the ID matches the receive data clear RDRF to 0 3 SCI status check and data receiving Read SCSSR check that RDRF is set to 1 then read data from the receive data register SCRDR 4 Receive error handling and break detection If a receive error occurs read the ORER and FER...

Page 514: ...and FER bits in SCSSR FER 1 or ORER 1 Read RDRF bit in SCSSR Read receive data from SCRDR Is ID the station s ID Yes Read ORER and FER bits in SSCSR No Error handling Yes Yes Yes No Start of reception No Yes Read receive data from SCRDR 1 2 4 3 Note Numbers in parentheses refer to steps in the preceding procedure description Figure 14 15 Sample Flowchart for Receiving Multiprocessor Serial Data ...

Page 515: ... Break Yes Framing error handling Yes Error handling Overrun error handling Yes FER 1 Clear ORER and FER bits in SCSSR to 0 End No No No Clear RE bit in SCSCR to 0 Figure 14 15 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...

Page 516: ... ID does not match data RXI interrupt handler reads RDR data and clears RDRF bit to 0 ID is not station s ID so MPIE bit is set to 1 again No RXI interrupt generated RDR state is maintained 0 1 1 1 1 0 1 Stop bit MPB Serial data Start bit Data ID1 Data data 1 Start bit MPB Stop bit Idle mark state D0 D1 D7 D0 D1 D7 0 Figure 14 16 Example of SCI Receive Operation 8 Bit Data with Multiprocessor Bit ...

Page 517: ...dle mark state D0 D1 D7 D0 D1 D7 0 RXI interrupt request multiprocessor interrupt generated MPIE 0 RXI interrupt handler reads RDR data and clears RDRF bit to 0 ID is that of station so reception continues unchanged and data is received by RXI interrupt handler MPIE bit set to 1 again Figure 14 16 Example of SCI Receive Operation cont 8 Bit Data with Multiprocessor Bit and One Stop Bit ...

Page 518: ...it 3 Bit 4 Bit 5 Bit 6 Bit 7 LSB MSB Serial clock Serial data One unit of communication data character or frame Note High except in continuous transmitting or receiving Figure 14 17 Data Format in Synchronous Communication In synchronous serial communication each data bit is output on the communication line from one falling edge of the serial clock to the next Data is guaranteed valid at the risin...

Page 519: ... transmitting receiving or changing the mode or communication format the software must clear the TE and RE bits to 0 in the serial control register SCSCR then initialize the SCI Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register SCTSR Clearing RE to 0 however does not initialize the RDRF PER FER and ORER flags and receive data register SCRDR which retain their previous con...

Page 520: ...ing procedure description Figure 14 18 Sample Flowchart for SCI Initialization Transmitting Serial Data Synchronous Mode Figure 14 19 shows a sample flowchart for transmitting serial data The procedure for transmitting serial data is 1 SCI status check and transmit data write Read the serial status register SCSSR check that the TDRE bit is 1 then write transmit data in the transmit data register S...

Page 521: ... End of transmission 1 2 TDRE 1 Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 Yes No Read TEND bit in SCSSR TEND 1 Yes No Clear TE bit in SCSCR to 0 Note Numbers in parentheses refer to steps in the preceding procedure description Figure 14 19 Sample Flowchart for Transmitting Serial Data ...

Page 522: ...utput from the TxD pin in order from the LSB bit 0 to the MSB bit 7 3 The SCI checks the TDRE bit when it outputs the MSB bit 7 If TDRE is 0 the SCI loads data from SCTDR into SCTSR then begins serial transmission of the next frame If TDRE is 1 the SCI sets the TEND bit in SCSSR to 1 transmits the MSB then holds the transmit data pin TxD in the MSB state If the transmit end interrupt enable bit TE...

Page 523: ...ror handling If a receive error occurs read the ORER bit in SCSSR to identify the error After executing the necessary error handling clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 2 SCI status check and receive data read Read the serial status register SCSSR check that RDRF is set to 1 then read receive data from the receive data register SCRDR and clear RDRF to 0 Th...

Page 524: ...F 1 Yes Clear RE bit in SCSCR to 0 No No Read RDRF bit in SCSSR 3 2 Yes Error handling 1 Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 Start of reception Note Numbers in parentheses refer to steps in the preceding procedure description Figure 14 21 Sample Flowchart for Receiving Serial Data ...

Page 525: ...RSR into SCRDR If this check is passed the SCI sets RDRF to 1 and stores the received data in SCRDR If the check is not passed receive error the SCI operates as indicated in table 14 12 This state prevents further transmission or reception While receiving the RDRF bit is not set to 1 Be sure to clear the error flag 3 After setting RDRF to 1 if the receive data full interrupt enable bit RIE is set ...

Page 526: ... data register SCTDR and clear TDRE to 0 The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1 2 Receive error handling If a receive error occurs read the ORER bit in SCSSR to identify the error After executing the necessary error handling clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 3 SCI status check and receive data read Read th...

Page 527: ...Error processing 2 ORER 1 No Read RDRF bit in SCSSR 4 Yes 3 Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 Clear TE and RE bits in SCSCR to 0 Notes 1 2 Numbers in parentheses refer to steps in the preceding procedure description In switching from transmitting or receiving to simultaneous transmitting and receiving clear both TE and RE to 0 then set both TE and RE to 1 simultaneously...

Page 528: ...E bit in SCSSR is set to 1 RXI is requested when the RDRF bit in SCSSR is set to 1 ERI is requested when the ORER PER or FER bit in SCSSR is set to 1 TEI is requested when the TEND bit in SCSSR is set to 1 Where the TXI interrupt indicates that transmit data writing is enabled the TEI interrupt indicates that the transmit operation is complete Table 14 13 SCI Interrupt Sources Interrupt Source Des...

Page 529: ...0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error framing error 1 1 1 0 X Overrun error parity error 1 1 0 1 X Framing error parity error 0 0 1 1 O Overrun error framing error parity error 1 1 1 1 X X Receive data is not transferred from SCRSR to SCRDR O Receive data is transferred from SCRSR to SCRDR Break Detection and Processing Break signals can be detected by reading the RxD ...

Page 530: ...ll not start transmitting even if TDRE is set to 1 Be sure to clear the receive error flags to 0 before starting to transmit Note that clearing RE to 0 does not clear the receive error flags Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode the SCI operates on a base clock of 16 times the transfer rate frequency In receiving the SCI synchronizes internally w...

Page 531: ...This is a theoretical value A reasonable margin to allow in system designs is 20 to 30 Notes on Synchronous External Clock Mode Do not set TE RE 1 until at least four clocks after external clock SCK has changed from 0 to 1 Set TE RE 1 only when external clock SCK is 1 When receiving RDRF is set to 1 when RE is set to zero 2 5 3 5 clocks after the rising edge of the SCK input of the D7 bit in RxD b...

Page 532: ...Rev 5 00 09 03 page 488 of 760 ...

Page 533: ...n the normal serial communication interface and the smart card interface 15 1 1 Features The smart card interface has the following features Asynchronous mode Data length 8 bits Parity bit generation and check Receive mode error signal detection parity error Transmit mode error signal detection and automatic re transmission of data Supports both direct convention and inverse convention Bit rate ca...

Page 534: ...Module data bus Internal data bus Pφ Pφ 4 Pφ 16 Pφ 64 TXI RXI ERI Bus interface Baud rate generator Transmit receive control SCSCMR SCRSR SCRDR SCTSR SCTDR SCSMR SCSCR SCSSR SCBRR Legend Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Figure 15 ...

Page 535: ...for the normal SCI function They are described in section 14 Serial Communication Interface SCI Table 15 2 Registers Name Abbreviation R W Initial Value 3 Address Access Size Serial mode register SCSMR R W H 00 H FFFFFE80 8 Bit rate register SCBRR R W H FF H FFFFFE82 8 Serial control register SCSCR R W H 00 H FFFFFE84 8 Transmit data register SCTDR R W H FF H FFFFFE86 8 Serial status register SCSS...

Page 536: ...elects the serial parallel conversion format Bit 3 SDIR Description 0 Contents of SCTDR are transferred LSB first and receive data is stored in SCRDR LSB first Initial value 1 Contents of SCTDR are transferred MSB first and receive data is stored in SCRDR MSB first Bit 2 Smart Card Data Inversion SINV Specifies whether to invert the logic level of the data This function is used in combination with...

Page 537: ... Receive Data Register Full RDRE Bit 5 Overrun Error ORER These bits have the same function as in the ordinary SCI See section 14 Serial Communication Interface SCI for more information Bit 4 Error Signal Status ERS In the smart card interface mode bit 4 indicates the state of the error signal returned from the receiving side during transmission The smart card interface cannot detect framing error...

Page 538: ...nd TDRE 1 and FER ERS 0 normal transmission 1 0 etu after a one byte serial character is transmitted Note etu Elementary Time Unit time for transfer of 1 bit 15 3 Operation 15 3 1 Overview The primary functions of the smart card interface are described below 1 Each frame consists of 8 bit data and 1 parity bit 2 During transmission the card leaves a guard time of at least 2 etu elementary time uni...

Page 539: ...d by the smart card interface on an IC card input the SCK pin output to the IC card s CLK pin This connection is not necessary when the internal clock is used on the IC card Use the chip s port output as the reset signal Apart from these pins power and ground pin connections are usually also required Note When the IC card is not connected and both RE and TE are set to 1 closed communication is pos...

Page 540: ...face The operating sequence is 1 The data line is high impedance when not in use and is fixed high with a pull up register 2 The transmitting side starts one frame of data transmission The data frame starts with a start bit Ds low level The start bit is followed by eight data bits D0 D7 and a parity bit Dp 3 On the smart card interface the data line returns to high impedance after this The data li...

Page 541: ...he serial control register SCSCR Clear the O E bit to 0 if the IC card uses the direct convention and set it to 1 if the card uses the inverse convention Select the on chip baud rate generator clock source with the CKS1 and CKS0 bits see section 15 3 5 Clock 2 Setting the bit rate register SCBRR Set the bit rate See section 15 3 5 Clock to see how to calculate the set value 3 Setting the serial co...

Page 542: ...7 D6 D5 D4 D3 D2 D1 D0 Dp A Z Z Z A A A A A A Z Z State b Inverse convention SDIR SINV and O E are all 1 Figure 15 4 Waveform of Start Character 15 3 5 Clock Only the internal clock generated by the on chip baud rate generator can be used as the communication clock in the smart card interface The bit rate for the clock is set by the bit rate register SCBRR and the CKS1 and CKS0 bits in the serial ...

Page 543: ...96 8 2 3200 0 4480 3 4800 0 5824 4 6400 0 7168 5 8064 5 Note The bit rate is rounded to one decimal place Calculate the value to be set in the bit rate register SCBRR from the operating frequency and the bit rate N is an integer in the range 0 N 255 specifying a smallish error N 106 1 1488 22n 1 B Pφ Table 15 6 Examples of SCBRR Settings for Bit Rate B Bits s n 0 φ φ φ φ MHz 9600 Bits s 7 1424 10 ...

Page 544: ...s on the smart card interface Table 15 8 Register Set Values and SCK Pin Register Value SCK Pin Setting SMIF C A A A A CKE1 CKE0 Output State 1 1 1 0 0 0 Port Determined by setting of port register SCP1MD1 and SCP1MD0 bits 1 0 0 1 SCK serial clock output state 2 2 1 1 0 0 Low output Low output state 1 1 0 1 SCK serial clock output state 3 2 1 1 1 0 High output High output state 1 1 1 1 SCK serial ...

Page 545: ... bits CKS1 and CKS0 bits in the serial mode register SCSMR At this time also clear the CHR and MP bits to 0 and set the STOP and PE bits to 1 4 Set the SMIF SDIR and SINV bits in the smart card mode register SCSCMR When the SMIF bit is set to 1 the TxD and RxD pins both switch from ports to SCI pins and become high impedance 5 Set the value corresponding to the bit rate in the bit rate register SC...

Page 546: ...SCR Has a 1 bit interval elapsed End 2 Set parity in O E bit set clock in CKS1 and CKS0 bits and set C A in SCSMR 3 Set clock in CKE1 and CKE0 bits and clear TIE RIE TE RE MPIE and TEIE bits to 0 in SCSCR 6 5 4 1 7 No Yes Set SMIF SDIR and SINV bits in SCSMR Note Numbers in parentheses refer to steps in the preceding procedure description Figure 15 5 Initialization Flowchart Example ...

Page 547: ... flag in SCSSR is set to 1 4 Write the transmit data into SCTDR clear the TDRE flag to 0 and start transmitting The TEND flag will be cleared to 0 5 To transmit more data return to step 2 6 To end transmission clear the TE bit to 0 This processing can be interrupted When the TIE bit is set to 1 and interrupt requests are enabled a transmit data empty interrupt TXI will be requested when the TEND f...

Page 548: ...SCTDR and clear TDRE flag in SCSSR to 0 1 Clear TE bit in SCSCR to 0 6 Error handling 2 FER ERS 0 TEND 1 Yes Yes Yes Yes No No All data transmitted No TEND 1 No Error handling FER ERS 0 Yes No 4 5 3 Note Numbers in parentheses refer to steps in the preceding procedure description Figure 15 6 Transmission Flowchart ...

Page 549: ...ag is set to 1 4 Read the receive data from SCRDR 5 To receive more data clear the RDRF flag to 0 and return to step 2 6 To end reception clear the RE bit to 0 This processing can be interrupted When the RIE bit is set to 1 and interrupt requests are enabled a receive data full interrupt RXI will be requested when the RDRF flag is set to 1 at the end of reception When an error occurs during recept...

Page 550: ...ceive data from SCRDR and clear RDRF flag in SCSSR to 0 1 Clear RE bit in SCSCR to 0 6 Error handling 2 ORER 0 or PER 0 RDRF 1 Yes Yes Yes No No All data received No 4 5 3 Note Numbers in parentheses refer to steps in the preceding procedure description Figure 15 7 Reception Flowchart Example ...

Page 551: ...o request a TXI interrupt Set the RDRF flag in SCSSR to 1 to request an RXI interrupt Set the ORER PER or FER ERS flag in SCSSR to 1 to request an ERI interrupt table 15 9 Table 15 9 Smart Card Mode Operating State and Interrupt Sources Mode State Flag Mask Bit Interrupt Source Transmit mode Normal TEND TIE TXI Error FER ERS RIE ERI Receive mode Normal RDRF RIE RXI Error PER ORER RIE ERI 15 4 Usag...

Page 552: ...ceive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation For smart card mode M 0 5 1 2N D 0 5 N L 0 5 F 1 F 100 Where M Receive margin N Ratio of bit rate to clock N 372 D Clock duty D 0 to 1 0 L Frame length L 10 F Absolute value of clock frequency deviation Using this equation the receive margin when F 0 and D 0 5 is as follows M 0 5 1 2 372 100 49 86...

Page 553: ...he frame that caused the error 3 When the received parity bit is checked and no error is found the PER bit in SCSSR is not set 4 When the received parity bit is checked and no error is found reception is considered to have been completed normally and the RDRF bit in SCSSR is automatically set to 1 If the RIE bit in SCSCR is enabled at this time an RXI interrupt is requested 5 When a normal frame i...

Page 554: ...he error signal indicating the error 3 The FER ERS bit in SCSSR is not set when no error signal is returned from the receiving side 4 When no error signal is returned from the receiving side the TEND bit in SCSSR is set to 1 when the transmission of the frame that includes the retransmission is considered completed If the TIE bit in SCSCR is enabled at this time a TXI interrupt will be requested D...

Page 555: ...evel low level It is also detected by reading the RxD level directly from the port SC data register SCPDR when a framing error occurs Full duplex communication The transmitting and receiving sections are independent so the SCI can transmit and receive simultaneously Both sections use 16 stage FIFO buffering so high speed continuous data transfer is possible in both the transmit and receive directi...

Page 556: ...XI TEI RXI BRI Bus interface Baud rate generator Transmit receive control SCRSR SCFRDR2 SCTSR SCFTDR2 SCSMR2 SCSCR2 Legend Receive shift register Receive FIFO data register 2 Transmit shift register Transmit FIFO data register 2 Serial mode register 2 Serial control register 2 SCSSR2 SCBRR2 SCFCR2 SCFDR2 SCPDR SCPCR Serial status register 2 Bit rate register 2 FIFO control register 2 FIFO data cou...

Page 557: ...nternal data bus Output enable Clock input enable SCIF Serial clock output Serial clock input R SCP5MD0 PCRW Reset C Q Q D R SCP5MD1 PCRW Reset C Q D R SCP5DT1 PDRW Reset SCPT 5 SCK2 C D PDRW Legend SCPDR write PDRR PCRW SCPDR read SCPCR write PDRR Note When reading the SCK2 pin clear the CKE1 and CKE0 bits in SCSCR to 0 and set the SCP5MD1 bit in SCSPR to 1 see section 14 2 8 SC Port Control Regi...

Page 558: ...760 Internal data bus Output enable SCIF Serial transmission output R SCP4MD0 PCRW Reset C Q Q D R SCP4MD1 PCRW Reset C Q D R SCP4DT1 PDRW Reset SCPT 4 TxD2 C D PCRW PDRW SCPCR write SCPDR write Legend Figure 16 3 SCPT 4 TxD2 Pin ...

Page 559: ... 16 4 SCPT 4 RxD2 Pin 16 1 3 Pin Configuration The SCIF has the serial pins summarized in table 16 1 Table 16 1 SCIF Pins Pin Name Abbreviation I O Function Serial clock pin SCK2 I O Clock I O Receive data pin RxD2 Input Receive data input Transmit data pin TxD2 Output Transmit data output Request to send pin RTS2 Output Request to send Clear to send pin CTS2 Input Clear to send ...

Page 560: ...egister 2 SCFTDR2 W H 04000156 H A4000156 2 8 bits Serial status register 2 SCSSR2 R W 1 H 0060 H 04000158 H A4000158 2 16 bits Receive FIFO data register 2 SCFRDR2 R Undefined H 0400015A H A400015A 2 8 bits FIFO control register 2 SCFCR2 R W H 00 H 0400015C H A400015C 2 8 bits FIFO data count register 2 SCFDR2 R H 0000 H 0400015E H A400015E 2 16 bits Notes These registers are located in area 1 of...

Page 561: ...ng the received data from the receive shift register SCRSR into SCFRDR for storage Continuous reception is possible until 16 bytes are stored The CPU can read but not write to SCFRDR If data is read when there is no receive data in the SCFRDR the value is undefined When this register is full of receive data subsequent serial data is lost Bit 7 6 5 4 3 2 1 0 R W R R R R R R R R 16 2 3 Transmit Shif...

Page 562: ...he data is ignored Bit 7 6 5 4 3 2 1 0 R W W W W W W W W W 16 2 5 Serial Mode Register SCSMR The serial mode register SCSMR is an 8 bit register that specifies the SCIF serial communication format and selects the clock source for the baud rate generator The CPU can always read and write to SCSMR SCSMR is initialized to H 00 by a reset and in standby or module standby mode Bit 7 6 5 4 3 2 1 0 CHR P...

Page 563: ... even number of 1s in the transmitted character and parity bit combined Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined 2 If odd parity is selected the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined Receive data is checked to see if it has an odd number of 1s in th...

Page 564: ...d to H 00 by a reset and in standby or module standby mode Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R R R W R W Bit 7 Transmit Interrupt Enable TIE Enables or disables the transmit FIFO data empty interrupt TXI requested when the serial transmit data is transferred from the transmit FIFO data register SCFTDR to the transmit shift register SCTSR ...

Page 565: ...r by clearing RIE to 0 With the RDF flag read 1 from the RDF flag and clear it to 0 after reading receive data from SCRDR until the quantity of receive data becomes less than the specified receive trigger number Bit 5 Transmit Enable TE Enables or disables the SCIF serial transmitter Bit 5 TE Description 0 Transmitter disabled Initial value 1 Transmitter enabled Note Serial transmission starts aft...

Page 566: ... for clock output 1 1 0 External clock SCK pin used for clock input 2 1 External clock SCK pin used for clock input 2 Notes 1 The output clock frequency is 16 times the bit rate 2 The input clock frequency is 16 times the bit rate 16 2 7 Serial Status Register SCSSR The serial status register SCSSR is a 16 bit register The upper 8 bits indicate the number of receive errors in the SCFRDR data and t...

Page 567: ... O E bit in SCSMR Notes 1 Clearing the RE bit to 0 in SCSCR does not affect the ER bit which retains its previous value Even if a receive error occurs the receive data is transferred to SCFRDR and the receive operation is continued Whether or not the data read from SCRDR includes a receive error can be detected by the FER and PER bits in SCSSR 2 In stop mode only the first stop bit is checked the ...

Page 568: ...f transmission Note Since SCFTDR is a 16 byte FIFO register the maximum quantity of data that can be written when TDFE is 1 is 16 minus the specified transmission trigger number If an attempt is made to write additional data the data is ignored The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFTDR Bit 4 Break Detection BRK Indicates that a break signal has been detected in rece...

Page 569: ...r occurred in the data read from SCFRDR Setting condition When a framing error is present in the data read from SCFRDR Bit 2 Parity Error PER Indicates a parity error in the data read from the receive FIFO data register SCFRDR Bit 2 PER Description 0 No receive parity error occurred in the data read from SCFRDR Initial value Clearing conditions 1 When the chip undergoes a power on reset or enters ...

Page 570: ...uantity of data that can be read when RDF is 1 is the specified receive trigger number If an attempt is made to read after all the data in SCFRDR has been read the data is undefined The quantity of receive data in SCFRDR is indicated by the lower 8 bits of SCFTDR Bit 0 Receive Data Ready DR Indicates that the quantity of data in the receive FIFO data register SCFRDR is less than the specified rece...

Page 571: ...16 2 8 Bit Rate Register SCBRR The bit rate register SCBRR is an 8 bit register that together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register SCSMR determines the serial transmit receive bit rate The CPU can always read and write to SCBRR SCBRR is initialized to H FF by a reset and in module standby or standby mode Each channel has independe...

Page 572: ...t Rates and SCBRR Settings Pφ φ φ φ MHz 2 2 097152 2 4576 Bit Rate bits s n N Error n N Error n N Error 110 1 141 0 03 1 148 0 04 1 174 0 26 150 1 103 0 16 1 108 0 21 1 127 0 00 300 0 207 0 16 0 217 0 21 0 255 0 00 600 0 103 0 16 0 108 0 21 0 127 0 00 1200 0 51 0 16 0 54 0 70 0 63 0 00 2400 0 25 0 16 0 26 1 14 0 31 0 00 4800 0 12 0 16 0 13 2 48 0 15 0 00 9600 0 6 6 99 0 6 2 48 0 7 0 00 19200 0 2 8...

Page 573: ...4 0 11 0 00 0 12 0 16 19200 0 4 2 34 0 5 0 00 0 6 6 99 31250 0 2 0 00 0 3 7 84 0 3 0 00 38400 0 2 0 00 0 2 8 51 Pφ φ φ φ MHz 4 9152 5 6 Bit Rate bits s n N Error n N Error n N Error 110 2 86 0 31 2 88 0 25 2 106 0 44 150 1 255 0 00 2 64 0 16 2 77 0 16 300 1 127 0 00 1 129 0 16 1 155 0 16 600 0 255 0 00 1 64 0 16 1 77 0 16 1200 0 127 0 00 0 129 0 16 0 155 0 16 2400 0 63 0 00 0 64 0 16 0 77 0 16 480...

Page 574: ...0 0 6 5 33 0 7 0 00 38400 0 4 0 00 0 5 0 00 0 6 6 99 Pφ φ φ φ MHz 9 8304 10 12 12 288 Bit Rate bits s n N Error n N Error n N Error n N Error 110 1 174 0 26 2 177 0 25 1 212 0 03 2 217 0 08 150 1 127 0 00 2 129 0 16 1 155 0 16 2 159 0 00 300 0 255 0 00 2 64 0 16 1 77 0 16 2 79 0 00 600 0 127 0 00 1 129 0 16 0 155 0 16 1 159 0 00 1200 0 255 0 00 1 64 0 16 0 77 0 16 1 79 0 00 2400 0 127 0 00 0 129 0...

Page 575: ... 00 0 12 0 16 0 15 0 00 0 15 1 73 115200 0 3 0 00 0 3 8 51 0 4 6 67 0 4 8 51 500000 0 0 7 84 0 0 0 00 0 0 22 9 0 0 25 0 Pφ φ φ φ MHz 24 24 576 28 7 30 Bit Rate bits s n N Error n N Error n N Error n N Error 110 3 106 0 44 3 108 0 08 3 126 0 31 3 132 0 13 150 3 77 0 16 3 79 0 00 3 92 0 46 3 97 0 35 300 2 155 0 16 2 159 0 00 2 186 0 08 2 194 0 16 600 2 77 0 16 2 79 0 00 2 92 0 46 2 97 0 35 1200 1 15...

Page 576: ...m Bit Rates for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings Pφ φ φ φ MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 8 250000 0 0 9 8304 307200 0 0 12 375000 0 0 14 7456 460800 0 0 16 500000 0 0 19 6608 614400 0 0 20 625000 0 0 24 750000 0 0 24 576 768000 0 0 28 7 896875 0 0 30 ...

Page 577: ...m Bit Rate bits s 2 0 5000 31250 2 097152 0 5243 32768 2 4576 0 6144 38400 3 0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 8 2 0000 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 19 6608 4 9152 307200 20 5 0000 312500 24 6 0000 375000 24 576 6 1440 384000 28 7 7 1750 448436 30 7 5000 468750 ...

Page 578: ...data full RDF flag in the serial status register SCSSR The RDF flag is set to 1 when the quantity of receive data stored in the receive FIFO register SCFRDR exceeds the set trigger number shown below Bit 7 RTRG1 Bit 6 RTRG0 Receive Trigger Number 0 0 1 Initial value 0 1 4 1 0 8 1 1 14 Bits 5 and 4 Transmit FIFO Data Trigger TTRG1 TTRG0 Set the quantity of remaining transmit data which sets the tra...

Page 579: ...escription 0 Reset operation disabled Initial value 1 Reset operation enabled Note Reset is executed in a reset or in standby mode Bit 1 Receive FIFO Data Register Reset RFRST Disables the receive data in the receive FIFO data register and resets the data to the empty state Bit 1 RFRST Description 0 Reset operation disabled Initial value 1 Reset operation enabled Note Reset is executed in a reset ...

Page 580: ... bits SCFDR can always be read by the CPU Upper 8 Bits 15 14 13 12 11 10 9 8 T4 T3 T2 T1 T0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R The upper 8 bits of SCFDR indicate the quantity of non transmitted data stored in SCFTDR H 00 means no transmit data and H 10 means that SCFTDR is full of transmit data Lower 8 Bits 7 6 5 4 3 2 1 0 R4 R3 R2 R1 R0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R...

Page 581: ...tions constitutes the communication format and character length In receiving it is possible to detect framing errors FER parity errors PER receive FIFO data full receive data ready and breaks In transmitting it is possible to detect transmit FIFO data empty The number of stored data bytes is indicated for both the transmit and receive FIFO registers An internal or external clock can be selected as...

Page 582: ...n Transmit Receive Formats Table 16 9 lists the eight communication formats that can be selected The format is selected by settings in the serial mode register SCSMR Table 16 9 Serial Communication Formats SCSMR Bits Serial Transmit Receive Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 START 8 bit data STOP 0 0 1 START 8 bit data STOP STOP 0 1 0 START 8 bit data P STOP 0 1 1...

Page 583: ... SCFRDR which retain their previous contents Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCSSR is set The TE bit can be cleared to 0 during transmission but the transmit data goes to the high impedance state after the bit is cleared to 0 Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission When an external clock is us...

Page 584: ... Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1 and set RIE TIE TEIE and MPIE bits Set communication format in SCSMR Yes No Set value in SCBRR Set CKE1 and CKE0 bits in SCSCR leaving TE and RE bits cleared to 0 End 1 2 3 4 Wait Note Numbers in parentheses refer to steps in the preceding procedure description Figure 16 5 Sample Flowchart for SCIF Initialization ...

Page 585: ...mit trigger set number 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write data to SCFTDR and then clear the TDFE flag to 0 3 Break output at the end of serial transmission To output a break in serial transmission set the port SC data register SCPDR and port SC control register SCPCR then clear the TE...

Page 586: ...Yes No TDFE 1 No All data transmitted No Yes Yes Break output Yes No Write transmit data 16 transmit trigger set number to SCFTDR read 1 from TDFE bit and TEND flag in SCSSR then clear to 0 End of transmission 1 2 3 Note Numbers in parentheses refer to steps in the preceding procedure description Figure 16 6 Sample Flowchart for Transmitting Serial Data ...

Page 587: ... If the TIE bit in the serial control register SCSR is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the TxD pin in the following order a Start bit One bit 0 is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is ...

Page 588: ...ration 8 Bit Data Parity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the CTS input value When CTS is set to 1 if transmission is in progress the line goes to the mark state after transmission of one frame When CTS is set to 0 the next transmit data is output starting from the start bit Figure 16 8 shows an example of the operation when ...

Page 589: ...tected by reading the value of the RxD pin 2 SCIF status check and receive data read Read the serial status register SCSSR and check that RDF 1 then read the receive data in the receive FIFO data register SCFRDR read 1 from the RDF flag and then clear the RDF flag to 0 The transition of the RDF flag from 0 to 1 can be identified by an RXI interrupt 3 Serial reception continuation procedure To cont...

Page 590: ...n No Yes PER v FER v ORER 1 RDF 1 Yes Yes Clear RE bit in SCSCR to 0 No No Read RDF flag in SCSSR Error handling Read receive data from SCFRDR and clear RDF flag in SCSSR to 0 1 2 3 Note Numbers in parentheses refer to steps in the preceding procedure description Figure 16 9 Sample Flowchart for Receiving Serial Data ...

Page 591: ...ed receive data is not transferred to SCFRDR while the BRK flag is set However note that the last data in SCFRDR is H 00 and the break data in which a framing error occurred is stored Error handling End BRK 1 DR 1 ER 1 Yes Yes Yes Clear DR ER BRK flags in SCSSR to 0 No No No Receive error handling Break processing Read receive data from SCFRDR 1 2 Figure 16 10 Sample Flowchart for Receiving Serial...

Page 592: ...b The SCIF checks whether receive data can be transferred from the receive shift register SCRSR to SCFRDR c Break check The SCIF checks that the BRK flag is 0 indicating that the break state is not set If all the above checks are passed the receive data is stored in SCFRDR Note Reception is not suspended when a receive error occurs 4 If the RIE bit in SCSR is set to 1 when the RDF or DR flag chang...

Page 593: ... Data Stop bit Idle mark state D0 D1 D7 D0 D1 D7 0 1 Figure 16 11 Example of SCIF Receive Operation 8 Bit Data Parity One Stop Bit 5 When modem control is enabled the RTS signal is output when SCFRDR is empty When RTS is 0 reception is possible When RTS is 1 this indicates that SCFRDR is full and reception is not possible Figure 16 12 shows an example of the operation when modem control is used 0 ...

Page 594: ...s generated The DMAC can be activated and data transfer performed when the RDF flag in SCSSR is set to 1 When receive data less than the receive trigger number is read from the receive data register SCFRDR by the DMAC 1 is read from the RDF flag after which 0 is written to it to clear it When the ER flag in SCSSR is set to 1 an ERI interrupt request is generated When the BRK flag in SCSSR is set t...

Page 595: ...ber can be read from SCFRDR allowing efficient continuous reception However if the number of data bytes in SCFRDR exceeds the trigger number the RDF flag will be set to 1 again even after having been cleared to 0 RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FI...

Page 596: ...synchronizes internally with the fall of the start bit which it samples on the base clock Receive data is latched at the rising edge of the eighth base clock pulse The timing is shown in figure 16 13 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 Base clock Receive data RxD Synchro nization sampling timing Data sampling timing 8 clocks 16 clocks Start bit 7 5 clocks ...

Page 597: ...Rev 5 00 09 03 page 553 of 760 Equation 2 When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 This is a theoretical value A reasonable margin to allow in system designs is 20 to 30 ...

Page 598: ...Rev 5 00 09 03 page 554 of 760 ...

Page 599: ...IF by making register settings 17 1 1 Features Conforms to the IrDA 1 0 system Asynchronous serial communication Data length 8 bits Stop bit length 1 bit Parity bit None On chip 16 stage FIFO buffers for both transmit and receive operations On chip baud rate generator with selectable bit rates Guard functions to protect the receiver during transmission Clock supply halted to reduce power consumpti...

Page 600: ...ram Figure 17 1 shows a block diagram of the IrDA SCIF Clock input TxD Transfer clock RxD Switching IrDA SCIF IrDA SCK TxD1 RxD1 Modulation unit Demodulation unit Legend SCIF Serial communication interface with FIFO Figure 17 1 Block Diagram of IrDA ...

Page 601: ...R Internal data bus Output enable Clock input enable IrDA Serial clock output Serial clock input R SCP3MD0 PCRW Reset C Q Q D R SCP3MD1 PCRW Reset C Q D R SCP3DT1 PDRW Reset SCPT 3 SCK1 C D PDRW Legend SCPDR write PDRR PCRW SCPDR read SCPCR write PDRR Note When reading the SCK1 pin the CKE1 and CKE0 bits in SCSCR to 0 and set the SCP3MD1 bit in SCPCR to 1 see section 14 2 8 SC Port Control Registe...

Page 602: ...f 760 Internal data bus Output enable IrDA Serial transfer output Q R SCP2DT1 PDRW Reset SCPT 2 TxD1 C D PCRW PDRW Legend SCPCR write SCPDR write R SCP2MD0 PCRW Reset C Q D R SCP2MD1 PCRW Reset C Q D Figure 17 3 SCPT 2 TxD1 Pin ...

Page 603: ...to 1 Figure 17 4 SCPT 2 RxD1 Pin 17 1 3 Pin Configuration The IrDA has the serial pins summarized in table 17 1 Table 17 1 IrDA Pins Pin Name Signal Name I O Function Serial clock pin SCK1 I O Clock I O Receive data pin RxD1 Input Receive data input Transmit data pin TxD1 Output Transmit data output Note Clock input from the serial clock pin cannot be set in IrDA mode ...

Page 604: ...t FIFO data register 1 SCFTDR1 W H 04000146 H A4000146 2 8 bits Serial status register 1 SCSSR1 R W 1 H 0060 H 04000148 H A4000148 2 16 bits Receive FIFO data register 1 SCFRDR1 R Undefined H 0400014A H A400014A 2 8 bits FIFO control register 1 SCFCR1 R W H 00 H 0400014C H A400014C 2 8 bits FIFO data count register 1 SCFDR1 R H 0000 H 0400014E H A400014E 2 16 bits Notes These registers are located...

Page 605: ... IrDA output pulse width and selects the baud rate generator clock source This module operates as IrDA when the IRMOD bit is set to 1 At this time bits 3 to 6 are fixed at 0 This register functions in the same way as the SCSMR register in the SCIF when the IRMOD bit is cleared to 0 therefore this module can also operate as an SCIF SCSMR is initialized to H 00 by a power on reset or manual reset wh...

Page 606: ...n t care Don t care 0 Pulse width 3 16 of bit length It is necessary to generate a fixed clock pulse IRCLK by dividing the Pφ clock by 1 2N 2 with the value of N determined by the setting of ICK3 ICK0 Example Pφ clock 14 7456 MHz IRCLK 921 6 kHz fixed N Setting of ICK3 ICK0 0 N 15 1 7 N Pφ 2XIRCLK Accordingly N is 7 Bits 1 and 0 Clock Select 1 and 0 CKS1 CKS0 Select the internal baud rate generato...

Page 607: ...on is first performed at a speed of 9600 bps and the communication speed is changed However the communication rate cannot be automatically changed in this module so the communication speed should be confirmed and the appropriate speed set for this module by software Note In IrDA mode reception cannot be performed when the TE bit in the serial control register SCSCR is set to 1 enabling transmissio...

Page 608: ...ame as shown in figure 17 5 Demodulation to 0 is performed for pulse output and demodulation to 1 is performed for no pulse output UART frame Data IR frame Data Receive Transmit Stop bit Stop bit Start bit Start bit Bit cycle 3 16 bit cycle pulse width 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 1 Figure 17 5 Transmit Receive Operation ...

Page 609: ...t output port D18 input output data bus A PTA1 input output port D17 input output data bus A PTA0 input output port D16 input output data bus B PTB7 input output port D31 input output data bus B PTB6 input output port D30 input output data bus B PTB5 input output port D29 input output data bus B PTB4 input output port D28 input output data bus B PTB3 input output port D27 input output data bus B P...

Page 610: ...ut output port CE2A output PCMCIA E PTE3 input output port E PTE2 input output port RAS3U output BSC E PTE1 input output port E PTE0 input output port TDO output UDI F PTF7 input port PINT15 input INTC TRST input AUD UDI F PTF6 input port PINT14 input INTC TMS input UDI F PTF5 input port PINT13 input INTC TD1 input UDI F PTF4 input port PINT12 input INTC TCK input UDI F PTF3 input port PINT11 inpu...

Page 611: ...PG J PTJ6 input output port STATUS0 output CPG J PTJ5 input output port J PTJ4 input output port J PTJ3 input output port CASU output BSC J PTJ2 input output port CASL output BSC J PTJ1 input output port J PTJ0 input output port RAS3L output BSC K PTK7 input output port WE3 output BSC DQMUU output BSC ICIOWR output BSC K PTK6 input output port WE2 output BSC DQMUL output BSC ICIORD output BSC K PT...

Page 612: ...2 output UART ch 3 SCPT SCPT5 input output port SCK2 input output UART ch 3 SCPT SCPT4 input port RxD2 input UART ch 3 SCPT4 output port TxD2 output UART ch 3 SCPT SCPT3 input output port SCK1 input output UART ch 2 SCPT SCPT2 input port RxD1 input UART ch 2 SCPT2 output port TxD1 output UART ch 2 SCPT SCPT1 input output port SCK0 input output UART ch 1 SCPT SCPT0 input port RxD0 input UART ch 1 S...

Page 613: ...A H 0400010E H A400010E 16 Port J control register PJCR R W H 0000 H 04000110 H A4000110 16 Port K control register PKCR R W H 0000 H 04000112 H A4000112 16 Port L control register PLCR R W H 0000 H 04000114 H A4000114 16 SC port control register SCPCR R W H A888 H 04000116 H A4000116 16 Notes 1 The initial value of the port E F G and H control registers depends on the state of the ASEMD0 pin If a...

Page 614: ...0000 by a power on reset but is not initialized by a manual reset in standby mode or in sleep mode Bits 15 and 14 PA7 Mode 1 and 0 PA7MD1 PA7MD0 Bits 13 and 12 PA6 Mode 1 and 0 PA6MD1 PA6MD0 Bits 11 and 10 PA5 Mode 1 and 0 PA5MD1 PA5MD0 Bits 9 and 8 PA4 Mode 1 and 0 PA4MD1 PA4MD0 Bits 7 and 6 PA3 Mode 1 and 0 PA3MD1 PA3MD0 Bits 5 and 4 PA2 Mode 1 and 0 PA2MD1 PA2MD0 Bits 3 and 2 PA1 Mode 1 and 0 P...

Page 615: ...er on reset but is not initialized by a manual reset in standby mode or in sleep mode Bits 15 and 14 PB7 Mode 1 and 0 PB7MD1 PB7MD0 Bits 13 and 12 PB6 Mode 1 and 0 PB6MD1 PB6MD0 Bits 11 and 10 PB5 Mode 1 and 0 PB5MD1 PB5MD0 Bits 9 and 8 PB4 Mode 1 and 0 PB4MD1 PB4MD0 Bits 7 and 6 PB3 Mode 1 and 0 PB3MD1 PB3MD0 Bits 5 and 4 PB2 Mode 1 and 0 PB2MD1 PB2MD0 Bits 3 and 2 PB1 Mode 1 and 0 PB1MD1 PB1MD0 ...

Page 616: ...er on reset but is not initialized by a manual reset in standby mode or in sleep mode Bits 15 and 14 PC7 Mode 1 and 0 PC7MD1 PC7MD0 Bits 13 and 12 PB6 Mode 1 and 0 PC6MD1 PC6MD0 Bits 11 and 10 PC5 Mode 1 and 0 PC5MD1 PC5MD0 Bits 9 and 8 PC4 Mode 1 and 0 PC4MD1 PC4MD0 Bits 7 and 6 PC3 Mode 1 and 0 PC3MD1 PC3MD0 Bits 5 and 4 PC2 Mode 1 and 0 PC2MD1 PC2MD0 Bits 3 and 2 PC1 Mode 1 and 0 PC1MD1 PC1MD0 ...

Page 617: ...and 10 PD5 Mode 1 and 0 PD5MD1 PD5MD0 Bits 7 and 6 PD3 Mode 1 and 0 PD3MD1 PD3MD0 Bits 5 and 4 PD2 Mode 1 and 0 PD2MD1 PD2MD0 Bits 3 and 2 PD1 Mode 1 and 0 PD1MD1 PD1MD0 Bits 1 and 0 PD0 Mode 1 and 0 PD0MD1 PD0MD0 These bits select the pin functions and perform input pull up MOS control Bit 2n 1 Bit 2n PDnMD1 PDnMD0 Pin Function 0 0 Other function see table 18 1 Initial value n 2 0 1 Port output 1...

Page 618: ...nd 14 PE7 Mode 1 and 0 PE7MD1 PE7MD0 Bits 13 and 12 PE6 Mode 1 and 0 PE6MD1 PE6MD0 Bits 11 and 10 PE5 Mode 1 and 0 PE5MD1 PE5MD0 Bits 9 and 8 PE4 Mode 1 and 0 PE4MD1 PE4MD0 Bits 7 and 6 PE3 Mode 1 and 0 PE3MD1 PE3MD0 Bits 5 and 4 PE2 Mode 1 and 0 PE2MD1 PE2MD0 Bits 3 and 2 PE1 Mode 1 and 0 PE1MD1 PE1MD0 Bits 1 and 0 PE0 Mode 1 and 0 PE0MD1 PE0MD0 These bits select the pin functions and perform inp...

Page 619: ...e Bits 15 and 14 PF7 Mode 1 and 0 PF7MD1 PF7MD0 Bits 13 and 12 PF6 Mode 1 and 0 PF6MD1 PF6MD0 Bits 11 and 10 PF5 Mode 1 and 0 PF5MD1 PF5MD0 Bits 9 and 8 PF4 Mode 1 and 0 PF4MD1 PF4MD0 Bits 7 and 6 PF3 Mode 1 and 0 PF3MD1 PF3MD0 Bits 5 and 4 PF2 Mode 1 and 0 PF2MD1 PF2MD0 Bits 3 and 2 PF1 Mode 1 and 0 PF1MD1 PF1MD0 Bits 1 and 0 PF0 Mode 1 and 0 PF0MD1 PF0MD0 These bits select the pin functions and ...

Page 620: ... register that selects the pin functions PGCR is initialized to H AAAA ASEMD0 1 or H A200 ASEMD0 0 by a power on reset but is not initialized by a manual reset in standby mode or in sleep mode Bits 15 and 14 PG7 Mode 1 and 0 PG7MD1 PG7MD0 Bits 13 and 12 PG6 Mode 1 and 0 PG6MD1 PG6MD0 Bits 11 and 10 PG5 Mode 1 and 0 PG5MD1 PG5MD0 Bits 9 and 8 PG4 Mode 1 and 0 PG4MD1 PG4MD0 Bits 7 and 6 PG3 Mode 1 a...

Page 621: ...PG0MD0 Pin Function 0 0 Other function see table 18 1 Initial value ASEMD0 0 0 1 Reserved 1 0 Port input Pull up MOS on Initial value ASEMD0 1 1 1 Port input Pull up MOS off Note Controlled by PG1MD1 bit 3 not PG0MD1 bit 1 18 3 8 Port H Control Register PHCR Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PH7 MD1 PH7 MD0 PH6 MD1 PH6 MD0 PH5 MD1 PH5 MD0 PH4 MD1 PH4 MD0 PH3 MD1 PH3 MD0 PH2 MD1 PH2 MD0 PH1...

Page 622: ...0 PH4MD1 PH4MD0 Bits 7 and 6 PH3 Mode 1 and 0 PH3MD1 PH3MD0 Bits 5 and 4 PH2 Mode 1 and 0 PH2MD1 PH2MD0 Bits 3 and 2 PH1 Mode 1 and 0 PH1MD1 PH1MD0 Bits 1 and 0 PH0 Mode 1 and 0 PH0MD1 PH0MD0 These bits select the pin functions and perform input pull up MOS control Bit 13 Bit 12 PH6MD1 PH6MD0 Pin Function 0 0 Other function see table 18 1 Initial value ASEMD0 0 0 1 Reserved 1 0 Port input Pull up ...

Page 623: ... is not initialized by a manual reset in standby mode or in sleep mode Bits 15 and 14 PJ7 Mode 1 and 0 PJ7MD1 PJ7MD0 Bits 13 and 12 PJ6 Mode 1 and 0 PJ6MD1 PJ6MD0 Bits 11 and 10 PJ5 Mode 1 and 0 PJ5MD1 PJ5MD0 Bits 9 and 8 PJ4 Mode 1 and 0 PJ4MD1 PJ4MD0 Bits 7 and 6 PJ3 Mode 1 and 0 PJ3MD1 PJ3MD0 Bits 5 and 4 PJ2 Mode 1 and 0 PJ2MD1 PJ2MD0 Bits 3 and 2 PJ1 Mode 1 and 0 PJ1MD1 PJ1MD0 Bits 1 and 0 PJ...

Page 624: ...er on reset but is not initialized by a manual reset in standby mode or in sleep mode Bits 15 and 14 PK7 Mode 1 and 0 PK7MD1 PK7MD0 Bits 13 and 12 PK6 Mode 1 and 0 PK6MD1 PK6MD0 Bits 11 and 10 PK5 Mode 1 and 0 PK5MD1 PK5MD0 Bits 9 and 8 PK4 Mode 1 and 0 PK4MD1 PK4MD0 Bits 7 and 6 PK3 Mode 1 and 0 PK3MD1 PK3MD0 Bits 5 and 4 PK2 Mode 1 and 0 PK2MD1 PK2MD0 Bits 3 and 2 PK1 Mode 1 and 0 PK1MD1 PK1MD0 ...

Page 625: ... mode Bits 15 and 14 PL7 Mode 1 and 0 PL7MD1 PL7MD0 Bits 13 and 12 PL6 Mode 1 and 0 PL6MD1 PL6MD0 Bits 11 and 10 PL5 Mode 1 and 0 PL5MD1 PL5MD0 Bits 9 and 8 PL4 Mode 1 and 0 PL4MD1 PL4MD0 Bits 7 and 6 PL3 Mode 1 and 0 PL3MD1 PL3MD0 Bits 5 and 4 PL2 Mode 1 and 0 PL2MD1 PL2MD0 Bits 3 and 2 PL1 Mode 1 and 0 PL1MD1 PL1MD0 Bits 1 and 0 PL0 Mode 1 and 0 PL0MD1 PL0MD0 These bits select the pin functions ...

Page 626: ...l reset in standby mode or in sleep mode When the TE bit in SCSCR is set to 1 the other function output state has a higher priority than the SCPCR setting for the TxD 2 0 pins When the RE bit in SCSCR is set to 1 the input state has a higher priority than the SCPCR setting for the RxD 2 0 pins Bits 15 and 14 SCP7 Mode 1 and 0 SCP7MD1 SCP7MD0 These bits select the pin function and perform input pul...

Page 627: ...CPT 4 output pin Receive data input 2 RxD2 1 0 SCPT 4 input pin pull up input pin Transmit data output 2 TxD2 1 1 General input SCPT 4 input pin Transmit data output 2 TxD2 Note There is no SCPT 4 simultaneous I O combination because one bit SCP4DT is accessed using two pins TxD2 and RxD2 When port input is set bit SCPnMD1 is set to 1 and when the TE bit in SCSCR is set to 1 the TxD2 pin is in the...

Page 628: ...ransmit data output 1 TxD1 Note There is no SCPT 2 simultaneous I O combination because one bit SCP2DT is accessed using two pins TxD1 and RxD1 When port input is set bit SCPnMD1 is set to 1 and when the TE bit in SCSCR is set to 1 the TxD1 pin is in the output state When the TE bit is cleared to 0 the TxD1 pin goes to the high impedance state Bits 3 and 2 SCP1 Mode 1 and 0 SCP1MD1 SCP1MD0 These b...

Page 629: ... 0 output pin Receive data input 0 RxD0 1 0 SCPT 0 input pin pull up input pin Transmit data output 0 TxD0 1 1 General input SCPT 0 input pin Transmit data output 0 TxD0 Note There is no SCPT 0 simultaneous I O combination because one bit SCP0DT is accessed using two pins TxD0 and RxD0 When port input is set bit SCPnMD1 is set to 1 and when the TE bit in SCSCR is set to 1 the TxD0 pin is in the ou...

Page 630: ...Rev 5 00 09 03 page 586 of 760 ...

Page 631: ...nput output PTA5 input output D21 input output PTA4 input output D20 input output PTA3 input output D19 input output PTA2 input output D18 input output PTA1 input output D17 input output PTA0 input output D16 input output Port A Figure 19 1 Port A 19 2 1 Register Description Table 19 1 summarizes the port A register Table 19 1 Port A Register Name Abbreviation R W Initial Value Address Access Size...

Page 632: ...he function is general input port if the port is read the corresponding pin level is read Table 19 2 shows the function of PADR PADR is initialized to H 00 by a power on reset It retains its previous value in standby mode and sleep mode and in a manual reset Table 19 2 Port A Data Register PADR Read Write Operations PAnMD1 PAnMD0 Pin State Read Write 0 0 Other function See table 18 1 PADR value Va...

Page 633: ... PTB1 input output D25 input output PTB0 input output D24 input output Port B Figure 19 2 Port B 19 3 1 Register Description Table 19 3 summarizes the port B register Table 19 3 Port B Register Name Abbreviation R W Initial Value Address Access Size Port B data register PBDR R W H 00 H 04000122 H A4000122 8 Notes This register is located in area 1 of physical space Therefore when the cache is on e...

Page 634: ...he function is general input port if the port is read the corresponding pin level is read Table 19 4 shows the function of PBDR PBDR is initialized to H 00 by a power on reset It retains its previous value in standby mode and sleep mode and in a manual reset Table 19 4 Port B Data Register PBDR Read Write Operations PBnMD1 PBnMD0 Pin State Read Write 0 0 Other function See table 18 1 PBDR value Va...

Page 635: ...ut MSC2 output PTC1 input output PINT1 input MSC1 output PTC0 input output PINT0 input MSC0 output Port C Figure 19 3 Port C 19 4 1 Register Description Table 19 5 summarizes the port C register Table 19 5 Port C Register Name Abbreviation R W Initial Value Address Access Size Port C data register PCDR R W H 00 H 04000124 H A4000124 8 Notes This register is located in area 1 of physical space Ther...

Page 636: ...ng pin level is read Table 19 6 shows the function of PCDR PCDR is initialized to H 00 by a power on reset after which the general input port function pull up MOS on is set as the initial pin function and the corresponding pin levels are read PCDR retains its previous value in standby mode and sleep mode and in a manual reset Table 19 6 Port C Data Register PCDR Read Write Operations PCnMD1 PCnMD0...

Page 637: ...put DRAK0 output PTD0 input output DRAK1 output Port D Figure 19 4 Port D 19 5 1 Register Description Table 19 7 summarizes the port D register Table 19 7 Port D Register Name Abbreviation R W Initial Value Address Access Size Port D data register PDDR R W or R B 0 0 0000 H 04000126 H A4000126 1 8 Notes This register is located in area 1 of physical space Therefore when the cache is on either acce...

Page 638: ...ction and the corresponding pin levels are read from bits PD7DT PD3DT PD1DT and PD0DT PDDR retains its previous value in standby mode and sleep mode and in a manual reset Note that the low level is read if bits 6 and 4 are read except in general purpose input Table 19 8 Port D Data Register PDDR Read Write Operations PDnMD1 PDnMD0 Pin State Read Write 0 0 Other function see table 18 1 PDDR value V...

Page 639: ...utput PTE0 input output TDO output Port E Figure 19 5 Port E 19 6 1 Register Description Table 19 9 summarizes the port E register Table 19 9 Port E Register Name Abbreviation R W Initial Value Address Access Size Port E data register PEDR R W H 00 H 04000128 H A4000128 8 Notes This register is located in area 1 of physical space Therefore when the cache is on either access this register from the ...

Page 640: ...ng pin level is read Table 19 10 shows the function of PEDR PEDR is initialized to H 00 by a power on reset after which the general input port function pull up MOS on is set as the initial pin function and the corresponding pin levels are read It retains its previous value in standby mode and sleep mode and in a manual reset Table 19 10 Port E Data Register PEDR Read Write Operations PEnMD1 PEnMD0...

Page 641: ...PINT9 input IRLS1 input PTF0 input PINT8 input IRLS0 input Port F Figure 19 6 Port F 19 7 1 Register Description Table 19 11 summarizes the port F register Table 19 11 Port F Register Name Abbreviation R W Initial Value Address Access Size Port F data register PFDR R H H 0400012A H A400012A 1 8 Notes This register is located in area 1 of physical space Therefore when the cache is on either access ...

Page 642: ...corresponding pin level is read Table 19 12 shows the function of PFDR PFDR is initialized by a power on reset after which the general input port function pull up MOS on is set as the initial pin function and the corresponding pin levels are read Table 19 12 Port F Data Register PFDR Read Write Operations PFnMD1 PFnMD0 Pin State Read Write 0 0 Other function see table 18 1 H 00 Ignored no effect o...

Page 643: ...TA1 input output PTG0 input AUDATA0 input output Port G Figure 19 7 Port G 19 8 1 Register Description Table 19 13 summarizes the port G register Table 19 13 Port G Register Name Abbreviation R W Initial Value Address Access Size Port G data register PGDR R W H H 0400012C H A400012C 1 8 Notes This register is located in area 1 of physical space Therefore when the cache is on either access this reg...

Page 644: ...corresponding pin level is read Table 19 14 shows the function of PGDR PGDR is initialized by a power on reset after which the general input port function pull up MOS on is set as the initial pin function and the corresponding pin levels are read Table 19 14 Port G Data Register PGDR Read Write Operations PGnMD1 PGnMD0 Pin State Read Write 0 0 Other function see table 18 1 H 00 Ignored no effect o...

Page 645: ...ut PTH0 input IRQ0 input Port H Figure 19 8 Port H 19 9 1 Register Description Table 19 15 summarizes the port H register Table 19 15 Port H Register Name Abbreviation R W Initial Value Address Access Size Port H data register PHDR R W or R B 0 H 0400012E H A400012E 1 8 Notes This register is located in area 1 of physical space Therefore when the cache is on either access this register from the P2...

Page 646: ...in function and the corresponding pin levels are read It retains its previous value in standby mode and sleep mode and in a manual reset Note that the low level is read if bits 6 to 0 are read except in general purpose input Table 19 16 Port H Data Register PHDR Read Write Operations PHnMD1 PHnMD0 Pin State Read Write 0 0 Other function see table 18 1 PHDR value Value is written to PHDR but does n...

Page 647: ...tput PTJ0 input output RAS3L output Port J Figure 19 9 Port J 19 10 1 Register Description Table 19 17 summarizes the port J register Table 19 17 Port J Register Name Abbreviation R W Initial Value Address Access Size Port J data register PJDR R W H 00 H 04000130 H A4000130 8 Notes This register is located in area 1 of physical space Therefore when the cache is on either access this register from ...

Page 648: ...nction is general input port if the port is read the corresponding pin level is read Table 19 18 shows the function of PJDR PJDR is initialized to H 00 by a power on reset It retains its previous value in software standby mode and sleep mode and in a manual reset Table 19 18 Port J Data Register PJDR Read Write Operations PJnMD1 PJnMD0 Pin State Read Write 0 0 Other function see table 18 1 PJDR va...

Page 649: ...ut output CS4 output PTK1 input output CS3 output PTK0 input output CS2 output Port K Figure 19 10 Port K 19 11 1 Register Description Table 19 19 summarizes the port K register Table 19 19 Port K Register Name Abbreviation R W Initial Value Address Access Size Port K data register PKDR R W H 00 H 04000132 H A4000132 8 Notes This register is located in area 1 of physical space Therefore when the c...

Page 650: ...he function is general input port if the port is read the corresponding pin level is read Table 19 20 shows the function of PKDR PKDR is initialized to H 00 by a power on reset It retains its previous value in standby mode and sleep mode and in a manual reset Table 19 20 Port K Data Register PKDR Read Write Operations PKnMD1 PKnMD0 Pin State Read Write 0 0 Other function see table 18 1 PKDR value ...

Page 651: ... 12 1 Register Description Table 19 21 summarizes the port L register Table 19 21 Port L Register Name Abbreviation R W Initial Value Address Access Size Port L data register PLDR R H 00 H 04000134 H A4000134 8 Notes This register is located in area 1 of physical space Therefore when the cache is on either access this register from the P2 area of logical space or else make an appropriate setting u...

Page 652: ...responding pin level is read Table 19 22 shows the function of PLDR PKDR is initialized to H 00 by power on reset It retains its previous value in software standby mode and sleep mode and in a manual reset The port L is also used as an analog pin therefore does not have a pull up MOS Table 19 22 Port L Data Register PLDR Read Write Operation PLnMD1 PLnMD0 Pin State Read Write 0 0 Other function se...

Page 653: ...t TxD1 output SCPT1 input output SCK0 input output SCPT0 input RxD0 input SCPT0 output TxD0 output SC Port Figure 19 12 SC Port 19 13 1 Register Description Table 19 23 summarizes the SC port register Table 19 23 SC Port Register Name Abbreviation R W Initial Value Address Access Size SC Port data register SCPDR R W or R B 0000000 H 04000136 H A4000136 1 8 Notes This register is located in area 1 ...

Page 654: ...the corresponding pin level is read Table 19 24 shows the function of SCPDR SCPDR is initialized to B 0000000 by a power on reset After initialization the general input port function pull up MOS on is set as the initial pin function and the corresponding pin levels are read from bits SCP7DT SCP5DT SCP3DT and SCP1DT SCPDR retains its previous value in standby mode and sleep mode and in a manual res...

Page 655: ...in 1 0 Input Pull up MOS on Pin state Value is written to SCPDR but does not affect pin state 1 Input Pull up MOS off Pin state Value is written to SCPDR but does not affect pin state n 0 to 6 SCPnMD1 SCPnMD0 Pin State Read Write 0 0 Other function see table 18 1 Low level Ignored no effect on pin state 1 Output Low level Ignored no effect on pin state 1 0 Input Pull up MOS on Pin state Ignored no...

Page 656: ...Rev 5 00 09 03 page 612 of 760 ...

Page 657: ...imum 15 µs per channel Pφ 33 MHz operation Three conversion modes Single mode A D conversion on one channel Multi mode A D conversion on one to four channels Scan mode Continuous A D conversion on one to four channels Four 16 bit data registers A D conversion results are transferred for storage into data registers corresponding to the channels Sample and hold function A D conversion can be externa...

Page 658: ...uccessive approxi mation register Comparator Sample and hold circuit ADI interrupt signal AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 φ 8 φ 16 ADCSR ADCR AVCC A D converter ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data register B ADDRC A D data register C ADDRD A D data register D Legend Internal data bus ADTRG ADDRC Figure 20 1 Block Diagram of A D ...

Page 659: ...able 20 1 A D Converter Pins Pin Name Abbreviation I O Function Analog power supply pin AVcc Input Analog power supply Analog ground pin AVss Input Analog ground and reference voltage Analog input pin 0 AN0 Input Group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Group1 analog inputs Analog input pin 5 AN5 Input...

Page 660: ...16 8 A D data register CL ADDRCL R H 00 H 0400008A H A400008A 2 8 A D data register DH ADDRDH R H 00 H 0400008C H A400008C 2 16 8 A D data register DL ADDRDL R H 00 H 0400008E H A400008E 2 8 A D control status register ADCSR R W 1 H 00 H 04000090 H A4000090 2 8 A D control register ADCR R W H 07 H 04000092 H A4000092 2 8 Notes These registers are located in area 1 of physical space Therefore when ...

Page 661: ...0 bit data which is transferred for storage into the A D data register corresponding to the selected channel The upper 8 bits of the result are stored in the upper byte bits 7 to 0 of the A D data register The lower 2 bits are stored in the lower byte bits 7 and 6 Bits 5 to 0 of an A D data register are reserved bits that are always read as 0 Table 20 3 indicates the pairings of analog input chann...

Page 662: ...Bit 7 ADF Description 0 Clearing conditions Initial value 1 Cleared by reading ADF while ADF 1 then writing 0 to ADF 2 Cleared when DMAC is activated by ADI interrupt and ADDR is read 1 Setting conditions 1 Single mode A D conversion ends 2 Multi mode A D conversion ends on all selected channels 3 Scan mode A D conversion ends on all selected channels Bit 6 A D Interrupt Enable ADIE Enables or dis...

Page 663: ...l selected channels 3 Scan mode A D conversion starts and continues cycling through the selected channels until ADST is cleared to 0 by software by a reset or by a transition to standby mode Bit 4 Multi Mode MULTI Selects single mode multi mode or scan mode For further information on operation in these modes see section 20 4 Operation Bit 4 MULTI ADCR Bit5 SCN Description 0 0 Single mode Initial v...

Page 664: ...nalog input channels Clear the ADST bit to 0 before changing the channel selection Channel Selection Description CH2 CH1 CH0 Single Mode MULTI 0 Multi Mode and Scan Mode MULTI 1 0 0 0 AN0 Initial value AN0 1 AN1 AN0 AN1 1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 1 0 0 AN4 AN4 1 AN5 AN4 AN5 1 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 ...

Page 665: ...nd TRGE0 bits should only be set when conversion is not in progress Bit 7 TRGE1 Bit 6 TRGE0 Description 0 0 0 1 A D conversion does not start when an external trigger is input Initial value 1 0 1 1 A D conversion starts at the falling edge of an input signal from the external trigger pin ADTRG Bit 5 Scan Mode SCN Selects multi mode or scan mode when the MULTI bit is set to 1 See the description of...

Page 666: ...is transferred into TEMP Next when the lower byte is read the TEMP contents are transferred to the bus master When reading an A D data register always read the upper byte before the lower byte It is possible to read only the upper byte but if only the lower byte is read the read value is not guaranteed Figure 20 2 shows the data flow for access to an A D data register See section 20 7 3 Access Siz...

Page 667: ...A D conversion After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the mode or channel is changed Typical operations when channel 1 AN1 is selected in single mode are described next Figure 20 3 shows a timing diagram for this example The ADCSR register specifies bits in the operation example 1 Single mode is selected MU...

Page 668: ...RC ADDRD Waiting Waiting Waiting Waiting Waiting Waiting A D conversion starts Set Set Set Clear Clear A D conversion result 1 A D conversion result 2 Read result Read result A D conversion 1 A D conversion result 2 Note Vertical arrows indicate instruction execution by software Figure 20 3 Example of A D Converter Operation Single Mode Channel 1 Selected ...

Page 669: ...n ADCSR to halt A D conversion After making the necessary changes set the ADST bit to 1 A D conversion will start again from the first channel in the group The ADST bit can be set at the same time as the mode or channel selection is changed Typical operations when three channels in group 0 AN0 to AN2 are selected in scan mode are described next Figure 20 4 shows a timing diagram for this example 1...

Page 670: ...ing Waiting Waiting Waiting Set Clear Clear A D conversion result 2 Waiting Waiting A D conversion result 3 A D conversion 1 Waiting A D conversion result 1 Transfer A D conversion 3 A D conversion A D conversion 2 Note Vertical arrows indicate instruction execution by software Figure 20 4 Example of A D Converter Operation Multi Mode Channels AN0 to AN2 Selected ...

Page 671: ...will start again from the first channel in the group The ADST bit can be set at the same time as the mode or channel selection is changed Typical operations when three channels AN0 to AN2 in group 0 are selected in scan mode are described next Figure 20 5 shows a timing diagram for this example 1 Scan mode is selected MULTI 1 SCN 1 channel group 0 is selected CH2 0 analog input channels AN0 to AN2...

Page 672: ...iting Transfer A D conversion 1 A D conversion 4 A D conversion 2 A D conversion 3 A D conversion result 1 A D conversion result 4 A D conversion result 2 A D conversion result 3 Clear 1 Clear 1 Set 1 Continuous A D conversion A D conversion 5 Notes 1 Vertical arrows indicate instruction execution by software 2 Data during conversion is ignored Figure 20 5 Example of A D Converter Operation Scan M...

Page 673: ...version time therefore varies within the ranges indicated in table 20 4 In multi mode and scan mode the conversion time values given in table 20 4 apply to the first conversion In the second and subsequent conversions the conversion time is fixed at 512 states when CKS 0 in ADCSR or 256 states when CKS 1 In both cases the CKS bit should be set according to the Pφ frequency so that the conversion t...

Page 674: ... Trigger Input Timing A D conversion can be externally triggered When the TRGE1 and TRGE0 bits are set to 1 in ADCR external trigger input is enabled at the ADTRG pin A high to low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR starting A D conversion Other operations regardless of the conversion mode are the same as if the ADST bit had been set to 1 by software Figure 20 7 shows the ...

Page 675: ...gure 20 8 In the figure the 10 bits of the A D converter have been simplified to 3 bits Offset error is the deviation between actual and ideal A D conversion characteristics when the digital output value changes from the minimum zero voltage 0000000000 000 in the figure to 000000001 001 in the figure figure 20 8 item 1 Full scale error is the deviation between actual and ideal A D conversion chara...

Page 676: ...alog Input Voltage Range During A D conversion the voltages input to the analog input pins ANn should be in the range AVSS ANn AVCC n 0 to 7 Relationships of AVCC and AVSS AVCC and AVSS should be related as follows AVCC VCC 0 3 V and AVSS VSS 20 7 2 Processing of Analog Input Pins To prevent damage from voltage surges at the analog input pins AN0 to AN7 connect an input protection circuit like the...

Page 677: ...dian modes The case is shown here in which H 3FF is obtained when AVCC is input as an analog input FF is the data containing the upper 8 bits of the conversion result and C0 is the data containing the lower 2 bits 0 01 µF 10 µF AVCC AN0 to AN7 AVSS SH7709S 100 Ω 0 1 µF Note Figure 20 9 Example of Analog Input Protection Circuit 1 0 kΩ AN0 to AN7 20 pF 1 MΩ Figure 20 10 Analog Input Pin Equivalent ...

Page 678: ...s MOV L ADDRAH R9 MOV B R9 R8 MOV L ADDRAL R9 MOV B R9 R8 FFFFFFFF C0C0C0C0 FFFFFFFF C0C0C0C0 FFFF C0C0 FFFF C0C0 FF C0 FF C0 Word access MOV L ADDRAH R9 MOV W R9 R8 MOV L ADDRAL R9 MOV W R9 R8 FFxxFFxx C0xxC0xx FFxxFFxx C0xxC0xx FFxx C0xx FFxx C0xx FF xx C0 xx xx FF xx C0 Longword access MOV L ADDRAH R9 MOV L R9 R8 FFxxC0xx FFxxC0xx Ffxx C0xx C0xx FFxx FF xx C0 xx xx C0 xx FF In this table ADDRAH...

Page 679: ...output channels Conversion time maximum 10 µs with 20 pF capacitive load Output voltage 0 V to AVcc 21 1 2 Block Diagram Figure 21 1 shows a block diagram of the D A converter AVCC DA0 DA1 DACR DADR0 DADR1 Module data bus Bus interface On chip data bus Control circuit Legend DACR D A control register DADR0 D A data register 0 DADR1 D A data register 1 8 bit D A AVSS Figure 21 1 Block Diagram D A C...

Page 680: ...the D A converter s registers Table 21 2 D A Converter Registers Name Abbreviation R W Initial Value Address 1 D A data register 0 DADR0 R W H 00 H 040000A0 H A40000A0 2 D A data register 1 DADR1 R W H 00 H 040000A2 H A40000A2 2 D A control register DACR R W H 1F H 040000A4 H A40000A4 2 Notes These registers are located in area 1 of physical space Therefore when the cache is on either access these...

Page 681: ... reset 21 2 2 D A Control Register DACR Bit 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE Initial value 0 0 0 1 1 1 1 1 R W R W R W R W R R R R R DACR is an 8 bit readable writable register that controls the operation of the D A converter DACR is initialized to H 1F by a reset Bit 7 D A Output Enable 1 DAOE1 Controls D A conversion and analog output Bit 7 DAOE1 Description 0 DA1 analog output is disabled Initia...

Page 682: ...tput Bit 7 DAOE1 Bit 6 DAOE0 Bit 5 DAE Description 0 0 D A conversion is disabled in channels 0 and 1 Initial value 0 1 0 D A conversion is enabled in channel 0 D A conversion is disabled in channel 1 0 1 1 D A conversion is enabled in channels 0 and 1 1 0 0 D A conversion is disabled in channel 0 D A conversion is enabled in channel 1 1 0 1 D A conversion is enabled in channels 0 and 1 1 1 D A co...

Page 683: ... D A conversion starts and DA0 becomes an output pin The converted result is output after the conversion time The output value is DADR0 contents 256 AVcc Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0 3 If the DADR0 value is modified conversion starts immediately and the result is output after the conversion time 4 When the DAOE0 bi...

Page 684: ...Rev 5 00 09 03 page 640 of 760 ...

Page 685: ...e UDI from the data input pin TDI and output from the data output pin TDO in synchronization with this clock TMS Mode select input pin The state of the TAP control circuit is determined by changing this signal in synchronization with TCK The protocol complies with the JTAG standard IEEE Std 1149 1 T T T TR R R RS S S ST T T T UDI reset input pin Input is accepted asynchronously with respect to TCK...

Page 686: ...S SE E E EB B B BR R R RKAK KAK KAK KAK Dedicated emulator pin 22 2 2 Block Diagram Figure 22 1 shows a block diagram of the UDI SDIR TCK TDO TDI TMS TRST SDBPR MUX SDBSR Shift register TAP controller Decoder Local bus Figure 22 1 Block Diagram of UDI 22 3 Register Descriptions The UDI has the following registers SDBPR Bypass register SDIR Instruction register SDBSR Boundary scan register ...

Page 687: ...t cannot be accessed by the CPU When SDIR is set to the bypass mode SDBPR is connected between UDI pins TDI and TDO 22 3 2 Instruction Register SDIR The instruction register SDIR is a 16 bit read only register The register is in bypass mode in its initial state It is initialized by TRST assertion or in the TAP test logic reset state and can be written to by the UDI irrespective of the CPU mode Ope...

Page 688: ...pass mode Initial value 0 0 0 1 Recovery from sleep Bits 11 to 0 Reserved These bits are always read as 1 22 3 3 Boundary Scan Register SDBSR The boundary scan register SDBSR is a shift register located on the PAD for controlling the input output pins of the SH7709S Using the EXTEST and SAMPLE PRELOAD commands a boundary scan test conforming to the JTAG standard can be carried out Table 22 3 shows...

Page 689: ...TA7 IN 299 IRQ4 PTH4 IN 329 D22 PTA6 IN 298 D31 PTB7 OUT 328 D21 PTA5 IN 297 D30 PTB6 OUT 327 D20 PTA4 IN 296 D29 PTB5 OUT 326 D19 PTA3 IN 295 D28 PTB4 OUT 325 D18 PTA2 IN 294 D27 PTB3 OUT 324 D17 PTA1 IN 293 D26 PTB2 OUT 323 D16 PTA0 IN 292 D25 PTB1 OUT 322 D15 IN 291 D24 PTB0 OUT 321 D14 IN 290 D23 PTA7 OUT 320 D13 IN 289 D22 PTA6 OUT 319 D12 IN 288 D21 PTA5 OUT 318 D11 IN 287 D20 PTA4 OUT 317 D...

Page 690: ...ontrol 264 D29 PTB5 Control 234 BS PTK4 IN 263 D28 PTB4 Control 233 WE2 DQMUL ICIORD PTK6 IN 262 D27 PTB3 Control 232 WE3 DQMUU ICIORD PTK7 IN 261 D26 PTB2 Control 231 AUDSYNC PTE7 IN 260 D25 PTB1 Control 230 CS2 PTK0 IN 259 D24 PTB0 Control 229 CS3 PTK1 IN 258 D23 PTA7 Control 228 CS4 PTK2 IN 257 D22 PTA6 Control 227 CS5 CE1A PTK3 IN 256 D21 PTA5 Control 226 CE2A PTE4 IN 255 D20 PTA4 Control 225 ...

Page 691: ... A6 Control 205 A19 OUT 175 A7 Control 204 A20 OUT 174 A8 Control 203 A21 OUT 173 A9 Control 202 A22 OUT 172 A10 Control 201 A23 OUT 171 A11 Control 200 A24 OUT 170 A12 Control 199 A25 OUT 169 A13 Control 198 BS PTK4 OUT 168 A14 Control 197 RD OUT 167 A15 Control 196 WE0 DQMLL OUT 166 A16 Control 195 WE1 DQMLU WE OUT 165 A17 Control 194 WE2 DQMUL ICIORD PTK6 OUT 164 A18 Control 193 WE3 DQMUU ICIOW...

Page 692: ...PTK0 Control 117 ADTRG PTH5 IN 146 CS3 PTK1 Control 116 IRLS3 PTF3 PINT11 IN 145 CS4 PTK2 Control 115 IRLS2 PTF2 PINT10 IN 144 CS5 CE1A PTK3 Control 114 IRLS1 PTF1 PINT9 IN 143 CS6 CE1B Control 113 IRLS0 PTF0 PINT8 IN 142 CE2A PTE4 Control 112 MD0 IN 141 CE2B PTE5 Control 111 CKE PTK5 OUT 140 CKE PTK5 IN 110 RAS3L PTJ0 OUT 139 RAS3L PTJ0 IN 109 PTJ1 OUT 138 PTJ1 IN 108 CASL PTJ2 OUT 137 CASL PTJ2 ...

Page 693: ...D5 Control 53 MCS4 PTC4 PINT4 IN 84 DACK1 PTD7 Control 52 MCS3 PTC3 PINT3 IN 83 PTE6 Control 51 MCS2 PTC2 PINT2 IN 82 PTE3 Control 50 MCS1 PTC1 PINT1 IN 81 RAS3U PTE2 Control 49 MCS0 PTC0 PINT0 IN 80 PTE1 Control 48 MD3 IN 79 BACK Control 47 MD4 IN 78 ASEBRKAK PTG5 Control 46 MD5 IN 77 AUDATA3 PTG3 Control 45 STATUS0 PTJ6 OUT 76 AUDATA2 PTG2 Control 44 STATUS1 PTJ7 OUT 75 AUDATA1 PTG1 Control 43 T...

Page 694: ...ontrol 26 MCS1 PTC1 PINT1 OUT 8 MCS4 PTC4 PINT4 Control 25 MCS0 PTC0 PINT0 OUT 7 WAKEUP PTD3 Control 24 DRAK0 PTD1 OUT 6 RESETOUT PTD2 Control 23 DRAK1 PTD0 OUT 5 MCS3 PTC3 PINT3 Control 22 STATUS0 PTJ6 Control 4 MCS2 PTC2 PINT2 Control 21 STATUS1 PTJ7 Control 3 MCS1 PTC1 PINT1 Control 20 TCLK PTH7 Control 2 MCS0 PTC0 PINT0 Control 19 IRQOUT Control 1 DRAK0 PTD1 Control 18 TxD0 SCPT0 Control 0 DRA...

Page 695: ...0 Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select IR scan 0 0 1 0 0 1 0 1 1 1 0 0 Figure 22 2 TAP Controller State Transitions Note The transition condition is the TMS value at the rising edge of TCK The TDI value is sampled at the rising edge of TCK shifting occurs at the falling edge of TCK The TDO value changes at the TCK falling edge The TDO is at high impedance except with shi...

Page 696: ...eset only High level Normal operation Notes 1 Selects main chip mode or ASE mode ASEMD0 H normal mode ASEMD0 L ASE mode Set ASEMD0 H when using on the user system alone without an emulator and the UDI 2 In ASE mode reset hold is enabled by driving the RESETP and TRST pins low for a constant cycle In this state the CPU does not start up even if RESETP is driven high When TRST is driven high UDI ope...

Page 697: ...nerates an interrupt by setting a command from the UDI in the SDIR An UDI interrupt is a general exception interrupt operation resulting in a branch to an address based on the VBR value plus offset and with return by the RTE instruction This interrupt request has a fixed priority level of 15 UDI interrupts are not accepted in sleep mode or standby mode 22 4 5 Bypass The JTAG based bypass mode for ...

Page 698: ... of a value to be transferred from an input pin to the internal circuitry or a value to be transferred from the internal circuitry to an output pin is latched into the boundary scan register and read from the scan path Snapshot latching is performed in synchronization with the rise of TCK in the Capture DR state Snapshot latching does not affect normal operation of this LSI In a PRELOAD operation ...

Page 699: ...ified in the CPG section Set pins MD 2 0 to the clock mode to be used After powering on wait for the CKIO clock to stabilize before performing a boundary scan test 5 Fix the RESETP pin low 6 Fix the CA pin high and the ASEMD0 pin low 22 6 Usage Notes 1 An UDI command other than an UDI interrupt once set will not be modified as long as another command is not re issued from the UDI An UDI interrupt ...

Page 700: ...Rev 5 00 09 03 page 656 of 760 ...

Page 701: ... chip in excess of the absolute maximum rating may result in permanent damage Order of turning on 1 7 V 1 8 V 1 9 V 2 0 V power Vcc Vcc PLL1 Vcc PLL2 Vcc RTC and 3 3 V power VccQ AVcc 1 First turn on the 3 3 V power then turn on the 1 7 V 1 8 V 1 9 V 2 0 V power within 1 ms This interval should be as short as possible 2 Until voltage is applied to all power supplies a low level is input at the RES...

Page 702: ...ND clock related and analog pins Power On Sequence Power off order 1 In the reverse order of powering on first turn off the 1 7 V 1 8 V 1 9 V 2 0 V power then turn off the 3 3 V power within 1 ms This interval should be as short as possible 2 Pin states are undefined while only the 1 7 V 1 8 V 1 9 V 2 0 V power is off The system design must ensure that these undefined states do not cause erroneous...

Page 703: ...el Vcc RTC 1 55 1 70 1 95 100 MHz model Icc 410 680 mA Vcc 2 0 V Iφ 200 MHz Current dissipation Normal operation 330 540 Vcc 1 9 V Iφ 167 MHz 250 410 Vcc 1 8 V Iφ 133 MHz 190 310 Vcc 1 7 V Iφ 100 MHz IccQ 20 40 VccQ 3 3 V Bφ 33 MHz Sleep mode 1 Icc 15 30 IccQ 10 20 1 When there is no other external bus cycle other than the refresh cycle Vcc 1 9 V VccQ 3 3 V Bφ 33MHz Standby mode Icc 40 120 µA IccQ...

Page 704: ...s Input high voltage RESETP RESETM NMI IRQ5 to IRQ0 MD5 to MD0 IRL3 to IRL0 IRLS3 to IRLS0 PINT15 to PINT0 ASEMD0 ADTRG TRST EXTAL CKIO RxD1 CA VIH VccQ 0 9 VccQ 0 3 V EXTAL2 When not connecting to a crystal oscillator connect to Vcc Port L 2 0 AVcc 0 3 Other input pins 2 0 VccQ 0 3 ...

Page 705: ...scillator connect to Vcc Port L 0 3 AVcc 0 2 Other input pins 0 3 VccQ 0 2 Input leak current All input pins I Iin I 1 0 µA Vin 0 5 to VccQ 0 5 V Three state leak current I O all output pins off condition I Isti I 1 0 µA Vin 0 5 to VccQ 0 5 V Output high voltage All output pins VOH 2 4 V VccQ 3 0 V IOH 200 µA 2 0 VccQ 3 0 V IOH 2 mA Output low voltage All output pins VOL 0 55 VccQ 3 6 V IOL 1 6 mA...

Page 706: ...s open Connect AVcc to VccQ and connect AVss to VssQ Current dissipation values shown are the values at which all output pins are without load under conditions of VIH min VccQ 0 5 V VIL max 0 5 V The same voltage should be supplied to Vcc Vcc RTC Vcc PLL1 and Vcc PLL2 If the IRL and IRLS interrupts are used the minimum is 1 9 V Table 23 3 Permitted Output Current Values VccQ 3 3 0 3 V Vcc 1 55 to ...

Page 707: ...rating Frequency Range VccQ 3 3 0 3 V VccQ 1 55 to 2 15 V AVcc 3 3 0 3 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Remarks CPU cache TLB f 30 200 MHz 200 MHz model Operating frequency 25 167 167 MHz model 133 133 MHz model 100 100 MHz model External bus 30 66 67 200 MHz model 25 167 MHz model 133 MHz model 100 MHz model Peripheral module 7 5 33 34 200 MHz model 6 25 167 MHz model 133 MHz model 10...

Page 708: ... fall time tCKIF 6 ns CKIO clock output frequency fOP 25 66 MHz 23 3 CKIO clock output cycle time tcyc 15 2 40 ns CKIO clock output low pulse width tCKOL 3 ns CKIO clock output high pulse width tCKOH 3 ns CKIO clock output rise time tCKOR 5 ns CKIO clock output fall time tCKOF 5 ns CKIO2 clock output delay time tCK2D 3 3 ns CKIO2 clock output rise time tCK20R 7 ns CKIO2 clock output fall time tCK2...

Page 709: ...e EXTAL pin Figure 23 1 EXTAL Clock Input Timing tCKIH tCKIF tCKIR tCKIL tCKIcyc VIH 1 2 VCCQ 1 2 VCCQ VIH VIL VIH VIL CKIO input Figure 23 2 CKIO Clock Input Timing tcyc tCKOL tCKOH VOH 1 2VCCQ CKIO output 1 2VCCQ tCKOR tCKOF VOH VOL VOL VOH tCK2D tCK2D VOH CKIO2 output tCK2OR tCK2OF VOH VOL VOL VOH Figure 23 3 CKIO Clock Output Timing ...

Page 710: ... time when built in oscillator is used Figure 23 4 Power on Oscillation Settling Time CKIO internal clock Stable oscillation Standby tOSC2 tRESPW MW tRESPS MS RESETP RESETM Note Oscillation settling time when built in oscillator is used in the oscillation off mode Figure 23 5 Oscillation Settling Time at Standby Return Return by Reset ...

Page 711: ...ation Settling Time at Standby Return Return by NMI CKIO internal clock Stable oscillation Standby tOSC4 IRL3 to IRL0 IRQ4 to IRQ0 PINT0 1 Note Oscillation settling time when built in oscillator is used in the oscillation off mode only when RTC is used WAKEUP Figure 23 7 Oscillation Settling Time at Standby Return Return by IRQ4 to IRQ0 PINT0 1 I I I IR R R RL L L L3 3 3 3 to I I I IR R R RL L L L...

Page 712: ...synchronization Figure 23 8 PLL Synchronization Settling Time during Standby Recovery Reset or NMI EXTAL input or CKIO input Stable input clock IRQ4 IRQ0 IRL3 IRL0 interrupt request Stable input clock Normal Normal PLL output CKIO output Internal clock STATUS 0 STATUS 1 Note PLL oscillation settling time during the continued oscillation mode or when clock is input from EXTAL pin or CKIO pin tPLL1 ...

Page 713: ...IO input CKIO output 2 PLL output Internal clock Multiplication rate modified tPLL2 Notes 1 CKIO input in clock mode 7 2 PLL output in other than clock mode 7 Figure 23 10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified ...

Page 714: ...US1 STATUS0 delay time tSTD 10 ns 23 15 Bus tri state delay time 1 tBOFF1 0 15 ns Bus tri state delay time 2 tBOFF2 0 15 ns Bus buffer on time 1 tBON1 0 15 ns Bus buffer on time 2 tBON2 0 15 ns Notes 1 RESETP NMI and IRQ5 to IRQ0 are asynchronous Changes are detected at the clock fall when the setup shown is used When the setup cannot be used detection can be delayed until the next clock falls 2 I...

Page 715: ...tRESPW MW Figure 23 11 Reset Input Timing CKIO RESETP RESETM tRESPH MH tRESPS MS VIH VIL NMI tNMIH tNMIS VIH VIL IRQ5 to IRQ0 tIRQH tIRQS VIH VIL Figure 23 12 Interrupt Signal Input Timing CKIO tIRQOD tIRQOD IRQOUT Figure 23 13 I I I IR R R RQOU QOU QOU QOUT T T T Timing ...

Page 716: ... tBACKD tBOFF2 tBOFF1 tBON1 tBACKD tBON2 tBREQH tBREQH tBREQS tBREQS MCSn Figure 23 14 Bus Release Timing CKIO tSTD tBOFF2 tBOFF1 tSTD tBON2 tBON1 Normal mode Standby mode Normal mode STATUS 0 STATUS 1 RD RD WR RAS CAS CSn WEn BS MCSn A25 to A0 D31 to D0 Figure 23 15 Pin Drive Timing at Standby ...

Page 717: ...23 16 23 21 23 40 23 46 Read data setup time 2 tRDS2 5 ns 23 22 23 25 23 30 23 33 Read data hold time 1 2 tRDH1 0 ns 23 16 23 21 23 40 23 46 Read data hold time 2 tRDH2 1 ns 23 22 23 25 23 30 23 33 Write enable delay time tWED 10 ns 23 16 23 18 23 40 23 41 Write data delay time 1 tWDD1 14 ns 23 16 23 18 23 40 23 41 23 44 23 46 Write data delay time 2 tWDD2 1 5 12 ns 23 26 23 29 23 34 23 36 Write d...

Page 718: ...setup time tIO16S 6 ns 23 45 23 46 IOIS16 hold time tIO16H 4 ns 23 45 23 46 DACK delay time 1 Reference for CKIO rise tDAKD1 10 ns 23 16 23 36 23 39 23 46 DACK delay time 2 Reference for CKIO fall tDAKD2 10 ns 23 16 23 22 Notes 1 Specified based on the slowest negate timing for CSn RD or WEn 2 Specified based on whichever negate timing is faster CSn or RD ...

Page 719: ... A25 to A0 CSn RD WR RD D31 to D0 read WEn D31 to D0 write BS T2 tAD tAH tAD tCSD1 tRWD tRSD tCSD2 tWED tWDD1 tRDS1 tBSD tBSD tDAKD1 tDAKD1 tRDH1 tRDH1 tWED tRSD tAH tRWH tRWD tWDH1 tRWH tRWH tAH tWDH3 DACKn read write tAS Figure 23 16 Basic Bus Cycle No Wait ...

Page 720: ...n RD WR RD D31 to D0 read WEn D31 to D0 write BS WAIT tAD tAD tRWD tRWH tAH tAH tRSD tCSD1 tWED tWDD1 tBSD tWTS tWTH tBSD tRDS1 tCSD2 tWED tRSD tRDH1 tRDH1 tRWD tAH tRWH tWDH3 tWDH1 tRWH tDAKD1 tDAKD1 DACKn read write tAS Figure 23 17 Basic Bus Cycle One Wait ...

Page 721: ...2 CKIO A25 to A0 CSn RD WR RD read D31 to D0 read WEn write D31 to D0 write BS WAIT tAD tAD tRWD tRSD tWED tWTS tWTH tBSD tBSD tRDS1 tWTS tWTH tCSD1 tCSD2 tRDH1 tRWH tAH tRWH tRWD tRWH tWDH3 tWDH1 tDAKD1 tDAKD2 DACKn tAS Figure 23 18 Basic Bus Cycle External Wait WAITSEL 1 ...

Page 722: ...AD tAD tAD tAD tCSD1 tRWD tBSD tBSD tAH tBSD tDAKD1 tDAKD2 tCSD2 tRSD tRDS1 tWTS tWTH tWTS tWTH tWTS tWTH tRDS tRSD T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 tRSD tRDH1 tRSD tAH tRDH1 tRWH tAH tRWH tRWD tRDH1 tBSD Note In the write cycle the basic bus cycle the basic bus cycle is performed Figure 23 19 Burst ROM Bus Cycle No Wait ...

Page 723: ... D31 to D0 Note In the write cycle the basic bus cycle is performed BS WAIT DACKn tAD tAD tAD tCSD1 tRWH tRWD tRSD tRSD tRDH1 tRDH1 tRDS1 tBSD tDAKD1 tDAKD2 tBSD tBSD tBSD tWTS tWTH tWTS tWTH T1 Tw Tw TB2 TB1 TB2 Tw T2 T2 tCSD2 tRDS1 tRDH1 tRSD tRWD tRWH Figure 23 20 Burst ROM Bus Cycle Two Waits ...

Page 724: ... TB1 T2 TBw tAD tAD tCSD1 tCSD2 tRWD tRWH tRDH1 tAH tAH tRWD tRSD tRSD1 tAH tAD tBSD tBSD tWTS tWTH tWTS tWTH tWTS tWTH tWTS tWTH tBSD tBSD tRDS1 tRDH1 tRSD tDAKD1 tDAKD2 tRDH1 tRWH tRSD1 tRDS Note In the write cycle the basic bus cycle is performed Figure 23 21 Burst ROM Bus Cycle External Wait WAITSEL 1 ...

Page 725: ... A16 A15 to A0 Tr tAD Row address Row address Read A command Row address Column address Tc1 Tc2 Tpc D31 to D0 tAD tAD tAD tAD tCSD3 tRWD tCSD3 tRWD tRASD2 tDQMD tDQMD tRDH2 tBSD tBSD High tRDS2 tRASD2 tCASD2 tCASD2 tAD tAD tAD DACKn tDAKD1 tDAKD1 Figure 23 22 Synchronous DRAM Read Bus Cycle RCD 0 CAS Latency 1 TPC 0 ...

Page 726: ...rw Trw Tc1 Tcw Td1 Tpc Tpc D31 to D0 Row address Row address Read A command Row address Column address tAD tAD tAD tAD tCSD3 tRWD tDQMD tRDH2 tBSD tBSD tRDS2 tCSD3 tRWD tRASD2 tDQMD tRASD2 tCASD2 tCASD2 tAD tAD tAD tAD DACKn tDAKD1 tDAKD1 Figure 23 23 Synchronous DRAM Read Bus Cycle RCD 2 CAS Latency 2 TPC 1 ...

Page 727: ...Tpc D31 to D0 Row address Row address Read A command Read command Row address Column address 1 4 tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRASD2 tDQMD tBSD tBSD tRDS2 tRDH2 tRDS2 tRDH2 tDQMD tRASD2 tCASD2 tCASD2 tDAKD1 tDAKD1 DACKn Figure 23 24 Synchronous DRAM Read Bus Cycle Burst Read Single Read 4 RCD 0 CAS Latency 1 TPC 1 ...

Page 728: ...c D31 to D0 read tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tRWD tDQMD tRDS2 tBSD tBSD tRDH2 tRDS2 tRDH2 tCSD3 tRWD tRASD2 tRASD2 tCASD2 tDQMD tCASD2 Row address Row address Row address Read command High Column address 1 4 tDAKD1 tDAKD1 DACKn Figure 23 25 Synchronous DRAM Read Bus Cycle Burst Read Single Read 4 RCD 1 CAS Latency 3 TPC 0 ...

Page 729: ...r Tc1 Trwl Tpc High D31 to D0 tAD Row address Row address Write A command Row address Column address tAD tAD tCSD3 tRWD tRASD2 tAD tAD tAD tAD tAD tCSD3 tRWD tRWD tRASD2 tCASD2 tDQMD tWDD2 tBSD tDQMD tWDH2 tBSD tCASD2 tDAKD1 tDAKD1 DACKn Figure 23 26 Synchronous DRAM Write Bus Cycle RCD 0 TPC 0 TRWL 0 ...

Page 730: ... Trwl Trwl Tpc Tpc High D31 to D0 tAD Row address Row address Write A command Row address Column address tAD tAD tAD tAD tAD tAD tCSD1 tRWD tRWD tAD tAD tAD tCSD1 tRWD tRASD2 tRASD2 tDQMD tWDD2 tBSD tCASD2 tDQMD tWDH2 tBSD tCASD2 tDAKD1 tDAKD1 DACKn Figure 23 27 Synchronous DRAM Write Bus Cycle RCD 2 TPC 1 TRWL 1 ...

Page 731: ... D31 to D0 tAD Row address Row address Write A command Write command Row address tAD tAD tAD tAD tCSD3 tRWD tRWD tAD tAD tAD tAD tCSD3 tRWD tRASD2 tRASD2 tDQMD tWDD2 tWDD2 tBSD tCASD2 tDQMD tWDH2 tBSD tCASD2 Column address 1 4 tDAKD1 tDAKD1 DACKn Figure 23 28 Synchronous DRAM Write Bus Cycle Burst Mode Single Write 4 RCD 0 TPC 1 TRWL 0 ...

Page 732: ... D31 to D0 Row address Row address Write A command Write command Row address Column address 1 4 tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD2 tDQMD tBSD tBSD tWDD2 tWDD2 tWDH2 tDQMD tRASD2 tCASD2 tCASD2 tDAKD1 tDAKD1 DACKn Figure 23 29 Synchronous DRAM Write Bus Cycle Burst Mode Single Write 4 RCD 1 TPC 0 TRWL 0 ...

Page 733: ...1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRASD2 tDQMD tDQMD tBSD tBSD High tAD tAD tAD tRDS2 tRDH2 tRDS2 tRDH2 tCASD2 tCASD2 tAD Row address Read command Column address tDAKD1 tDAKD1 DACKn Figure 23 30 Synchronous DRAM Burst Read Bus Cycle RAS Down Same Row Address CAS Latency 1 ...

Page 734: ...2 tRDS2 tBSD tRASD2 tCASD2 tDQMD tRWD tCSD3 tAD tAD tAD Tc1 Tc2 Tc3 Td1 Tc4 Td2 Td3 Td4 CKIO A12 or A10 A15 to A0 CSn RD WR RAS CAS DQMxx D31 to D0 BS CKE Row address DACKn tDAKD1 tDAKD1 Column address Read command Figure 23 31 Synchronous DRAM Burst Read Bus Cycle RAS Down Same Row Address CAS Latency 2 ...

Page 735: ...o D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD2 tRASD2 tDQMD tDQMD tDQMD tBSD tBSD tDAKD1 tDAKD1 High tAD tAD tAD tAD tAD tAD tRDS2 tRDH2 tRDS2 tRDH2 tAD Row address Read command Row address Row address Column address tCASD2 tCASD2 DACKn Figure 23 32 Synchronous DRAM Burst Read Bus Cycle RAS Down Different Row Address TPC 0 RCD 0 CAS Latency 1 ...

Page 736: ...tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD2 tRASD2 tRASD2 tRASD2 tDQMD tDQMD tDQMD tBSD tBSD High tAD tAD tAD tAD tAD tAD tRDS2 tRDH2 tRDS2 tRDH2 tAD Td4 Row address Read command Column address tCASD2 tCASD2 Row address Row address tDAKD1 tDAKD1 DACKn Figure 23 33 Synchronous DRAM Burst Read Bus Cycle RAS Down Different Row Address TPC 1 RCD 0 CAS Latency 1 ...

Page 737: ...6 A15 to A0 Tc1 Tc2 Tc3 Tc4 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRASD2 tRASD2 tDQMD tDQMD tWDD2 tWDD2 tBSD tBSD High tAD tAD tAD tCASD2 tCASD2 tAD Row address Write command Column address tDAKD1 tDAKD1 DACKn Figure 23 34 Synchronous DRAM Burst Write Bus Cycle RAS Down Same Row Address ...

Page 738: ...Tc3 Tc4 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRWD tRASD2 tRASD2 tDQMD tDQMD tDQMD tBSD tBSD High tAD tAD tAD tAD tAD tAD tAD Row address Write command Row address Row address Column address tCASD2 tCASD2 tDAKD1 tDAKD1 DACKn Figure 23 35 Synchronous DRAM Burst Write Bus Cycle RAS Down Different Row Address TPC 0 RCD 0 ...

Page 739: ... tAD tCSD3 tCSD3 tRWD tRWD tRWD tRWD tRASD2 tRASD2 tRASD2 tRASD2 tDQMD tDQMD tDQMD tWDD2 tWDD2 tBSD tBSD High tAD tAD tAD tAD tAD tAD Td4 Write command Column address tCASD2 tCASD2 Row address Row address tAD tAD Row address tDAKD1 tDAKD1 DACKn Figure 23 36 Synchronous DRAM Burst Write Bus Cycle RAS Down Different Row Address TPC 1 RCD 1 ...

Page 740: ...age 696 of 760 CKIO CSn RD WR CASxx CKE RAS3x Tp Tpc TRr TRrw TRrw Tpc Tpc tCSD3 tCSD3 tCSD3 tCSD3 tRASD2 tRASD2 tRASD2 tRASD2 tCASD2 tCASD2 tRWD tRWD High Figure 23 37 Synchronous DRAM Auto Refresh Timing TRAS 1 TPC 1 ...

Page 741: ...f 760 Tpc TRa1 TRs2 TRs2 TRs3 CKIO CKE CSn RAS CAS RD WR t RWD tRWD t CASD2 tRASD2 tCSD3 t CASD2 t CSD3 t RASD2 Tp tCSD3 tCSD3 tRASD2 tRASD2 Tpc Tpc tCKED tCKED tRWD Figure 23 38 Synchronous DRAM Self Refresh Cycle TRAS 1 TPC 1 ...

Page 742: ... D0 A13 or A11 A11 to A2 or A9 to A2 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 High CKE tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD2 tRASD2 tRASD2 tRASD2 tCASD2 tCASD2 tDAKD1 tDAKD1 DACKn Figure 23 39 Synchronous DRAM Mode Register Write Cycle ...

Page 743: ...pcm1 Tpcm2 CKIO A25 to A0 CExx RD WR RD D15 to D0 WE1 D15 to D0 BS DACKn tAD tAD tCSD1 tCSD1 tRWD tRSD tRSD tRWD tDAKD1 tDAKD1 tWED tWDD1 tWED tRDS1 tRDH1 tBSD tBSD tWDH4 tWDH1 read read write write Figure 23 40 PCMCIA Memory Bus Cycle TED 0 TEH 0 No Wait ...

Page 744: ... to A0 CExx RD WR RD read D15 to D0 read WE1 write D15 to D0 write BS DACKn WAIT tAD tCSD1 tRWD tAD tCSD1 tRWD tWDH4 tRSD tRSD tDAKD1 tDAKD1 tWED tWDD1 tWED tWDH1 tRDH1 tBSD tWTS tWTH tWTS tWTH tRDS1 tBSD Figure 23 41 PCMCIA Memory Bus Cycle TED 2 TEH 1 One Wait External Wait WAITSEL 1 ...

Page 745: ...WR RD D15 to D0 BS DACKn tAD tAD tCSD1 tRWD tCSD1 tRWD tAD tAD tAD tAD tDAKD1 tRSD tRSD tRDH1 tRDH1 tRSD tRSD tBSD tBSD tBSD tBSD tRDS1 tRDS1 Note Even though burst mode is set write cycle operation is the same as in normal mode read read tDAKD1 Figure 23 42 PCMCIA Memory Bus Cycle Burst Read TED 0 TEH 0 No Wait ...

Page 746: ...D15 to D0 read Note Even though burst mode is set the write cycle operation is the same as in normal mode BS DACKn WAIT tAD tAD tCSD1 tRWD tCSD1 tDAKD1 tRWD tAD tAD tAD tRSD tRSD tRSD tDAKD1 tBSD tBSD tBSD tBSD tRDH1 tRDH1 tRDS1 tWTS tWTH tWTS tWTS tWTH tWTH Figure 23 43 PCMCIA Memory Bus Cycle Burst Read TED 1 TEH 1 Two Waits Burst Pitch 3 WAITSEL 1 ...

Page 747: ...25 to A0 CExx RD WR ICIORD read D15 to D0 read ICIOWR write D15 to D0 write BS DACKn tAD tAD tCSD1 tCSD1 tRWD tICRSD tICRSD tRWD tDAKD1 tDAKD1 tICWSD tWDD1 tICWSD tRDH1 tRDS1 tBSD tBSD tWDH1 tWDH4 Figure 23 44 PCMCIA I O Bus Cycle TED 0 TEH 0 No Wait ...

Page 748: ...R ICIORD read D15 to D0 read ICIOWR write D15 to D0 write BS DACKn WAIT IOIS16 tAD tCSD1 tRWD tAD tCSD1 tRWD tICRSD tICRSD tDAKD1 tDAKD1 tICWSD tWDD1 tICWSD tWDH1 tWDH4 tRDH1 tWTS tWTH tWTS tWTH tIO16S tIO16H tRDS1 tBSD tBSD Figure 23 45 PCMCIA I O Bus Cycle TED 2 TEH 1 One Wait External Wait WAITSEL 1 ...

Page 749: ... BS WAIT IOIS16 DACKn tAD tAD tCSD1 tCSD1 tRWD tRWD tWDD1 tWDH4 tWDH4 tBSD tBSD tAD tAD tICRSD tICRSD tICRSD tICRSD tICWSD tWTS tWTH tWTH tIO16S tIO16H tAD tRDS1 tCSD1 tDAKD1 tDAKD1 tRDS1 tICWSD tICWSD tICWSD tRDH1 tRDH1 tWDD1 tWDH1 tBSD tBSD tWTS read read write write Figure 23 46 PCMCIA I O Bus Cycle TED 1 TEH 1 One Wait Bus Sizing WAITSEL 1 ...

Page 750: ...se time tSCKR 1 5 23 50 Input clock fall time tSCKF 1 5 Input clock pulse width tSCKW 0 4 0 6 tscyc Transmission data delay time tTXD 100 ns 23 51 Receive data setup time clock synchronization tRXS 100 Receive data hold time clock synchronization tRXH 100 RTS delay time tRTSD 100 CTS setup time clock synchronization tCTSS 100 CTS hold time clock synchronization tCTSH 100 Port Output data delay tim...

Page 751: ...ng tTCKS tTCKS tTCKWH tTCKWL CKIO TCLK input Figure 23 48 TCLK Clock Input Timing RTC crystal oscillator Stable oscillation VCC VCCmin tROSC Figure 23 49 Oscillation Settling Time at RTC Crystal Oscillator Power on tSCKW SCK input tSCKR tSCKF tSCYC Figure 23 50 SCK Input Clock Timing ...

Page 752: ... SCI I O Timing in Clock Synchronous Mode tPORTS1 CKIO PORT 7 to 0 read B P clock ratio 1 1 PORT 7 to 0 read B P clock ratio 4 1 tPORTH1 tPORTS2 PORT 7 to 0 read B P clock ratio 2 1 tPORTH2 tPORTS3 tPORTH3 PORT 7 to 0 write tPORTD Figure 23 52 I O Port Timing DREQn CKIO tDREQS tDREQH Figure 23 53 D D D DR R R RE E E EQ Q Q Q Input Timing ...

Page 753: ...ulse width tTCKH 12 ns TCK low pulse width tTCKL 12 ns TCK rise fall time tTCKf 4 ns TRST setup time tTRSTS 12 ns 23 56 TRST hold time tTRSTH 50 tcyc TDI setup time tTDIS 10 ns 23 57 TDI hold time tTDIH 10 ns TMS setup time tTMSS 10 ns TMS hold time tTMSH 10 ns TDO delay time tTDOD 16 ns ASEMD0 setup time tASEMDH 12 ns 23 58 ASEMD0 hold time tASEMDS 12 ns tTCKL tTCKf VIL VIL VIH VIH VIH 1 2VccQ 1 ...

Page 754: ...Figure 23 56 T T T TR R R RS S S ST T T T Input Timing Reset Hold TCK TDI TMS tTDIS tTMSS tTDIH tTCKCYC tTMSH tTDOD TDO Figure 23 57 UDI Data Transfer Timing tASEMD0S tASEMD0H RESETP ASEMD0 Figure 23 58 A A A AS S S SE E E EM M M MD D D D0 0 0 0 Input Timing ...

Page 755: ...0 ADTRG PINT15 to PINT0 TRST RxD1 CA NMI IRQ5 IRQ0 CKIO and MD5 MD0 are within Vss to Vcc Input rise and fall times 1 ns IOL IOH CL VREF LSI output pin DUT output Notes CL is the total value that includes the capacitance of measurement instruments etc and is set as follows for each pin 30pF CKIO RAS CAS CS0 CS2 CS6 CE2A CE2B BACK 50pF All other pins IOL and IOH are the values shown in table 23 3 1...

Page 756: ...ed to this LSI s pins is shown below The graph shown in figure 23 60 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device If the connected load capacitance exceeds the range shown in figure 23 60 the graph will not be a straight line 3 2 1 0 0 10 20 30 40 50 Load Capacitance pF Delay Time ns Figure 23 60 Load Capacitanc...

Page 757: ...rmissible signal source single source impedance 5 kΩ Nonlinearity error 3 0 LSB Offset error 2 0 LSB Full scale error 2 0 LSB Quantization error 0 5 LSB Absolute accuracy 4 0 LSB 23 5 D A Converter Characteristics Table 23 11 lists the D A converter characteristics Table 23 11 D A Converter Characteristics VccQ 3 3 0 3 V Vcc 1 55 to 2 15 V AVcc 3 3 0 3 V Ta 20 to 75 C Item Min Typ Max Unit Test Co...

Page 758: ...Rev 5 00 09 03 page 714 of 760 ...

Page 759: ...1 O 1 O 1 CKIO IO 1 IO 1 IO 1 IO 1 IO 1 EXTAL2 I I I I I XTAL2 O O O O O Clock CAP1 CAP2 RESETP I I I I I RESETM I I I I I BREQ I I I I I BACK O O O O L MD 5 0 I I I I I CA I I I I I System control STATUS 1 0 PTJ 7 6 O OP 2 OP 2 OP 2 OP 2 IRQ 3 0 IRL 3 0 PTH 3 0 V 7 I I I I IRQ 4 PTH 4 V 7 I I I I NMI I I I I I IRLS 3 0 PTF 3 0 PINT 11 8 V I IZ I I MCS 7 0 PTC 7 0 PINT 7 0 V OP 2 ZH 10 K 2 OP 2 ZP...

Page 760: ...L PTJ 0 H OP 2 ZOK 3 OP 2 ZOP 3 RAS3U PTE 2 V OP 2 ZOK 3 OP 2 ZOP 3 CASL PTJ 2 H OP 2 ZOK 3 OP 2 ZOP 3 CASU PTJ 3 H OP 2 ZOK 3 OP 2 ZOP 3 WE0 DQMLL H O ZH 10 O Z WE1 DQMLU WE H O ZH 10 O Z WE2 DQMUL ICIORD PTK 6 H OP 2 ZH 10 K 2 OP 2 ZP 2 WE3 DQMUU ICIOWR PTK 7 H OP 2 ZH 10 K 2 OP 2 ZP 2 RD WR H O ZH 10 O Z RD H O ZH 10 O Z CKE PTK 5 H OP 2 OK 2 OP 2 OP 2 Bus control WAIT Z I Z I Z DREQ0 PTD 4 V Z...

Page 761: ...T 6 V OP 2 ZK 2 OP 2 OP 2 SCIF with FIFO CTS2 IRQ5 SCPT 7 V 7 ZI 6 I I I AUDSYNC PTE 7 OV OP 2 OK 2 OP 2 OP 2 CE2B PTE 5 V OP 2 ZH 10 K 2 OP 2 ZP 2 CE2A PTE 4 V OP 2 ZH 10 K 2 OP 2 ZP 2 TDO PTE 0 OV OP 2 OK 2 OP 2 OP 2 IOIS16 PTG 7 V I Z I I PTG 5 0 V I Z I I AUDCK PHT 6 V I Z I I ADTRG PTH 5 V 7 I IZ I I WAKEUP PTD 3 V OP 2 OK 2 OP 2 ZP 2 RESETOUT PTD 2 O OP 2 ZK 2 OP 2 OP 2 AUDATA 3 0 PTG 3 0 OV...

Page 762: ... MD0 setting 2 K or P when the port function is used 3 K or P when the port function is used Z or O when the port function is not used depending on register setting 4 K or P when the port function is used I or O when the port function is not used depending on register setting 5 Depending on register setting 6 I or O when the port function is used 7 Input Schmitt buffers of IRQ 5 0 and ADTRG on oth...

Page 763: ...T 0 171 B13 I Serial port 0 data input input port RXD1 SCPT 2 172 C13 I Serial port 1 data input input port RXD2 SCPT 4 174 B12 I Serial port 2 data input input port TXD0 SCPT 0 164 C15 O Serial port 0 data output output port TXD1 SCPT 2 166 A14 O Serial port 1 data output output port TXD2 SCPT 4 168 C14 O Serial port 2 data output output port SCK0 SCPT 1 165 D15 I O Serial port 0 clock input outp...

Page 764: ... 177 to 180 185 to 188 B11 D11 C11 B10 D9 B9 A9 D8 I O Mask ROM chip select I O port port interrupt request WAKEUP PTD 3 182 D10 I O Wakeup I O port RESETOUT PTD 2 184 C9 I O Reset output I O port DRAK0 PTD 1 189 C8 I O DMA control pin I O port DRAK1 PTD 0 190 B8 I O DMA control pin I O port DREQ0 PTD 4 191 A8 I DMA transfer request 0 input port DREQ1 PTD 6 192 D7 I DMA transfer request 1 input po...

Page 765: ...M WE1 DQMLU WE 90 V13 O D15 D8 select signal DQM SDRAM PCMCIA WE signal WE2 DQMUL ICIORD PTK 6 91 W13 I O D23 D16 select signal DQM SDRAM PCMCIA IORD signal I O port WE3 DQMUU ICIOWR PTK 7 92 T14 I O D31 D24 select signal DQM SDRAM PCMCIA IOWR signal I O port RD WR 93 U14 O Read write select signal AUDSYNC PTE 7 94 V14 I O AUD synchronous I O port PTE 6 116 P18 I O I O port PTE 3 117 P17 I O I O p...

Page 766: ...0 to 143 H19 G16 G17 G18 I External interrupt request input port port interrupt request AUDCK PTH 6 151 D16 I AUD clock input port WAIT 123 M19 I Hardware wait request BREQ 122 N16 I Bus request BACK 121 N17 O Bus acknowledge IRQOUT 160 A16 O Interrupt refresh request output RESETP 193 C7 I Power on reset input NMI 7 C3 I Nonmaskable interrupt request IRQ 3 0 IRL 3 0 PTH 3 0 11 to 8 F2 F1 E4 E3 I ...

Page 767: ...pply 2 0 1 9 1 8 1 7 V AVCC 205 A4 Power supply Analog power supply 3 3 V VSSQ 19 33 45 57 69 83 95 109 161 181 H2 M3 R3 T7 U4 W11 W14 T19 C16 C10 Power supply Power supply 0 V VCC 29 81 134 154 175 L3 L4 U11 T11 J17 J16 E18 C19 C12 D12 Power supply Internal power supply 2 0 1 9 1 8 1 7 V VSS 27 79 132 152 153 173 K3 K4 U10 T10 K17 K16 E19 D17 D19 A12 D13 Power supply Internal power supply 0 V VSS...

Page 768: ... Power supply 0 V When PLL2 is not used CAP2 Leave unconnected VCC PLL2 Power supply 2 0 1 9 1 8 1 7 V VSS PLL2 Power supply 0 V When on chip crystal oscillator is not used XTAL Leave unconnected When EXTAL pin is not used EXTAL Pull up 3 3 V When A D converter is not used AN 7 0 Leave unconnected AVCC Power supply 3 3 V AVSS Power supply 0 V When UDI is not used ASEMD0 Pull up 3 3 V ...

Page 769: ...ASL PTJ 2 High High High High CASU PTJ 3 High High High High R High High High High WE0 DQMLL W Low Low High Low R High High High High WE1 DQMLU WE W High High Low Low R High High High High WE2 DQMUL ICIORD PTK 6 W High High High High R High High High High WE3 DQMUU ICIOWR PTK 7 W High High High High CE2A PTE 4 High High High High CE2B PTE 5 High High High High CKE PTK 5 Disabled Disabled Disabled ...

Page 770: ...igh High High High WE2 DQMUL ICIORD PTK 6 W High High Low High High Low Low R High High High High High High High WE3 DQMUU ICIOWR PTK 7 W High High High Low High Low Low CE2A PTE 4 High High High High High High High CE2B PTE 5 High High High High High High High CKE PTK 5 Disabled Disabled Disabled Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 ...

Page 771: ...High CASU PTJ 3 High High High High R High High High High WE0 DQMLL W Low High Low Low R High High High High WE1 DQMLU WE W High Low High Low R High High High High WE2 DQMUL ICIORD PTK 6 W High High High High R High High High High WE3 DQMUU ICIOWR PTK 7 W High High High High CE2A PTE 4 High High High High CE2B PTE 5 High High High High CKE PTK 5 Disabled Disabled Disabled Disabled WAIT Enabled 1 E...

Page 772: ...igh High High High WE2 DQMUL ICIORD PTK 6 W High Low High High Low High Low R High High High High High High High WE3 DQMUU ICIOWR PTK 7 W Low High High High Low High Low CE2A PTE 4 High High High High High High High CE2B PTE 5 High High High High High High High CKE PTK 5 Disabled Disabled Disabled Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 ...

Page 773: ... 2 High High High High CASU PTJ 3 High High High High R High High High High WE0 DQMLL W R High High High High WE1 DQMLU WE W R High High High High WE2 DQMUL ICIORD PTK 6 W R High High High High WE3 DQMUU ICIOWR PTK 7 W CE2A PTE 4 High High High High CE2B PTE 5 High High High High CKE PTK 5 Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 IOIS16 PTG 7 Disabled Disabl...

Page 774: ...ORD PTK 6 W R High High High High High High High WE3 DQMUU ICIOWR PTK 7 W CE2A PTE 4 High High High High High High High CE2B PTE 5 High High High High High High High CKE PTK 5 Disabled Disabled Disabled Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 IOIS16 PTG 7 Disabled Disabled Disabled Disabled Disabled Disabled Disabled A25 to A0 ...

Page 775: ... High High High High CASU PTJ 3 High High High High R High High High High WE0 DQMLL W R High High High High WE1 DQMLU WE W R High High High High WE2 DQMUL ICIORD PTK 6 W R High High High High WE3 DQMUU ICIOWR PTK 7 W CE2A PTE 4 High High High High CE2B PTE 5 High High High High CKE PTK 5 Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 IOIS16 PTG 7 Disabled Disabled...

Page 776: ...ORD PTK 6 W R High High High High High High High WE3 DQMUU ICIOWR PTK 7 W CE2A PTE 4 High High High High High High High CE2B PTE 5 High High High High High High High CKE PTK 5 Disabled Disabled Disabled Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 IOIS16 PTG 7 Disabled Disabled Disabled Disabled Disabled Disabled Disabled A25 to A0 ...

Page 777: ...E1 DQMLU WE W High Low High High Low High Low R High High Low High High Low Low WE2 DQMUL ICIORD PTK 6 W High High Low High High Low Low R High High High Low High Low Low WE3 DQMUU ICIOWR PTK 7 W High High High Low High Low Low CE2A PTE 4 High High High High High High High CE2B PTE 5 High High High High High High High CKE PTK 5 High 2 High 2 High 2 High 2 High 2 High 2 High 2 WAIT Disabled Disable...

Page 778: ...1 DQMLU WE W High High Low High High Low Low R High Low High High Low High Low WE2 DQMUL ICIORD PTK 6 W High Low High High Low High Low R Low High High High Low High Low WE3 DQMUU ICIOWR PTK 7 W Low High High High Low High Low CE2A PTE 4 High High High High High High High CE2B PTE 5 High High High High High High High CKE PTK 5 High 2 High 2 High 2 High 2 High 2 High 2 High 2 WAIT Disabled Disabled...

Page 779: ...gh High R High High High High High High High High WE0 DQMLL W High High High High High High High High R High High High High High High High High WE1 DQMLU WE W Low Low Low Low High High High High R High High High High Low Low Low Low WE2 DQMUL ICIORD PTK 6 W High High High High High High High High R High High High High High High High High WE3 DQMUU ICIOWR PTK 7 W High High High High Low Low Low Low...

Page 780: ...gh High High High R High High High High High High High High WE1 DQMLU WE W Low Low Low Low High High High High R High High High High Low Low Low Low WE2 DQMUL ICIORD PTK 6 W High High High High High High High High R High High High High High High High High WE3 DQMUU ICIOWR PTK 7 W High High High High Low Low Low Low CE2A PTE 4 High High High High High High High High CE2B PTE 5 High High Low Low Hig...

Page 781: ... High R High High High High High High High High WE0 DQMLL W High High High High High High High High R High High High High High High High High WE1 DQMLU WE W Low Low Low Low High High High High R High High High High Low Low Low Low WE2 DQMUL ICIORD PTK 6 W High High High High High High High High R High High High High High High High High WE3 DQMUU ICIOWR PTK 7 W High High High High Low Low Low Low C...

Page 782: ...gh High High High R High High High High High High High High WE1 DQMLU WE W Low Low Low Low High High High High R High High High High Low Low Low Low WE2 DQMUL ICIORD PTK 6 W High High High High High High High High R High High High High High High High High WE3 DQMUU ICIOWR PTK 7 W High High High High Low Low Low Low CE2A PTE 4 High High High High High High High High CE2B PTE 5 High High Low Low Hig...

Page 783: ...RB CCN L FFFFFFE8 32 32 CCR CCN L FFFFFFEC 32 32 CCR2 CCN I 40000B0 32 32 TRA CCN L FFFFFFD0 32 32 EXPEVT CCN L FFFFFFD4 32 32 INTEVT CCN L FFFFFFD8 32 32 BARA UBC L FFFFFFB0 32 32 BAMRA UBC L FFFFFFB4 32 32 BBRA UBC L FFFFFFB8 16 16 BARB UBC L FFFFFFA0 32 32 BAMRB UBC L FFFFFFA4 32 32 BBRB UBC L FFFFFFA8 16 16 BDRB UBC L FFFFFF90 32 32 BDMRB UBC L FFFFFF94 32 32 BRCR UBC L FFFFFF98 16 16 BETR UBC...

Page 784: ...CR BSC I FFFFFF74 16 16 SDMR BSC I FFFFD000 FFFFEFFF 8 MCSCR0 BSC I FFFFFF50 16 16 MCSCR1 BSC I FFFFFF52 16 16 MCSCR2 BSC I FFFFFF54 16 16 MCSCR3 BSC I FFFFFF56 16 16 MCSCR4 BSC I FFFFFF58 16 16 MCSCR5 BSC I FFFFFF5A 16 16 MCSCR6 BSC I FFFFFF5C 16 16 MCSCR7 BSC I FFFFFF5E 16 16 R64CNT RTC P FFFFFEC0 8 8 RSECCNT RTC P FFFFFEC2 8 8 RMINCNT RTC P FFFFFEC4 8 8 RHRCNT RTC P FFFFFEC6 8 8 RWKCNT RTC P FF...

Page 785: ...2 8 8 TCOR0 TMU P FFFFFE94 32 32 TCNT0 TMU P FFFFFE98 32 32 TCR0 TMU P FFFFFE9C 16 16 TCOR1 TMU P FFFFFEA0 32 32 TCNT1 TMU P FFFFFEA4 32 32 TCR1 TMU P FFFFFEA8 16 16 TCOR2 TMU P FFFFFEAC 32 32 TCNT2 TMU P FFFFFEB0 32 32 TCR2 TMU P FFFFFEB4 16 16 TCPR2 TMU P FFFFFEB8 32 32 SCSMR SCI P FFFFFE80 8 8 SCBRR SCI P FFFFFE82 8 8 SCSCR SCI P FFFFFE84 8 8 SCTDR SCI P FFFFFE86 8 8 SCSSR SCI P FFFFFE88 8 8 SC...

Page 786: ...2 16 32 DMATCR1 DMAC P 4000038 32 16 32 CHCR1 DMAC P 400003C 32 8 16 32 SAR2 DMAC P 4000040 32 16 32 DAR2 DMAC P 4000044 32 16 32 DMATCR2 DMAC P 4000048 32 16 32 CHCR2 DMAC P 400004C 32 8 16 32 SAR3 DMAC P 4000050 32 16 32 DAR3 DMAC P 4000054 32 16 32 DMATCR3 DMAC P 4000058 32 16 32 CHCR3 DMAC P 400005C 32 8 16 32 DMAOR DMAC P 4000060 16 8 16 CMSTR CMT P 4000070 16 8 16 32 CMCSR CMT P 4000072 16 8...

Page 787: ... PBCR PORT P 4000102 16 16 PCCR PORT P 4000104 16 16 PDCR PORT P 4000106 16 16 PECR PORT P 4000108 16 16 PFCR PORT P 400010A 16 16 PGCR PORT P 400010C 16 16 PHCR PORT P 400010E 16 16 PJCR PORT P 4000110 16 16 PKCR PORT P 4000112 16 16 PLCR PORT P 4000114 16 16 SCPCR PORT P 4000116 16 16 PADR PORT P 4000120 8 8 PBDR PORT P 4000122 8 8 PCDR PORT P 4000124 8 8 PDDR PORT P 4000126 8 8 PEDR PORT P 4000...

Page 788: ...lock pulse generator BSC Bus state controller RTC Realtime clock INTC Interrupt controller TMU Timer unit SCI Serial communication interface 2 Internal buses L CPU CCN cache TLB connected I BSC cache DMAC INTC CPG and UDI connected P BSC and peripheral modules RTC TMU SCI SCIF IrDA A D D A DMAC PORT CMT connected 3 The access size shown is for control register access read write An incorrect result...

Page 789: ...Module SDMR BSC SCSMR C A CHR PE O E STOP MP CKS1 CKS0 SCI SCBRR SCI SCSCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI SCTDR SCI SCSSR TDRE RDRF ORER FER PER TEND MPB MPBT SCI SCRDR SCI SCSCMR SDIR SINV SMIF SCI TOCR TCOE TMU TSTR STR2 STR1 STR0 TMU TCOR0 TMU TCNT0 TMU UNF TCR0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMU TCOR1 TMU TCNT1 TMU ...

Page 790: ...C0 TMU TCPR2 TMU R64CNT 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz RTC RSECCNT 10 sec 1 sec RTC RMINCNT 10 min 1 min RTC RHRCNT 10 hours 1 hour RTC RWKCNT Day of week RTC RDAYCNT 10 days 1 day RTC RMONCNT 10 months 1 month RTC RYRCNT 10 years 1 year RTC RSECAR ENB 10 sec 1 sec RTC RMINAR ENB 10 min 1 min RTC RWKAR ENB Day of week RTC RHRAR ENB 10 hours 1 hour RTC RDAYAR ENB 10 days 1 day RTC RMONAR ENB...

Page 791: ...P1 DRAMTP0 A5PCM A6PCM BSC A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 BCR2 A3SZ1 A3SZ0 A2SZ1 A2SZ0 BSC WAITSEL A6IW1 A6IW0 A5IW1 A5IW0 A4IW1 A4IW0 WCR1 A3IW1 A3IW0 A2IW1 A2IW0 A0IW1 A0IW0 BSC A6W2 A6W1 A6W0 A5W2 A5W1 A5W0 A4W2 A4W1 WCR2 A4W0 A3W1 A3W0 A2W1 A2W0 A0W2 A0W1 A0W0 BSC TPC1 TPC0 RCD1 RCD0 TRWL1 TRWL0 TRAS1 TRAS0 MCR RASD AMX3 AMX2 AMX1 AMX0 RFSH RMODE BSC A6W3 A5W3 A5TED2 A6TED2 A5TEH2 A6TEH2 ...

Page 792: ... IFC0 PFC1 PFC0 CPG STBCR STBY STBXTL MSTP2 MSTP1 MSTP0 CPG STBCR2 MSTP9 MDCHG MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 CPG WTCNT CPG WTCSR TME WT IT RSTS WOVF IOVF CKS2 CKS1 CKS0 CPG BDRB UBC BDMRB UBC BASMA BASMB SCMFCA SCMFCB SCMFDA SCMFDB PCTE PCBA BRCR DBEB PCBB SEQ ETBE UBC BARB UBC BAMRB BASM BAM BAM UBC BBRB CDB1 CDB0 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0 UBC BARA UBC ...

Page 793: ...BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BRSR BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 UBC DVF BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BRDR BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 UBC TRA CCN EXPEVT CCN INTEVT CCN SV MMUCR RC RC TF IX AT CCN ...

Page 794: ... 750 of 760 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BASRA UBC BASRB UBC CCR 0 0 CF CB WT CE CCN W3LOAD W3LOCK CDR2 W2LOAD W2LOCK CCN PTEH CCN V PTEL PR PR SZ C D SH CCN TTB CCN TEA CCN INTEVT2 INTC ...

Page 795: ...0S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S INTC PINT15S PINT14S PINT13S PINT12S PINT11S PINT10S PINT9S PINT8S ICR2 PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S INTC PINT15E PINT14E PINT13E PINT12E PINT11E PINT10E PINT9E PINT8E PINTER PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E INTC IRQ3 level IRQ2 level IPRC IRQ1 level IRQ0 level INTC PINT0 to 7 level PINT8 to 15 level IPR...

Page 796: ...t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 CHCR0 DS TM TS1 TS0 IE TE DE DMAC SAR1 DMAC DAR1 DMAC DMATCR1 DMAC RL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 DMAC CHCR1 DS TM TS1 TS0 IE TE DE SAR2 DMAC DAR2 DMAC DMATCR2 DMAC ...

Page 797: ... SM1 SM0 RS3 RS2 RS1 RS0 CHCR2 TM TS1 TS0 IE TE DE DMAC SAR3 DMAC DAR3 DMAC DMATCR3 DMAC DI DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 CHCR3 TM TS1 TS0 IE TE DE DMAC PR1 PR0 DMAOR AE NMIF DME DMAC CMSTR STR CMT CMCSR CMF CKS1 CKS0 CMT CMCNT CMT CMCOR CMT ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A DC ADDRAL AD1 AD0 A DC ...

Page 798: ...A1M D1 PA1M D0 PA0M D1 PA0M D0 PORT PB7M D1 PB7M D0 PB6M D1 PB6M D0 PB5M D1 PB5M D0 PB4M D1 PB4M D0 PBCR PB3M D1 PB3M D0 PB2M D1 PB2M D0 PB1M D1 PB1M D0 PB0M D1 PB0M D0 PORT PC7M D1 PC7M D0 PC6M D1 PC6M D0 PC5M D1 PC5M D0 PC4M D1 PC4M D0 PCDR PC3M D1 PC3M D0 PC2M D1 PC2M D0 PC1M D1 PC1M D0 PC0M D1 PC0M D0 PORT PD7M D1 PD7M D0 PD6M D1 PD6M D0 PD5M D1 PD5M D0 PD4M D1 PD4M D0 PDCR PD3M D1 PD3M D0 PD2...

Page 799: ...D1 PL3M D0 PL2M D1 PL2M D0 PL1M D1 PL1M D0 PL0M D1 PL0M D0 PORT SCP7M D1 SCP7M D0 SCP6M D1 SCP6M D0 SCP5M D1 SCP5M D0 SCP4M D1 SCP4M D0 SCPCR SCP3M D1 SCP3M D0 SCP2M D1 SCP2M D0 SCP1M D1 SCP1M D0 SCP0M D1 SCP0M D0 PORT PADR PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT PORT PBDR PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT PORT PCDR PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT PORT PDDR PD...

Page 800: ...CKE0 SCIF SCFTDR2 SCIF PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 SCSSR2 ER TEND TDFE BRK FER PER RDF DR SCIF SCFRDR2 SCIF SCFCR2 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP SCIF T4 T3 T2 T1 T0 SCFDR2 R4 R3 R2 R1 R0 SCIF Legend MMU Memory management unit UBC User break controller CPG Clock pulse generator BSC Bus state controller RTC Realtime clock INTC Interrupt controller TMU Timer unit SC1 Serial...

Page 801: ...6417709SHF200B 208 pin plastic HQFP FP 208E HD6417709SF167B 208 pin plastic LQFP FP 208C 1 9 0 15 V 167 MHz HD6417709SBP167B 240 pin CSP BP 240A HD6417709SF133B 208 pin plastic LQFP FP 208C 1 8 0 25 V 1 8 0 15 V 133 MHz HD6417709SBP133B 240 pin CSP BP 240A HD6417709SF100B 208 pin plastic LQFP FP 208C SH7709S 3 3 0 3 V 1 7 0 25 V 1 7 0 15 V 100 MHz HD6417709SBP100B 240 pin CSP BP 240A ...

Page 802: ...e Code JEDEC JEITA Mass reference value FP 208C Conforms 2 7 g Dimension including the plating thickness Base material dimension 30 0 0 2 30 0 0 2 0 5 1 70 Max 0 8 0 17 0 05 156 105 104 52 1 157 208 53 0 22 0 05 0 08 M 0 08 1 40 0 5 0 1 1 0 28 0 10 0 05 1 25 0 20 0 04 0 15 0 04 Unit mm Figure D 1 Package Dimensions FP 208C ...

Page 803: ...8E Conforms 5 3 g Dimension including the plating thickness Base material dimension 30 6 0 2 30 6 0 2 0 5 3 56 Max 0 8 0 17 0 05 156 105 104 52 1 157 208 53 0 22 0 05 0 10 M 0 10 3 20 0 5 0 1 1 3 28 0 15 0 10 0 15 1 25 0 20 0 04 0 15 0 04 Unit mm Figure D 2 Package Dimensions FP 208E ...

Page 804: ... C 0 65 0 33 0 05 1 40Max B A D C F E H G K J M L P N T R V U W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 20 C A 0 20 C B B C φ0 08 A B 240 φ0 40 0 05 M 0 65 A Unit mm Package Code JEDEC JEITA Mass reference value BP 240A 0 4 g Figure D 3 Package Dimensions BP 240A ...

Page 805: ...ber 2001 Rev 5 00 September 18 2003 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Renesas Kodaira Semiconductor Co Ltd 2001 2003 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 806: ...acher Str 3 D 85622 Feldkirchen Germany Tel 49 89 380 70 0 Fax 49 89 929 30 11 Renesas Technology Hong Kong Ltd 7 F North Tower World Finance Centre Harbour City Canton Road Hong Kong Tel 852 2265 6688 Fax 852 2375 6836 Renesas Technology Taiwan Co Ltd FL 10 99 Fu Hsing N Rd Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Shanghai Co Ltd 26 F Ruijin Building No 205 Maoming...

Page 807: ...SH7709S Group Hardware Manual REJ09B0081 0500O ADE 602 250C ...

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