Realtek Ameba-D RTL872 D Series, User Manual

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Universal Asynchronous Receiver/Transmitter (UART)
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
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The UART consists of several modules, which provide the following functions:

dma_intf

DMA control unit

interface with GDMA module

tx_fifo

asynchronous FIFO

11bit*16

xmitckt

shift register

generate UART format data

support fractional baud rate

irda_sir_encoder

SIR encoder of UART Tx data

rx_fifo

asynchronous FIFO

11 bits*16

recvckt_new

receive UART format data

error detection

interrupt control

support fractional baud rate

oscillator (OSC) clock for low power

monitor and eliminate Rx baud rate error and own frequency drift

irda_sir_decoder

SIR decoder of UART Rx data

apb_slv_wrap

APB3 bus interface

regmng

register control unit
14.2 Register
Table 14-1 shows the register map of the UART module. The base address for KM4 UART0 is 0x4000_4000, and KM0 LUART is 0x4800_E000.
Table 14-1 Register map of UART
Name Address Offset Access Description
IER 0x0004 R/W Enable Interrupt Register
IIR 0x0008 RO Interrupt Identification Register
LCR 0x000C R/W Line Control Register
MCR 0x0010 R/W Modem Control Register
LSR 0x0014 RO Line Status Register
MSR 0x0018 RO Modem Status Register
SCR 0x001C R/W Scratch Pad Register
STSR 0x0020 R/W Factor of Baud Rate Calculation Register
RBR 0x0024 RO Receiver Buffer Register
THR 0x0024 WO Transmitter Holding Register
MISCR 0x0028 R/W DMA Mode and IrDA Mode Control Register
IRDA_SIR_TX_PW_CTRL 0x002C R/W IrDA SIR Tx Pulse Width Control Register
IRDA_SIR_RX_PW_CTRL 0x0030 R/W IrDA SIR Rx Pulse Width Control Register
BAUD_MON 0x0034 R/W Baud Rate Monitor Register
DBG_UART 0x003C R/W Debug Register
REG_RX_PATH_CTRL 0x0040 R/W Rx Path Control Register
REG_MON_BAUD_CTRL 0x0044 R/W Baud Rate Monitor Control Register
REG_MON_BAUD_STS 0x0048 R/W Baud Rate Monitor Status Register
REG_MON_CYC_NUM 0x004C RO Clock Cycle Monitored Register
It displays the actually monitored clock cycle.
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2019-05-15 10:08:03