Direct Memory Access Controller (DMAC)
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The source requests a burst transaction at time T2. The destination requests a burst transaction at time T1 and completes this burst request at
time T3. At time T4, the destination requests a single transaction, which is to be the last in the block transfer. Suppose that at time T4 the
DMAC has fetched seven words from the source and written four words to the destination. Therefore, the DMAC has three words in the
channel FIFO, but the destination requires only one word to complete the block transfer.
The DMAC, recognizing that it has enough data in the channel FIFO to complete the block transfer to the destination, fetches no more data
from the source and early-terminates the source burst transaction (only seven of the eight data items in the source burst transaction have
been fetched from the source) – Early-Terminated Burst Transaction. The DMAC asserts dma_finish[0] to the source at time T5, and this has
the same timing as dma_ack[0], as shown in Fig 9-31.
At time T6, the last single transaction to the destination has completed, which has removed one of the remaining three data words in the
channel FIFO. At this time, both the source and destination block transfers have completed, and there remain two data words in the channel
FIFO that have been fetched from the source. These two data words are lost because they do not form the start of the next block transfer for
multi-block transfers, since the channel FIFO is cleared between blocks for multi-block transfers.
Note
: There is an exception to Case a. If the last AHB transfer to the source received a SPLIT/RETRY response over the AHB bus, then
dma_finish is not asserted until the AHB transfer that received the SPLIT/RETRY response is retried and an OKAY response is received over the
hresp AHB bus; to do otherwise would be a violation of the AMBA protocol. This additional word that is fetched is effectively lost, since it is not
transferred to the destination.
Case 1b – Timing exception on dma_finish to the source when data pre-fetching is enabled
Consider the block transfer shown in Fig 9-32, where the destination is the flow controller and data pre-fetching is enabled (CFG
x
.FCMODE = 0).
Fig 9-32 Timing exception on dma_finish to source peripheral
The source requests a burst transaction at time T2 and completes the burst transaction at time T5. The destination requests a burst transaction
at time T1 and completes this burst request at time T3. At time T4, the destination requests a single transaction, which is to be the last in the
block transfer. At time T5, the DMAC has completed the burst transaction from the source.
At time T5, the DMAC has fetched eight words from the source and written four words to the destination, which means that the DMAC has
four words in the channel FIFO. However, the destination requires only one word to complete the block transfer. The DMAC, recognizing that it
has enough data in the channel FIFO to complete the block transfer to the destination, fetches no more data from the source and signals a
source block completion by asserting dma_finish[0] for a single cycle at time T6. Since there is no active transaction on the source side – that is,
the previous source burst transaction has completed and there has been no new burst request from the source – the dma_finish[0] cannot
form a handshaking loop with dma_req[0] (there is no active burst request) and therefore is asserted for only a single cycle.
Similar to Case a, when both the source and destination block transfers have completed at time T7, there are three data items left in the
channel FIFO that are effectively lost.
Case 2a – Data pre-fetching enabled but no data loss. Source enters Single Transaction Region when destination signals last transaction
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