Direct Memory Access Controller (DMAC)
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9.2.8.1
Transfer Operation
The following examples show the effect of different settings of each parameter from Table 9-4 on a DMA block transfer. In all examples, it is
assumed that no bursts are early-terminated by the AHB system arbiter, unless otherwise stated. Example 1 through Example 8 use hardware
handshaking on both the source and destination side.
The following is a brief description of each of the examples:
Example 1 – Block transfer when the DMAC is the flow controller.
Example 2 – Effect of DMAH_CHx_FIFO_DEPTH on a block transfer.
Example 3 – Effect of maximum AMBA burst length, CFGx.MAX_ABRST, on a block transfer.
Example 4 – Block transfer when the DMAC is the flow controller and the source peripheral enters the Single Transaction Region.
Example 5 – Block transfer when the DMAC is the flow controller and the destination peripheral enters the Single Transaction Region.
Also demonstrates channel FIFO flushing to the destination peripheral at the end of a block transfer.
Example 6 – Effect of CFGx.FIFO_MODE on a block transfer.
Example 7 – Block transfer when the destination peripheral is the flow controller and data pre-fetching from the source is enabled;
CFGx.FCMODE = 0.
Example 8 – Block transfer when the destination peripheral is the flow controller and data pre-fetching from the source is disabled;
CFGx.FCMODE = 1.
The DMAC is programmed with the number of data items that are to be transferred for each burst transaction request,
CTL
x
.SRC_MSIZE/CTL
x
.DEST_MSIZE. Similarly, the width of each data item in the transaction is set by the CTL
x
.SRC_TR_WIDTH and
CTL
x
.DST_TR_WIDTH fields.
9.2.8.1.1
Example 1
Scenario
: Example block transfer when the DMAC is the flow controller. Table 9-5 lists the DMA parameters for this example.
Table 9-5 Parameters in transfer operation – Example 1
Parameter
Description
CTL
x
.TT_FC = 3’b011
Peripheral-to-peripheral transfer with DMAC as flow controller
CTL
x
.BLOCK_TS = 12
–
CTL
x
.SRC_TR_WIDTH = 3’b010
32 bits
CTL
x
.DST_TR_WIDTH = 3’b010
32 bits
CTL
x
.SRC_MSIZE = 3’b001
Source burst transaction length = 4
CTL
x
.DEST_MSIZE = 3’b001
Destination burst transaction length = 4
CFG
x
.MAX_ABRST = 1’b0
No limit on maximum AMBA burst length
DMAH_CH
x
_FIFO_DEPTH = 16 bytes
–
Using equation (5), a total of 48 bytes are transferred in the block; that is,
blk_size_bytes_dma
= 48. As shown in Fig 9-17, this block transfer
consists of three bursts of length 4 from the source, interleaved with three bursts, again of length 4, to the destination.
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