Key-Scan
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325
4:0
KS_FIFO_DATA_LEVEL
R
0x0
Number of entry in FIFO
16.3.9
KS_DATA
Name:
Key-Scan Event FIFO Data Register
Size:
32 bits
Address offset:
0x20
Read/write access:
read-only
When reading this register, these bits return the value in the Event FIFO.
31
30
29
28
…
15
14
13
12
11
10
9
…
2
1
0
RSVD
KS_DATA
R
Bit
Name
Access
Reset
Description
31:12
RSVD
N/A
-
Reserved
11:0
KS_DATA
R
0x0
Bit[11:8]: Key press or release event
0x0: Key release event
0x1: Key press event
Bit[7:4]: Row index
Bit[3:0]: Column index
16.3.10
KS_IMR
Name:
Key-Scan Interrupt Mask Register
Size:
32 bits
Address offset:
0x24
Read/write access:
read/write
These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1
unmasks the interrupt.
31
30
29
…
9
8
7
RSVD
6
5
4
3
2
1
0
KS_SCAN_EVENT_I
NT_MASK
KS_FIFO_LIMIT_IN
T_MASK
KS_FIFO_OV_INT_
MASK
KS_FIFO_FULL_INT
_MASK
KS_SCAN_FINISH_INT
_MASK
KS_FIFO_NOTEMPTY_IN
T_MASK
KS_ALL_RELEASE_INT
_MASK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Access
Reset
Description
31:7
RSVD
N/A
-
Reserved
6
KS_SCAN_EVENT_INT_MASK
R/W
0x0
0x0: Mask scan event interrupt
0x1: Unmask scan event interrupt
5
KS_FIFO_LIMIT_INT_MASK
R/W
0x0
0x0: Mask FIFO limit interrupt
0x1: Unmask FIFO limit interrupt
4
KS_FIFO_OV_INT_MASK
R/W
0x0
0x0: Mask FIFO overflow interrupt
0x1: Unmask FIFO overflow interrupt
3
KS_FIFO_FULL_INT_MASK
R/W
0x0
0x0: Mask FIFO full interrupt
0x1: Unmask FIFO full interrupt
2
KS_SCAN_FINISH_INT_MASK
R/W
0x0
0x0: Mask scan finish interrupt
0x1: Unmask scan finish interrupt
1
KS_FIFO_NOTEMPTY_INT_MASK
R/W
0x0
0x0: Mask FIFO non-empty interrupt
0x1: Unmask FIFO non-empty interrupt
0
KS_ALL_RELEASE_INT_MASK
R/W
0x0
0x0: Mask all release interrupt
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2019-05-15 10:08:03
