Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
232
The RTC prescale diagram is shown in Fig 11-2 .
Asynchronous
prescaler
(128)
Synchronous
prescaler
(256)
calibration
Time counter
( day:hh:mm:ss)
Alarm
[day]:[hh]:[mm]:[ss]
RTCCLK
(32.768kHz)
clk_apre
(256Hz)
clk_spre
(1Hz)
=
RTC_OUT
OSEL[1:0]
alarm_out
clk_spre
clk_apre
0
1
0
1
(-1)
DCS
* DC
(P1)*(CALP+1)*60
Fig 11-2 RTC prescale diagram
11.1.4
RTC Clock Select Diagram
The RTC clock select diagram is shown in Fig 11-3.
When system boots, the default RTC clock source (RTCCLK) is from SDM32K with 0x4800_0004[13:12] = 0 and 0x4800_0004[8] = 0.
When setting 0x4800_0004[13:12] = 10/11 and 0x4800_0004[8] = 0, it means that EXT32K is selected as RTC clock source.
When setting 0x4800_0004[8] = 1 but no care for 0x4800_0004[13:12], the configure divider data for XTAL32K output is from
XTAL40MHz.
When setting 0x4800_0004[13:12] = 01 and 0x4800_0004[8] = 0, the RTC clock source shall be 131kHz. This channel can be selected
when testing for the precision of 131kHz.
When switching RTCCLK between XTAL32K and SDM32K/EXT32K with setting 0x4800_0004[8], you must keep the clock exit in the two
channels. When switching has done, the other channel unused can be power off if needed.
SDM
131K
0
1
0
1
External 32K
0
1
xtal_clk
divider
RTC clock
0x4800_0004[8]
0x4800_0004[12]
0x4800_0004[13]
XTAL32K
Fig 11-3 RTC clock select diagram
11.2
Functional Description
11.2.1
Clock and Prescaler
A programmable prescaler stage generates a 1Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is
split into 2 programmable prescalers.
A 9-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.
A 9-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register.
Realtek confidential files
The document authorized to
SZ99iot
2019-05-15 10:08:03
