Direct Memory Access Controller (DMAC)
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Peripheral to Peripheral
Source Peripheral
Peripheral to Peripheral
Destination Peripheral
As an example, the DMAC can be programmed as the flow controller when a DMA block must be transferred from a receive SSI peripheral to
memory. In a block transfer, software programs the SSI register – CTRLR1.NDF – with the number of source data items minus 1. Software then
programs the CTL
x
.BLOCK_TS register with the same value and programs the DMAC as the flow controller.
The SSI has no built-in intelligence to signal block completion to the DMAC; this is not required in this case because software knows the block
size prior to enabling the channel.
As another example, a peripheral can be a block flow controller when a DMA block must be transferred from an Ethernet controller to
memory. In this case, the size of an ethernet packet may not be known prior to enabling the DMAC channel. Therefore, the ethernet controller
needs built-in intelligence to indicate to the DMAC when a block transfer has completed.
9.2.3
Handshaking Interface
Handshaking interfaces are used at the transaction level to control the flow of single or burst transactions. The operation of the handshaking
interface is different and depends on whether the peripheral or the DMAC is the flow controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer or accept data over the AHB bus.
A non-memory peripheral can request a DMA transfer through the DMAC using one of two types of handshaking interfaces:
Hardware
Software
Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished
through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface.
Note
:
Throughout the remainder of this document, references to both source and destination hardware handshaking interfaces assume an
active-high interface (refer to CFGx.SRC(DST)_HS_POL bits in the Channel Configuration register). When active-low handshaking interfaces are
used, then the active level and edge are reversed from that of an active-high interface.
The type of handshaking interface depends on whether the peripheral is a flow controller or not.
Note
:
Source and destination peripherals can independently select the handshaking interface type; that is, hardware or software handshaking.
For more information, refer to the CFGx.HS_SEL_SRC and CFGx.HS_SEL_DST parameters in the CFGx register.
9.2.4
Basic Interface Definitions
Note
:
In this chapter and the following equations, references to CTLx.SRC_MSIZE, CTLx.DEST_MSIZE, CTLx.SRC_TR_WIDTH, and
CTLx.DST_TR_WIDTH refer to the decoded values of the parameters; for example, CTLx.SRC_MSIZE = 3’b001 decodes to 4, and
CTLx.SRC_TR_WIDTH = 3’b010 decodes to 32 bits.
The following definitions are used in this chapter:
Source single transaction size in bytes
src_single_size_bytes
= CTL
x
.SRC_TR_WIDTH/8
(1)
Source burst transaction size in bytes
src_burst_size_bytes
= CTLx.SRC_MSIZE *
src_single_size_bytes
(2)
Destination single transaction size in bytes
dst_single_size_bytes
= CTLx.DST_TR_WIDTH/8
(3)
Destination burst transaction size in bytes
dst_burst_size_bytes
= CTLx.DEST_MSIZE *
dst_single_size_bytes
(4)
Block size in bytes:
DMAC is flow controller–With the DMAC as the flow controller, the processor programs the DMAC with the number of data items
(block size) of source transfer width (CTL
x
.SRC_TR_WIDTH) to be transferred by the DMAC in a block transfer; this is programmed
into the CTL
x
.BLOCK_TS field. Therefore, the total number of bytes to be transferred in a block is:
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