Memory Organization
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2.4
KM4 Embedded SRAM
The KM4 contains up to a total 512KB of contiguous, on-chip static RAM memory. This embedded SRAM can be accessed as bytes (8 bits), half-
words (16 bits) or full words (32 bits). It is divided into the following two blocks which can be accessed by both KM4 and KM0.
KM4 SRAM1 (up to 256KB)
KM4 SRAM2 (up to 256KB)
Dividing SRAM into two slave ports allows user’s program to potentially obtain better performance. For example, simultaneous access to
SRAM1 by the CPU and by the system DMA controller does not result in any bus stalls for either master.
Generally speaking, the CPU reads or writes all peripheral data at some point, even when all such data is read from or sent to a peripheral by
DMA. So, minimizing stalls is likely to involve putting data to/from different peripherals in RAM on each port.
Alternatively, sequences of data from the same peripheral can be alternated between RAM on each port. This could be helpful if DMA fills or
empties a RAM buffer, and signals the CPU before proceeding on to a second buffer. The CPU then tends to access the data while the DMA is
using the other RAM.
In power domains, the entire SRAM is also divided into three blocks:
SRAM_PD1 (up to 256KB)
SRAM_PD2 (up to 128KB)
SRAM_PD3 (up to 128KB)
Each block can be disabled or enabled individually in the Power Management Unit (PMU) block to save power, and the entire SRAM can also
keep power for quickly resuming from sleep mode when system enters sleep mode.
2.5
KM0 Embedded SRAM
The KM0 features 64KB of system SRAM. The embedded SRAM can be accessed as bytes (8 bits), half-words (16 bits) or full words (32 bits).
This SRAM can be accessed by both KM4 and KM0.
2.6
KM4 Extension SRAM
When Bluetooth is disabled, more 64KB SRAM will be extended. This SRAM can also be accessed by both KM4 and KM0, up to 50MHz*32 bits.
2.7
Retention SRAM
Ameba-D features 1KB of retention SRAM in order to allow saving data with minimal power usage during deepsleep mode.
This SRAM can be accessed by both KM4 and KM0.
2.8
SPI Flash Memory
The SPI Flash Controller (SPIC) manages CPU I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash
memory operations, and the read/write protection mechanisms. It accelerates code execution with a system of instruction prefetch and cache
lines.
2.9
PSRAM
4MB 8IO DDR PSRAM is included in Ameba-D, up to 50MHz DDR.
