Ameba-D User Manual
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140
If status write-back is enabled, the upper word of the control register, CTL
x
[63:32], is written to the control register location of the LLI in
system memory at the end of the block transfer.
Note
: You need to program this register prior to enabling the channel
.
Bit
Name
Access Reset
Description
63:45
RSVD
N/A
0x0
Reserved
44
DONE
R/W
0x0
Done bit
If status write-back is enabled, the upper word of the control
register, CTL
x
[63:32], is written to the control register location
of the Linked List Item (LLI) in system memory at the end of the
block transfer with the done bit set.
Software can poll the LLI CTL
x
.DONE bit to see when a block
transfer is complete. The LLI CTL
x
.DONE bit should be cleared
when the linked lists are set up in memory prior to enabling
the channel.
LLI accesses are always 32-bit accesses (Hsize = 2) aligned to 32-
bit boundaries and cannot be changed or programmed to
anything other than 32-bit.
b
:32
(See description)
BLOCK_TS
R/W
0x2
Block Transfer Size.
When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total
number of single transactions to perform for every block
transfer; a single transaction is mapped to a single AMBA beat.
Width
: The width of the single transaction is determined by
CTL
x
.SRC_TR_WIDTH.
Once the transfer starts, the read-back value is the total
number of data items already read from the source peripheral,
regardless of what is the flow controller.
When the source or destination peripheral is assigned as the
flow controller, then the maximum block size that can be read
back saturates at DMAH_CH
x
_MAX_BLK_SIZE, but the actual
block size can be greater.
b
= log
2
(DMAH_CH
x
_MAX_BL 1) + 31
Bit[43:
b
+1] do not exist and return 0 on a read.
31:29
RSVD
N/A
0x0
Reserved
28
LLP_SRC_EN
R/W
0x0
Block chaining is enabled on the source side only if the
LLP_SRC_EN field is high and LLP
x
.LOC is non-zero.
Dependencies:
This field does not exist if the configuration
parameter DMAH_CH
x
_MULTI_BLK_EN is not selected or if
DMAH_CH
x
_HC_LLP is selected; in this case, the read-back
value is always 0.
27
LLP_DST_EN
R/W
0x0
Block chaining is enabled on the destination side only if the
LLP_DST_EN field is high and LLP
x
.LOC is non-zero.
Dependencies:
This field does not exist if the configuration
parameter DMAH_CH
x
_MULTI_BLK_EN is not selected or if
DMAH_CH
x
_HC_LLP is selected; in this case, the read-back
value is always 0.
26:25
SMS
R/W
DMAH_CH
x
_SMS[1:0]
Source Master Select. Identifies the Master Interface layer
from which the source device (peripheral or memory) is
accessed.
00 = AHB master 1
01 = AHB master 2
10 = AHB master 3
11 = AHB master 4
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2019-05-15 10:08:03
