Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
474
22.4.1.3
Serial Data
Serial Data (SD) line is designed into two lines (SD_i, SD_o) for Ameba-D I
2
S except in 5.1 Tx mode, where three lines (SD0, SD1, SD2) are
used.
SD is transmitted with MSB first.
In I
2
S data format, MSB has a fixed position, whereas the position of the LSB depends on the word length.
When system word length is greater than transmitter word length, the word is truncated (least significant data bits are set to ‘0’).
If receiver is sent more bits than its word length, the bits after the LSB are ignored.
If receiver is sent fewer bits than its word length, the missing bits are set to zero internally.
In I
2
S data format, transmitter always sends MSB of the next word one clock period after the WS changes.
SD sent by transmitter is synchronized with either the trailing (HIGH to LOW) or the leading (LOW to HIGH) edge of the clock signal.
SD must be latched into the receiver on the leading edge of SCK.
22.4.2
Operation Mode
22.4.2.1
Transmitter as the Master
In this operation mode, as the master, the transmitter has to generate the SCK, WS signal and SD, while the receiver accepts the SCK, WS, SD
from the bus as the slave. See Fig 22-4.
TRANSMITTER
RECEIVER
Serial Clock
Word Select
Serial Data
TRANSMITTER = MASTER
Fig 22-4 Transmitter as the master
22.4.2.2
Receiver as the Master
In this operation mode, as the master, the receiver has to generate the SCK and WS signal, while the transmitter sends SD under the control of
SCK and WS as the slave. See Fig 22-5.
TRANSMITTER
RECEIVER
Serial Clock
Word Select
Serial Data
RECEIVER = MASTER
Fig 22-5 Receiver as the master
22.4.2.3
Controller as the Master
In this operation mode, as the master, the controller generates the SCK and WS signal; while the transmitter and the receiver act as the slave,
the transmitter has to generate data under the control of external clocks. See Fig 22-6.
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