Direct Memory Access Controller (DMAC)
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Fig 9-22 Breakdown of block transfer where max_abrst = 2, Case 2
This depends on the timing of the source and destination transaction requests, relative to each other. Fig 9-23 illustrates the channel FIFO
status for Fig 9-22.
Fig 9-23 Channel FIFO contents at times indicated in Fig 9-22
Recommendation
: To allow a burst transaction to complete in a single burst, the following should be true:
CFG
x
.MAX_ABRST >= max(
src_burst_size_bytes
,
dst_burst_size_bytes
)
Adhering to the above recommendation results in a reduced number of bursts per block, which in turn results in improved bus utilization and
lower latency for block transfers. Limiting a burst to a maximum length prevents the DMAC from saturating the AHB bus when the AHB system
arbiter is configured to only allow changing of the grant signals to bus masters at the end of an undefined length burst. It also prevents a
channel from saturating a DMAC master bus interface.
9.2.8.1.4
Example 4
Scenario:
Source peripheral enters Single Transaction Region; the DMAC is the flow controller.
This example demonstrates how a block from the source can be completed using a series of single transactions. It also demonstrates how the
watermark level that triggers a burst request in the source peripheral can be dynamically adjusted so that the block transfer from the source
completes with an Early-Terminated Burst Transaction. Table 9-6 lists the parameters used in this example.
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