Realtek Ameba-D RTL872 D Series, User Manual

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Memory Organization
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2 Memory Organization
2.1 Introduction
Ameba-D incorporates several distinct memory regions. Program memory, data memory, registers, and I/O ports are organized within the
same linear 4Gbytes address space. The bytes are coded in memory in Little-Endian format.
The addressable memory space is divided into multiple main blocks, as shown in Table 2-1. All the memory areas that are not allocated to on-
chip memories and peripherals are considered “RSVD” (reserved). For the detailed mapping of available memory and register areas, refer to
the following sections.
Table 2-1 Address space main blocks
Base Address Top Address Size Function Description
0x0000_0000 0x0001_FFFF 128KB KM0 ITCM ROM (actually 96KB) 32MB: KM0 Memory Address
0x0002_0000 0x0002_7FFF 32KB KM0 DTCM ROM (actually 16KB)
0x0002_8000 0x0007_FFFF 352KB RSVD
0x0008_0000 0x0008_FFFF 64KB KM0 SRAM
0x0009_0000 0x000B_FFFF 192KB RSVD
0x000C_0000 0x000C_3FFF 16KB Retention SRAM (1KB) (the same port
with KM0 SRAM)
0x000C_4000 0x000F_FFFF 240KB RSVD
0x0010_0000 0x01FF_FFFF 31MB RSVD
0x0200_0000 0x07FF_FFFF 96MB External PSRAM 224MB: External Memory Address
0x0800_0000 0x0FFF_FFFF 128MB External FLASH
0x1000_0000 0x1007_FFFF 512KB KM4 SRAM 256MB: KM4 Memory Address
0x1008_0000 0x100D_FFFF 384KB RSVD
0x100E_0000 0x100E_FFFF 64KB Extension SRAM0 from Bluetooth
0x100F_0000 0x100F_FFFF 64KB Extension SRAM1 from Wi-Fi
0x1010_0000 0x1013_FFFF 256KB KM4 ITCM ROM
0x101C_0000 0x101D_7FFF 96KB KM4 DTCM ROM
0x101C_0000 0x101F_FFFF 256KB RSVD
0x1020_0000 0x1FFF_FFFF 254MB RSVD
0x2000_0000 0x3FFF_FFFF 512MB RSVD Reserved
0x4000_0000 0x47FF_FFFF 128MB KM4 Peripherals 128MB: KM4 Peripherals Address
0x4800_0000 0x4FFF_FFFF 128MB KM0 Peripherals 128MB: KM0 Peripherals Address
0x5000_0000 0x57FF_FFFF 128MB KM4 Peripherals Secure 128MB: KM4 Peripherals Secure Address
0x5800_0000 0xFFFF_FFFF 2816MB RSVD Reserved
2.2 KM4 Memory Map and Register Boundary Addresses
Table 2-2 gives the boundary addresses of the peripherals available in the KM4 devices.
Table 2-2 KM4 register boundary addresses
Port Name Security Base Address Top Address Size
KM4_SRAM1 IDAU 0x1000_0000 0x1003_FFFF 256KB
KM4_SRAM2 IDAU 0x1004_0000 0x1007_FFFF 256KB
Extension SRAM IDAU 0x100E_0000 0x100F_FFFF 128KB
PSRAM Memory IDAU 0x0200_0000 0x07FF_FFFF 96MB
HS_SYSON Non-Secure 0x4000_0000 0x4000_0FFF 4KB
Secure 0x5000_0000 0x5000_0FFF 4KB
HS_TIM0 ~ 3/4/5 Non-Secure 0x4000_2000 0x4000_2FFF 4KB
HS_UART0 Non-Secure 0x4000_4000 0x4000_4FFF 4KB