Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
450
31
30
29
…
10
9
8
RSVD
7
6
5
4
3
2
1
0
DAT_PLRTY
OE_PLRTY
LAT_PLRTY
LAT_PLRTY
LEDIFUPDATE
COLORCHAN
COLORNUM
R/W
R/W
R/W
R/W
R/W1S
R/W
R/W
Bit
Name
Access
Reset
Description
31:8
RSVD
N/A
0
Reserved
7
DAT_PLRTY
R/W
0
The Data pulse polarity
0: Normal
1: Inverted
6
OE_PLRTY
R/W
0
The OE pulse polarity
0: Low level for active pulse
1: High level for active pulse
5
LAT_PLRTY
R/W
0
The polarity of the LATCH active edge
0: Data pushed to output buffer at LATCH rising edge
1: Data pushed to output buffer at LATCH falling edge
4
LAT_PLRTY
R/W
0
The polarity of the DCLK active edge
0: Data fetched at DCLK rising edge
1: Data fetched at DCLK falling edge
3
LEDIFUPDATE
R/W1S
0
Force Hardware to update LED I/F parameters after current LED refresh frame
done.
CPU writes 1 to force Hardware updating parameters. After updating, this bit is
cleared.
When the LCDC is running, if the following values related with LED I/F mode are
modified dynamically, only writing 1 to this bit can the newer value be used by
hardware after the current frame refresh done.
The LATW, OEACTW bits in the
register
2
COLORCHAN
R/W
0
0: One channel
1: Two channels
1:0
COLORNUM
R/W
0x0
Color number in frame buffer (SRAM/PSRAM)
0: One color
1: Two colors
2: Three colors
3: Reserved
20.3.5.2
LCDC_LED_TIMING
Name
: LCDC LED timing register
Size:
32 bits
Address offset:
0x0084
Read/write access:
read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
OEACTW
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OEACTW
LATW
R/W
R/W
Bit
Name
Access
Reset
Description
31:24
RSVD
N/A
0
Reserved
23:8
OEACTW
R/W
0
OE Active Width Time – 1 (unit: dotclock).
7:0
LATW
R/W
0
LAT Width Time - 1 (unit: dotclock).
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2019-05-15 10:08:03
