Ameba-D User Manual
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254
Fig 13-18 illustrates operation as a master receiver where the Stop bit of the IC_DATA_CMD register is set and the Tx FIFO is not empty.
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ACK
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
R
SDA
SCL
FIFO
EMPTY
S
ACK
Data with read
command written
into Tx FIFO
Command availability makes
START condition
One command (not last)
with STOP bit set
Because STOP bit is set in
current command byte.
Master issues STOP condition.
NAK
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ACK
R
D
6
D
7
P
S
Because more command is available in Tx FIFO, a
new transmission immediately starts with a
START condition.
Fig 13-18 Master receiver — Stop bit of IC_DATA_CMD set/Tx FIFO not empty
13.2.6
Multiple Master Arbitration
The I
2
C bus protocol allows multiple masters to reside on the same bus. If there are two masters on the same I²C-bus, there is an arbitration
procedure if both try to take control of the bus at the same time by generating a START condition at the same time. Once a master (for
example, a microcontroller) has control of the bus, no other master can take control until the first master sends a STOP condition and places
the bus in an idle state.
Arbitration takes place on the SDA line, while the SCL line is 1. The master, which transmits a 1 while the other master transmits 0, loses
arbitration and turns off its data output stage. The master that lost arbitration can continue to generate clocks until the end of the byte
transfer. If both masters are addressing the same slave device, the arbitration could go into the data phase.
Upon detecting that it has lost arbitration to another master, the I
2
C will stop generating SCL.
Fig 13-19 illustrates the timing of when two masters are arbitrating on the bus.
Fig 13-19 Multiple master arbitration
For high-speed mode, the arbitration cannot go into the data phase because each master is programmed with a unique high-speed master
code. This 8-bitcode is defined by the system designer and is set by writing to the IC_HS_MADDR (High Speed Master Mode Code Address)
register. Because the codes are unique, only one master can win arbitration, which occurs by the end of the transmission of the high-speed
master code. Control of the bus is determined by address or master code and data sent by competing masters, so there is no central master
nor any order of priority on the bus.
Slaves are not involved in the arbitration process.
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2019-05-15 10:08:03
