Realtek Ameba-D RTL872 D Series, User Manual

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Audio Codec Controller (ACC)
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
389
SP_CLK_DIV 0x001C R/W SPORT frequency synthesizer register
18.4.1.1 SP_TX_DR

Name : SPORT Tx data register

Size : 32 bits

Address offset : 0x0000

Read/write access : write
31 30 29 28 27 26 25 24 … 7 6 5 4 3 2 1 0
SP_TX_DR
W
Bit Name Access Reset Description
31:0 SP_TX_DR W 32’h0 It’s Tx data window between SW/GDMA and SPORT.
18.4.1.2 SP_CTRLR0

Name : SPORT control 0 register

Size : 32 bits

Address offset : 0x0004

Read/write access : read/write
31 30 29 28 27 26 25 24
LONG_FRAME_S
YNC
MCLK_SEL SP_SEL_I2S_RX_CH SP_DAC_COMP SP_START_RX SP_RX_DISABLE
R/W R/W R/W R/W R/W R/W
23 22 21 20 19 18 17 16
RX_LSB_FIRST TX_LSB_FIRST SP_SEL_I2S_TX_CH SP_ADC_COMP SP_START_TX SP_TX_DISABLE
R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8
SP_I2S_SELF_LPB
K_EN
SP_INV_I2S_SCLK SP_DATA_LEN_SEL
SP_EN_I2S_MON
O
SP_EN_PCM_N_M
ODE
SP_DATA_FORMAT_SEL
R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
DSP_CTL_MODE SP_LOOPBACK
SP_WCLK_INVER
SE
SLAVE_DATA_
SEL
SLAVE_CLK_SEL RX_INV_I2S_SCLK TX_INV_I2S_SCLK SP_RESET
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Access Reset Description
31 LONG_FRAME_SYNC R/W 1’b0

1’b0: Short frame sync

1’b1: Long frame sync
30 MCLK_SEL R/W 1’b0

1’b1: MCLK output=128*fs

1’b0: MCLK output=256*fs
29:28 SP_SEL_I2S_RX_CH R/W 2’b00

2’b00: L/R

2’b01: R/L

2’b10: L/L

2’b11: R/R @ ADC path
27:26 SP_DAC_COMP R/W 2’b00

2’b00: OFF

2’b01: u law

2’b10: A law
25 SP_START_RX R/W 1’b0

1’b0: Rx is disabled

1’b1: Rx is started
24 SP_RX_DISABLE R/W 1’b1

1’b1: SPORT Rx is disabled

1’b0: SPORT Rx is enabled
23 RX_LSB_FIRST R/W 1’b0

1’b0: MSB first when Rx

1’b1: LSB first
22 TX_LSB_FIRST R/W 1’b0

1’b0: MSB first when Tx
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2019-05-15 10:08:03