Direct Memory Access Controller (DMAC)
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If channel-level or bus-level locking is enabled for a channel at the transaction level, and either the source or destination of the channel is a
memory device, then the locking is ignored and the channel proceeds as if locking (bus or channel) is disabled.
Note
: Since there is no notion of a transaction level for a memory peripheral, then transaction-level locking is not allowed when either source
or destination is memory.
9.2.11.1.4
Channel Locking and Deadlock
Certain combinations of channel-level and bus-level locking may lead to deadlock, where multiple channels are concurrently enabled and no
channel can proceed with the DMA transfer. This occurs only for configurations where DMAH_NUM_MASTER_INT > 1 and
DMAH_NUM_CHANNELS > 1.
9.2.12
Arbitration for AHB Master Interface
Each DMAC channel has two request lines that request ownership of a particular master bus interface: channel source and channel destination
request lines.
Source and destination arbitrate separately for the bus. Once a source/destination state machine gains ownership of the master bus interface
and the master bus interface has ownership of the AHB bus, then AHB transfers can proceed between the peripheral and DMAC. Fig 9-42
illustrates the arbitration flow of the master bus interface.
Fig 9-42 Arbitration flow for master bus interface
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