Realtek Ameba-D RTL872 D Series, User Manual

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Nested Vectored Interrupt Controller (NVIC)
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This register allows changing the interrupt state to pending and reading back the interrupt pending
state for peripheral functions.
ISPR1 0x204 R/W 0 Interrupt Set Pending Register 1. See ISPR0 description.
ICPR0 0x280 R/W 0 Interrupt Clear Pending Register 0.
This register allows changing the interrupt state to no pending and reading back the interrupt
pending state for peripheral functions.
ICPR1 0x284 R/W 0 Interrupt Clear Pending Register 1. See ICPR0 description.
IABR0 0x300 RO 0 Interrupt Active Bit Register 0.
This register allows reading the current interrupt active state for specific peripheral functions.
IABR1 0x304 RO 0 Interrupt Active Bit Register 1. See IABR0 description.
IPR0 0x400 R/W 0 Interrupt Priority Register 0.
This register contains the 3-bit priority fields for interrupt 0 to 3.
IPR1 0x404 R/W 0 Interrupt Priority Register 1.
This register contains the 3-bit priority fields for interrupt 4 to 7.
IPR2 0x408 R/W 0 Interrupt Priority Register 2.
This register contains the 3-bit priority fields for interrupt 8 to 11.
IPR3 0x40C R/W 0 Interrupt Priority Register 3.
This register contains the 3-bit priority fields for interrupt 12 to 15.
IPR4 0x410 R/W 0 Interrupt Priority Register 4.
This register contains the 3-bit priority fields for interrupt 16 to 19.
IPR5 0x414 R/W 0 Interrupt Priority Register 5.
This register contains the 3-bit priority fields for interrupt 20 to 23.
IPR6 0x418 R/W 0 Interrupt Priority Register 6.
This register contains the 3-bit priority fields for interrupt 24 to 27.
IPR7 0x41C R/W 0 Interrupt Priority Register 7.
This register contains the 3-bit priority fields for interrupt 28 to 31.
IPR8 0x420 R/W 0 Interrupt Priority Register 8.
This register contains the 3-bit priority fields for interrupt 32 to 35.
IPR9 0x424 R/W 0 Interrupt Priority Register 9.
This register contains the 3-bit priority fields for interrupt 36 to 39.
IPR10 0x428 R/W 0 Interrupt Priority Register 10.
This register contains the 3-bit priority field for interrupt 40 to 43.
IPR11 0x42C R/W 0 Interrupt Priority Register 11.
This register contains the 3-bit priority fields for interrupt 44 to 47.
IPR12 0x430 R/W 0 Interrupt Priority Register 12.
This register contains the 3-bit priority fields for interrupt 48 to 51.
IPR13 0x434 R/W 0 Interrupt Priority Register 13.
This register contains the 3-bit priority fields for interrupt 52 to 55.
IPR14 0x438 R/W 0 Interrupt Priority Register 14.
This register contains the 3-bit priority fields for interrupt 56 to 58.
STIR 0xF00 WO - Software Trigger Interrupt Register, allows software to generate interrupts.
4.4.1 ISER0 and ISER1
The ISER0 register allows enabling the first 32 peripheral interrupts, or reading the enabled state of those interrupts. The remaining interrupts
are enabled via the ISER1 register. The interrupts can be disabled through the ICER0 and ICER1 registers.
Each bit in the ISER0 and ISER1 registers controls one interrupt in NVIC table.
The operation of read/write to this register means that:

Write: Writing 0 has no effect, writing 1 enables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
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2019-05-15 10:08:03