Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
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4.4.2
ICER0 and ICER1
The ICER0 register allows disabling the first 32 peripheral interrupts, or reading the enabled state of those interrupts. The remaining interrupts
are disabled via the ICER1 register. The interrupts can be enabled through the ISER0 and ISER1 registers.
The operation of read/write to this register means that:
Write: Writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
4.4.3
ISPR0 and ISPR1
The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or reading the pending state of those interrupts. The
remaining interrupts can have their pending state set via the ISPR1 register. The pending state of the interrupts can be cleared through the
ICPR0 and ICPR1 registers.
The operation of read/write to this register means that:
Write: Writing 0 has no effect, writing 1 change the interrupt state to pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
4.4.4
ICPR0 and ICPR1
The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or reading the pending state of those interrupts. The
remaining interrupts can have their pending state cleared via the ICPR1 register. The pending state of the interrupts can be set through the
ISPR0 and ISPR1 registers.
The operation of read/write to this register means that:
Write: Writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
4.4.5
IABR0 and IABR1
The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. Bits in IABR registers are set
while the corresponding interrupt service routines are in progress. Additional interrupts active state can be read via the IABR1 register.
The operation of read to this register means that:
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
4.4.6
IPR0 ~ IPR14
Each IPR register controls the priority of the 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority.
4.4.7
STIR
The Software Trigger Interrupt Register (STIR) provides an alternate way for software to generate an interrupt, in addition to using the ISPR
registers. This mechanism can only be used to generate peripheral interrupts, not system exceptions.
By default, only privileged software can write to the STIR register. Unprivileged software can be given this ability if privileged software sets the
USERSETMPEND bit in the CCR register.
The interrupt number to be programmed in the STIR register is listed in Table 4-3.
Table 4-3 Software trigger interrupt register
Address Offset
Bit
Name
Description
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