Realtek Ameba-D RTL872 D Series, User Manual

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Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
54
7.3.2 IPC x _IDR

Name : Interrupt Disable Register

Size : 32 bits

Address offset : 0x0004

Read/write access : write-only
The IPC
x _IDR ( x = {0, 1}) is used to disable IPC interrupts, and the interrupt mask can be read from IPC x _IER_R.
31 30 29 28 27 … 4 3 2 1 0
IPC_IDR x
WO
Bit Name Access Default Description
31:0 IPC_IDR x WO 0

Writing a ‘1’ to a bit of this register disables the corresponding interrupt.

Writing a ‘0’ has no effect.
7.3.3 IPC x _IRR

Name : Interrupt Request Register

Size : 32 bits

Address offset : 0x0008

Read/write access : write-only
The IPC
x _IRR ( x = {0, 1}) register allows other CPUs to send interrupt requests to the peer CPU. This is intended to allow communication
between CPUs. For example, one CPU can be handling certain peripherals and signaling another CPU when data is available. The use of this
feature is entirely up to the user.
31 30 29 28 27 … 4 3 2 1 0
IPC_IRR x
WO
Bit Name Access Default Description
31:0 IPC_IRR x WO 0

Writing a ‘1’ to a bit of this register requests the corresponding interrupt.

Writing a ‘0’ has no effect.
7.3.4 IPC x _ICR

Name : Interrupt Clear Register

Size : 32 bits

Address offset : 0x000C

Read/write access : write-only
The IPC
x _ISR ( x = {0, 1}) is used to clear pending IPC interrupts. It is set by the target CPU.
31 30 29 28 27 … 4 3 2 1 0
IPC_ICR x
WO
Bit Name Access Default Description
31:0 IPC_ICR x WO 0

Writing a ‘1’ to a bit of this register clears the corresponding interrupt.

Writing a ‘0’ has no effect.
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2019-05-15 10:08:03