General Purpose Input/Output (GPIO)
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75
Bit
Name
Access
Description
31:
GPIO_PWIDTH_C
Reserved
Read as zero
Reserved
GPIO_PWIDTH_C
–1:0
Port C Data Direction
R/W
Values written to this register independently control the direction
of the corresponding data bit in Port C. The default direction can
be configured as input or output after system reset through the
GPIO_DFLT_DIR_C parameter.
0 – Input (default)
1 – Output
Reset Value
:
GPIO_DFLT_DIR_C
8.3.3.9
gpio_swportc_ctl
Name:
Port C Data Source
Size
:
1 bit wide if GPIO_PORTC_SINGLE_CTL = 1
GPIO_PWIDTH_C
bits wide if GPIO_PORTC_SINGLE_CTL = 0
Address offset
: 0x20
Read/write access
: read/write
Bit
Name
Access Description
0
-or-
0:
GPIO_PWIDTH_C
-1
(See above)
Port C Data Source
R/W
The data and control source for a signal can come from either software or
hardware; this bit selects between them. The default source is configurable
through the GPIO_DFLT_SRC_C configuration parameter.
0 – Software mode (default)
1 – Hardware mode
If GPIO_PORTC_SINGLE_CTL = 0, the register will contain one bit for each bit of
the signal. Upon reset in this case, the value of GPIO_DFLT_SRC_C is replicated
across all bits of the signal so that all bits power up with the same operating
mode. Furthermore, the default source of each bit of the signal can subsequently
be changed by writing to the corresponding bit of this register.
This register is not available unless GPIO_HW_PORTC = 1.
Reset Value
:
If GPIO_PORTC_SINGLE_CTL = 1, then the reset value is
GPIO_DFLT_SRC_C
.
If GPIO_PORTC_SINGLE_CTL = 0, then the reset value is
{GPIO_PWIDTH_C{GPIO_DFLT_SRC_C in each bit}}.
8.3.3.10
gpio_swportd_dr
Name:
Port D Data Register
Size:
GPIO_PWIDTH_D
Address offset
: 0x24
Read/write access
: read/write
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2019-05-15 10:08:03
