Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
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9
Direct Memory Access Controller (DMAC)
9.1
Product Overview
This chapter provides a basic overview of the Ameba-D DMAC, which is an AHB-Central DMA Controller core that transfers data from a source
peripheral to a destination peripheral over one or more AHB bus.
9.1.1
General Product Description
Fig 9-1 shows the following functional groupings of the main interfaces to the DMAC block.
DMA hardware request interface
Up to eight channels
FIFO per channel for source and destination
Arbiter
AHB master interface
AHB slave interface
Fig 9-1 Block diagram of DMAC
One channel of the DMAC is required for each source/destination pair. In the most basic configurations, as illustrated in Fig 9-2, the DMAC has
one master interface and one channel. The master interface reads the data from a source peripheral (A) and writes it to a destination
peripheral (B). Two AHB transfers are required for each DMA data transfer; this is also known as a dual-access transfer.
Fig 9-2 illustrates a peripheral-to-peripheral DMA transfer, where peripheral A (source) uses a hardware handshaking interface, and peripheral
B (destination) uses a software handshaking interface. For example, the request to send data to peripheral B is originated by the CPU, while
writing to peripheral B is handled by the DMAC. The channel source and destination arbitrate independently for the AHB master interface,
along with other channels.
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