Ameba-D User Manual
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complete interrupt and disables the channel. You can either respond to the Block Complete or Transfer Complete interrupts, or poll for
the transfer complete raw interrupt status register (RawTfr[
n
],
n
= channel number) until it is set by hardware, in order to detect when
the transfer is complete. Note that if this polling is used, software must ensure that the transfer complete interrupt is cleared by writing
to the Interrupt Clear register, ClearTfr[
n
], before the channel is enabled. If the DMAC is not in Row 1 or Row 5 as shown in Table 9-19,
the following steps are performed.
(23)
The DMA transfer proceeds as follows:
a.
If interrupts are enabled (CTL
x
.INT_EN = 1) and the block-complete interrupt is unmasked (MaskBlock[
x
] = 1’b1, where
x
is the
channel number), hardware sets the block-complete interrupt when the block transfer has completed. It then stalls until the block-
complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block-complete ISR
(interrupt service routine) should clear the CFG
x
.RELOAD_SRC source reload bit. This puts the DMAC into Row 1, as shown in Table
9-19. If the next block is not the last block in the DMA transfer, then the source reload bit should remain enabled to keep the DMAC
in Row 7, as shown in Table 9-19.
b.
If interrupts are disabled (CTL
x
.INT_EN = 0) or the block-complete interrupt is masked (MaskBlock[
x
] = 1’b0, where
x
is the channel
number), then hardware does not stall until it detects a write to the block-complete interrupt clear register; instead, it immediately
starts the next block transfer. In this case, software must clear the source reload bit, CFG
x
.RELOAD_SRC in order to put the device
into Row 1 of Table 9-19 before the last block of the DMA transfer has completed.
(24)
The DMAC fetches the next LLI from memory location pointed to by the current LLPx register and automatically reprograms the DARx,
CTLx, and LLPx channel registers. Note that the SAR
x
is not reprogrammed, since the reloaded value is used for the next DMA block
transfer. If the next block is the last block of the DMA transfer, then the CTL
x
and LLP
x
registers just fetched from the LLI should match
Row 1 or Row 5 of Table 9-19.
The DMA transfer might look like that shown in Fig 9-55.
Fig 9-55 Multi-block DMA transfer with source address auto-reloaded and linked list destination address
The DMA transfer flow is shown in Fig 9-56.
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