Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
178
9.4.5
Programming a Channel
Three registers – LLPx, CTLx, and CFGx – need to be programmed to determine whether single- or multi-block transfers occur, and which type
of multi-block transfer is used. The different transfer types are shown in Table 9-19.
The DMAC can be programmed to fetch the status from the source or destination peripheral; this status is stored in the SSTATx and DSTATx
registers. When the DMAC is programmed to fetch the status from the source or destination peripheral, it writes this status and the contents
of the CTL
x
register back to memory at the end of a block transfer. The Write Back column of Table 9-19 shows when this occurs.
The “Update Method” columns indicate where the values of SARx, DARx, CTLx, and LLPx are obtained for the next block transfer when multi-
block DMA transfers are enabled.
Note
:
In Table 9-19, all other combinations of LLPx.LOC = 0, CTLx.LLP_SRC_EN, CFGx.RELOAD_SRC, CTLx.LLP_DST_EN, and CFGx.RELOAD_DST
are illegal, and will cause indeterminate or erroneous behavior.
The programming examples are as follows:
Single-block Transfer (Row 1)
Multi-Block Transfer with Linked List for Source and Linked List for Destination (Row 10)
Multi-Block Transfer with Source Address Auto-Reloaded and Destination Address Auto-Reloaded (Row 4)
Multi-Block Transfer with Source Address Auto-Reloaded and Linked List Destination Address (Row 7)
Multi-Block Transfer with Source Address Auto-Reloaded and Contiguous Destination Address (Row 3)
Multi-Block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8)
9.4.5.1
Single-block Transfer (Row 1)
This section describes a single-block transfer, Row 1 in Table 9-19.
Note
: Row 5 in Table 9-19 is also a single-block transfer with write-back of control and status information enabled at the end of the single-block
transfer.
(1)
Read the Channel Enable register to choose a free (disabled) channel.
(2)
Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr,
ClearBlock, ClearSrcTran, ClearDstTran, and ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all
interrupts have been cleared.
(3)
Program the following channel registers:
a)
Write the starting source address in the SARx register for channel
x
.
b)
Write the starting destination address in the DARx register for channel
x.
c)
Program CTL
x
and CFG
x
according to Row 1, as shown in Table 9-19. Program the LLPx register with 0.
d)
Write the control information for the DMA transfer in the CTLx register for channel
x
. For example, in the register, you can program
the following:
i.
Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by
programming the TT_FC of the CTL
x
register. Table 9-17 lists the decoding for this field.
ii.
Set up the transfer characteristics, such as:
Transfer width for the source in the SRC_TR_WIDTH field. Table 9-16 lists the decoding for this field.
Transfer width for the destination in the DST_TR_WIDTH field. Table 9-16 lists the decoding for this field.
Source master layer in the SMS field where the source resides.
Destination master layer in the DMS field where the destination resides.
Incrementing/decrementing or fixed address for the source in the SINC field.
Incrementing/decrementing or fixed address for the destination in the DINC field.
e)
Write the channel configuration information into the CFGx register for channel x.
i.
Designate the handshaking interface type (hardware or software) for the source and destination peripherals; this is not
required for memory.
This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a 0 activates the hardware
handshaking interface to handle source/destination requests.
Writing a 1 activates the software handshaking interface to handle source and destination requests.
Realtek confidential files
SZ99iot
2019-05-15 10:08:03
