Realtek Ameba-D RTL872 D Series, User Manual

Page: 469 / 494

Quadrature Decoder (Q-Decoder)
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
469
31 30 29 28 27 26 25 24
RSVD
23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8
RC_INT_M
RSVD
VUPLMT_INT_M VLOWLMT_INT_M
RSVD
VCCAP_INT_M PCE_INT_M IDX_INT_M
R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
RUF_INT_M ROF_INT_M PC_INT_M DR_INT_M IL_INT_M UF_INT_M OF_ INT_M CT_INT_M
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Access Default Description
31:16 RSVD N/A -- Reserved
15 RC_INT_M R/W 0 Rotation counter comparing interrupt mask

0: Unmask

1: Mask
This interrupt is asserted when the rotation counter is equal to the value of ‘RCC‘.
14 RSVD N/A -- Reserved
13 VUPLMT_INT_M R/W 0 Velocity upper limit interrupt mask

0: Unmask

1: Mask
When a capture event happens and the velocity counter capture is bigger than the
velocity upper limit, this interrupt is asserted.
12 VLOWLMT_INT_M R/W 0 Velocity lower limit interrupt mask

0: Unmask

1: Mask
When a capture event happens and the velocity counter capture is less than the
velocity low limit, this interrupt is asserted.
11 RSVD N/A -- Reserved
10 VCCAP_INT_M R/W 0 Velocity counter capture interrupt mask

0: Unmask

1: Mask
When the velocity timer reaches zero, the value of velocity counter register and the
value of position counter are captured in capture registers. This interrupt is asserted
when the capture event is detected, and two capture registers are loaded.
9 PCE_INT_M R/W 0 Position counter error interrupt mask

0: Unmask

1: Mask
This interrupt is asserted when the index pulse signal is detected but the position
counter is not equal to 0.
This bit is valid only when the index pulse detection is enabled (depending on
IDX_EN)
8 IDX_INT_M R/W 0 Index pulse signal interrupt mask

0: Unmask

1: Mask
This interrupt is asserted when the index pulse signal present.
This bit is valid only when the index pulse detection is enabled (depending on
IDX_EN)
7 RUF_INT_M R/W 0 Rotation counter underflow interrupt mask

0: Unmask

1: Mask
This interrupt is asserted when the rotation counter underflow occurs(0

0xFFF).
6 ROF_INT_M R/W 0 Rotation counter overflow interrupt mask
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2019-05-15 10:08:03