Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
412
31:7
RSVD
N/A
-
Reserved
6
DCOL
R
0
Data Collision Error. Relevant only when the SPI is configured as a master device. This bit is set if the
SPI master is actively transmitting when another master selects this device as a slave. This informs
the processor that the last data transfer was halted before completion. This bit is cleared when
read.
0 – No error
1 – Transmit data collision error
5
TXE
R
0
Transmission Error. Set if the transmit FIFO is empty when a transfer is started. This bit can be set
only when the SPI is configured as a slave device. Data from the previous transmission is resent on
the txd line. This bit is cleared when read.
0
–
No error
1
–
Transmission error
4
RFF
R
0
Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO
contains one or more empty location, this bit is cleared.
0 – Receive FIFO is not full
1 – Receive FIFO is full
3
RFNE
R
0
Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared
when the receive FIFO is empty. This bit can be polled by software to completely empty the receive
FIFO.
0 – Receive FIFO is empty
1 – Receive FIFO is not empty
2
TFE
R
1
Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the
transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request
an interrupt.
0 – Transmit FIFO is not empty
1 – Transmit FIFO is empty
1
TFNF
R
1
Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is
cleared when the FIFO is full.
0 – Transmit FIFO is full
1 – Transmit FIFO is not full
0
BUSY
R
0
SSI Busy Flag. When set, indicates that a serial transfer is in progress; when cleared indicates that
the SPI is idle or disabled.
0 – SPI is idle or disabled
1 – SPI is actively transferring data
19.3.2.11
IMR
Name:
Interrupt Mask Register
Size:
6 bits: when SSI_IS_MASTER = 1
8 bits: when SSI_IS_MASTER = 0
Address offset
:
0x2C
Read/write access:
read/write
This read/write register masks or enables all interrupts generated by the SPI.
31
30
29
…
10
9
8
RSVD
7
6
5
4
3
2
1
0
SSRIM
TXUIM
MSTIM/FAEIM
RXFIM
RXOIM
RXUIM
TXOIM
TXEIM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Access
Reset
Description
31:8
RSVD
N/A
-
Reserved
7
SSRIM
R/W
1
SS_N Rising Edge Detect Interrupt Mask. This bit field is present only if the SPI is configured as
a serial-slave device.
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2019-05-15 10:08:03
