Direct Memory Access Controller (DMAC)
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
179
ii.
If the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking
interface to the source and destination peripheral; this requires programming the SRC_PER and DEST_PER bits,
respectively.
f)
If gather is enabled (parameter DMAH_CHx_SRC_GAT_EN = True and CTLx.SRC_GATHER_EN is enabled), program the SGRx register
for channel x.
g)
If scatter is enabled (parameter DMAH_CHx_DST_SCA_EN = True and CTLx.DST_SCATTER_EN), program the DSRx register for
channel x.
(4)
After the DMAC-selected channel has been programmed, enable the channel by writing a 1 to the ChEnReg.CH_EN bit. Ensure that bit 0
of the DmaCfgReg register is enabled.
(5)
Source and destination request single and burst DMA transactions in order to transfer the block of data (assuming non-memory
peripherals). The DMAC acknowledges at the completion of every transaction (burst and single) in the block and carries out the block
transfer.
(6)
Once the transfer completes, hardware sets the interrupts and disables the channel. At this time, you can respond to either the Block
Complete or Transfer Complete interrupts, or poll for the transfer complete raw interrupt status register (RawTfr[n], n = channel number)
until it is set by hardware, in order to detect when the transfer is complete. Note that if this polling is used, the software must ensure
that the transfer complete interrupt is cleared by writing to the Interrupt Clear register, ClearTfr[n], before the channel is enabled.
9.4.5.2
Multi-Block Transfer with Linked List for Source and Linked List for Destination (Row 10)
Note
: This type of multi-block transfer can only be enabled when either of the following parameters is set:
DMAH_CHx_MULTI_BLK_TYPE = NO_HARDCODE
DMAH_CHx_MULTI_BLK_TYPE = LLP_LLP
(1)
Read the Channel Enable register to choose a free (disabled) channel.
(2)
Set up the chain of Linked List Items (otherwise known as block descriptors) in memory. Write the control information in the LLI.CTLx
register location of the block descriptor for each LLI in memory (see Fig 9-45) for channel
x
. For example, in the register, you can program
the following:
a)
Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming
the TT_FC of the CTLx register. Table 9-17 lists the decoding for this field.
b)
Set up the transfer characteristics, such as:
Transfer width for the source in the SRC_TR_WIDTH field. Table 9-16 lists the decoding for this field.
Transfer width for the destination in the DST_TR_WIDTH field. Table 9-16 lists the decoding for this field.
Source master layer in the SMS field where the source resides.
Destination master layer in the DMS field where the destination resides.
Incrementing/decrementing or fixed address for the source in the SINC field.
Incrementing/decrementing or fixed address for the destination in the DINC field.
(3)
Write the channel configuration information into the CFGx register for channel x.
a)
Designate the handshaking interface type (hardware or software) for the source and destination peripherals; this is not required for
memory.
This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a 0 activates the hardware handshaking
interface to handle source/destination requests for the specific channel. Writing a 1 activates the software handshaking interface to
handle source/destination requests.
b)
If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the
source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively.
(4)
Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the last) are set as shown in Row 10 of Table 9-19. The
LLI.CTLx register of the last Linked List Item must be set as described in Row 1 or Row 5 of Table 9-19. Fig 9-45 shows a Linked List
example with two list items.
(5)
Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the last) are non-zero and point to the base address of
the next Linked List Item.
(6)
Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory point to the start source/destination block address
preceding that LLI fetch.
(7)
If parameter DMAH_CHx_CTL_WB_EN = True, ensure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI entries in
memory is cleared.
(8)
If source status fetching is enabled (DMAH_CHx_CTL_WB_EN = True, DMAH_CHx_STAT_SRC = True, and CFGx.SS_UPD_EN is enabled),
program the SSTATARx register so that the source status information can be fetched from the location pointed to by the SSTATARx. For
conditions under which the source status information is fetched from system memory, refer to the Write Back column of Table 9-19.
(9)
If destination status fetching is enabled (DMAH_CHx_CTL_WB_EN = True, DMAH_CHx_STAT_DST = True, and CFGx.DS_UPD_EN is
enabled), program the DSTATARx register so that the destination status information can be fetched from the location pointed to by the
Realtek confidential files
The document authorized to
SZ99iot
2019-05-15 10:08:03
