Direct Memory Access Controller (DMAC)
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
123
9.2.10.2.2
Case 2: SSI.DMATDLR = 6
Fig 9-40 illustrates the watermark levels in Case 2 where SSI.DMATDLR = 6.
Fig 9-40 Case 2 watermark levels where SSI.DMATDLR = 6
Case 2 uses the parameters listed in Table 9-13.
Table 9-13 Transmit watermark level – Case 2
Parameter
Description
SSI.DMATDLR = 6
SSI transmit FIFO watermark level
DMA.CTL
x
.DEST_MSIZE = SSI_TX_FIFO_DEPTH - SSI.DMATDLR = 2
DMA.CTL
x
.DEST_MSIZE is equal to the empty space in the transmit
FIFO at the time the burst request is made.
SSI_TX_FIFO_DEPTH = 8
SSI transmit FIFO depth
DMA.CTL
x
.BLOCK_TS = 30
Block size
The number of burst transactions in the block are:
DMA.CTL
x
.BLOCK_TS/DMA.CTL
x
.DEST_MSIZE = 30/2 = 15
In this block transfer, there are fifteen destination burst transactions in a DMA block transfer, but the watermark level, SSI.DMATDLR, is high.
Therefore, the probability of an SSI underflow is low because the DMAC has plenty of time to service the destination burst transaction request
before the SSI transmit FIFO becomes empty.
Thus, the second case has a lower probability of underflow at the expense of more burst transactions per block. This potentially provides a
greater amount of bursts per block and a worse bus utilization than the former case.
Therefore, the goal in choosing a watermark level is to minimize the number of transactions per block, while at the same time keeping the
probability of an underflow condition to an acceptable level. In practice, this is a function of the following ratio:
For example, promoting the channel to the highest-priority channel in the DMAC, and promoting the DMAC master interface to the highest-
priority master in the AHB layer, increases the rate at which the DMAC can respond to burst transaction requests. This in turn allows the user
to decrease the watermark level, which improves bus utilization without compromising the probability of an underflow occurring.
9.2.10.3
Selecting CTLx.DEST_MSIZE and Transmit FIFO Overflow
As can be seen from Fig 9-40, programming DMA.CTL
x
.DEST_MSIZE to a value greater than the watermark level that triggers the DMAC request
may cause overflow when there is not enough space in the SSI transmit FIFO to service the destination burst request. Therefore, the following
equation must be adhered to in order to avoid overflow:
DMA.CTL
x
.DEST_MSIZE <= SSI_TX_FIFO_DEPTH - SSI.DMATDLR
(13)
In “Case 2: SSI.DMATDLR = 6”, the amount of space in the transmit FIFO at the time the burst request is made is equal to the destination burst
length, DMA.CTL
x
.DEST_MSIZE. Thus, the transmit FIFO may be full, but not overflowed, upon completion of the burst transaction.
Therefore, for optimal operation, DMA.CTL
x
.DEST_MSIZE should be set at the FIFO level that triggers a transmit DMAC request; that is:
DMA.CTL
x
.DEST_MSIZE = SSI_TX_FIFO_DEPTH - SSI.DMATDLR
(14)
Realtek confidential files
The document authorized to
SZ99iot
2019-05-15 10:08:03
