Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
248
S
or
R
From slave
ACK
MSB
1
2
7
LSB
8
1
2
ACK
9
3-8
9
R or P
From Receiver
START or
RESTART
Condition
STOP and
RESTART
Condition
Fig 13-3 Data transfer on the I
2
C bus
The I
2
C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL line is low, except for STOP,
START, and RESTART conditions. The output drivers are open-drain or open-collector to perform wire-AND functions on the bus. The maximum
number of devices on the bus is limited by only the maximum capacitance specification of 400pF. Data is transmitted in byte packages.
13.2.3.1
START and STOP Generation
When operating as an I
2
C master, putting data into the transmit FIFO causes the Ameba-D I
2
C to generate a START condition on the I
2
C bus.
Writing a 1 to IC_DATA_CMD[9] causes the hardware to generate a STOP condition on the I
2
C bus; a STOP condition is not issued if this bit is
not set, even if the transmit FIFO is empty. Writing a 1 to IC_DATA_CMD[10] causes the hardware to hold bus after the current data is
transmitted and generate a RESTART condition when the next data in FIFO is ready to be transmitted on bus.
When operating as a slave, the Ameba-D I
2
C does not generate START and STOP conditions, as per the protocol. However, if a read request is
made to the Ameba-D I
2
C, it holds the SCL line low until read data has been supplied to it. This stalls the I
2
C bus until read data is provided to
the slave Ameba-D I
2
C, or the Ameba-D I
2
C slave is disabled by writing a 0 to bit0 of the REG_IC_ENABLE.
13.2.3.2
Combined Formats
The Ameba-D I
2
C supports mixed read and write combined format transactions in both 7-bit and 10-bit addressing modes.
The I
2
C does not support mixed address and mixed address format—that is, a 7-bit address transaction followed by a 10-bit address transaction
or vice versa—combined format transactions.
To initiate combined format transfers, IC_CON.IC_RESTART_EN should be set to 1. With this value set and operating as a master, when the I
2
C
completes an I
2
C transfer, it checks the transmit FIFO and executes the next transfer. If the direction of this transfer differs from the previous
transfer, the combined format is used to issue the transfer. If the transmit FIFO is empty when the current I
2
C transfer completes,
IC_DATA_CMD[9] is checked.
If set to 1, a STOP bit is issued.
If set to 0, the SCL is hold low until the next command is written to the transmit FIFO.
13.2.4
I
2
C Protocols
The I
2
C has the protocols discussed in this section.
13.2.4.1
START and STOP Conditions
When the bus is idle, both the SCL and SDA signals are pulled high through external pull-up resistors on the bus. When the master wants to
start a transmission on the bus, the master issues a START condition. This is defined to be a high-to-low transition of the SDA signal while SCL is
1. When the master wants to terminate the transmission, the master issues a STOP condition. This is defined to be a low-to-high transition of
the SDA line while SCL is 1. Fig 9-10 shows the timing of the START and STOP conditions. When data is being transmitted on the bus, the SDA
line must be stable when SCL is 1.
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2019-05-15 10:08:03
