Inter-IC Sound (I2S)
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473
I2S out
control
I2S
DAC/ADC
MCK
SCK
WS
SD0
SD1
SD2
Fig 22-2 I
2
S 5.1 channel audio-out interface configuration
22.4
Functional Description
22.4.1
Signal Lines
Signal lines in I
2
S data format are shown in Fig 1-3.
WORD
n
-1
Right Channel
WORD
n
+1
Right Channel
WORD
n
Left Channel
WS
SCK
SD
MSB
MSB
LSB
Fig 22-3 Signal lines in I
2
S data format
22.4.1.1
Serial Clock
Serial clock is a synchronous bit clock, every data bit has a pulse.
Serial clock is generated by internal in master mode and provided by external in slave mode
SCK rate = 2*sample rate*sample bit
22.4.1.2
Word Select
Word Select (WS) indicates the channel being transmitted:
WS = 0: Channel 1 (left)
WS = 1: Channel 2 (right)
There is no need to be symmetrical, it changes either on a trailing or leading edge of SCK.
In I
2
S data format, it changes one clock period before the MSB is transmitted.
Allow the slave transmitter to derive synchronous timing of the SD
Enable the receiver to store the previous data word and clear the input for the next data word
WS changes during a WS period. So the left channel data are transmitted when WS stays low and the right channel data are transmitted
when WS stays high.
In mono mode, WS changes as in stereo mode, but the difference is that there are no data transmitted when WS=1 (the right channel).
Frequency of WS equals to the sample rate.
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2019-05-15 10:08:03
