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Ameba-D User Manual

290

R_DCD

R_RI

R_DSR

R_CTS

D_DCD

TERI

D_DSR

D_CTS

Bit

Name

Access

Reset Description

31:8

RSVD

N/A

Reserved

R_DCD

Complement of the DCD input or equals to OUT2 (MCR[3]) in loopback mode.

R_RI

Complement of the RI input or equals to OUT1 (MCR[2]) in loopback mode.

R_DSR

Complement of the DSR input or equals to DTR (MCR[0]) in loopback mode.

R_CTS

Complement of the CTS input or equals to RTS (MCR[1]) in loopback mode.

D_DCD

Delta Data Carrier Detect (DDCD) indicator



1: The DCD line has changed its state.



0: Otherwise

TERI

Trailing Edge of Ring Indicator (TERI) detector.



1: The RI line has changed its state from low to high.



0: Otherwise.

D_DSR

Delta Data Set Ready (DDSR) indicator



1: The DSR line has changed its state.



0: Otherwise.

D_CTS

Delta Clear to Send (DCTS) indicator



1: The CTS line has changed its state.



0: Otherwise.

14.2.7

SCR



Name:

Scratch Pad Register



Size:

32 bits



Address offset:

0x001C



Read/write access:

read/write

RSVD

XFACTOR_ADJ[10:0]

R/W

XFACTOR_ADJ[10:0]

R/W

RSVD

DBG_SEL[3:0]

R/W

SCRATCH[7]

SCRATCH[6]

RSVD

PIN_LB_TEST

RSVD

R/W

Bit

Name

Access Reset

Description

31:27

RSVD

N/A

Reserved

26:16

XFACTOR_ADJ[10:0]

R/W

One factor of baud rate calculation for Tx path, that is the ovsr_adj[10:0] of the
baud rate formula.

15:12

RSVD

N/A

Reserved

11:8

DBG_SEL[3:0]

R/W

Debug port selection

SCRATCH[7]

R/W

Rx break signal interrupt status, Write 1 to clear.

SCRATCH[6]

R/W

Rx break signal interrupt enable

5:4

RSVD

N/A

Reserved

PIN_LB_TEST

R/W

For UART IP txd/rxd/rts/cts pin loopback test

2:0

RSVD

N/A

Reserved

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Summary of Contents for Ameba-D RTL872 D Series

Page 1: ...UM0400 Ameba D User Manual Realtek Semiconductor Corp No 2 Innovation Road II Hsinchu Science Park Hsinchu 300 Taiwan Tel 886 3 578 0211 Fax 886 3 577 6047 www realtek com...

Page 2: ...agrees that prior to using or distributing any systems that include Realtek s reference designs Customer will thoroughly test such systems and the functionality of such Realtek products used in such s...

Page 3: ...altek is a trademark of Realtek Semiconductor Corporation Other names mentioned in this document are trademarks registered trademarks of their respective owners USING THIS DOCUMENT Though every effort...

Page 4: ...d SRAM 27 2 6 KM4 Extension SRAM 27 2 7 Retention SRAM 27 2 8 SPI Flash Memory 27 2 9 PSRAM 27 3 Memory Protection Unit MPU 28 3 1 Register Map 28 3 2 Register Field Description 28 3 2 1 MPU_TYPE 28 3...

Page 5: ...6 2 5 Pad Shut Down 47 6 2 6 I2 C Open drain Mode 47 6 2 7 Audio Pad 47 6 3 Pin Multiplexing Function 48 6 4 Register PADCTRL 49 7 Inter Processor Communication IPC 51 7 1 Features 51 7 2 Functional D...

Page 6: ...ol Configurations 120 9 2 10 Peripheral Burst Transaction Requests 121 9 2 11 Generating Requests for the AHB Master Bus Interface 125 9 2 12 Arbitration for AHB Master Interface 127 9 2 13 Scatter Ga...

Page 7: ...on Circuit 233 11 2 3 Programmable Alarm 234 11 2 4 Write Protection 234 11 2 5 Digital Calibration 234 11 2 6 Day Threshold Program 235 11 3 Registers 235 11 3 1 RTC Time Register RTC_TR 235 11 3 2 R...

Page 8: ...troduction 284 14 1 1 Features 284 14 1 2 Block Diagram 284 14 2 Register 285 14 2 1 IER 286 14 2 2 IIR 286 14 2 3 LCR 287 14 2 4 MCR 288 14 2 5 LSR 289 14 2 6 MSR 289 14 2 7 SCR 290 14 2 8 STSR 291 1...

Page 9: ...16 2 2 Work Principle 315 16 2 3 FIFO Mechanism 318 16 2 4 Clock Configuration 318 16 2 5 Shadow Key Problem 319 16 3 Registers 321 16 3 1 KS_CLK_DIV 321 16 3 2 KS_TIM_CFG0 322 16 3 3 KS_TIM_CFG1 322...

Page 10: ...tion Modes 400 19 2 4 DMA Controller Interface 404 19 3 Registers 404 19 3 1 Register Memory Map 404 19 3 2 Registers and Field Descriptions 406 20 Liquid Crystal Display Controller LCDC 421 20 1 Over...

Page 11: ...22 4 Functional Description 473 22 4 1 Signal Lines 473 22 4 2 Operation Mode 474 22 4 3 Serial Data Standard 475 22 4 4 Clock Type 476 22 4 5 Memory Block 478 22 4 6 FIFO Allocation 478 22 5 Register...

Page 12: ...pt clear timing when GPIO_SYNC_PA_INTERRPUTS 0 and GPIO_INT_BOTH_EDGE 1 metastability Removed 68 Fig 8 14 Level sensitive interrupt RTL diagram 68 Fig 8 15 Active low level sensitive interrupt generat...

Page 13: ...g 9 49 Flowchart for DMA programming example 177 Fig 9 50 Multi block with linked address for source and destination 181 Fig 9 51 Multi block with linked address for source and destination where SARx...

Page 14: ...3 16 Master receiver Restart bit of IC_DATA_CMD is set 253 Fig 13 17 Master transmitter Stop bit of IC_DATA_CMD set Tx FIFO not empty 253 Fig 13 18 Master receiver Stop bit of IC_DATA_CMD set Tx FIFO...

Page 15: ...5 Fig 19 2 SPI Serial Format SCPH 0 397 Fig 19 3 SPI Serial Format Continuous Transfers SCPH 0 and SS toggling 397 Fig 19 4 SPI Serial Format Continuous Transfers SCPH 0 and SS not toggling 397 Fig 19...

Page 16: ...X_INV 1 position counter reset on PHA PHB 1 0 457 Fig 21 11 Auto index mechanism when IDX_INV 0 458 Fig 21 12 Auto index mechanism when IDX_INV 1 458 Fig 21 13 Rotation count when RC_MOD 1 459 Fig 21...

Page 17: ...t clear timing when GPIO_SYNC_PA_INTERRPUTS 0 and GPIO_INT_BOTH_EDGE 1 metastability Removed 68 Fig 8 14 Level sensitive interrupt RTL diagram 68 Fig 8 15 Active low level sensitive interrupt generati...

Page 18: ...Fig 9 49 Flowchart for DMA programming example 177 Fig 9 50 Multi block with linked address for source and destination 181 Fig 9 51 Multi block with linked address for source and destination where SAR...

Page 19: ...16 Master receiver Restart bit of IC_DATA_CMD is set 253 Fig 13 17 Master transmitter Stop bit of IC_DATA_CMD set Tx FIFO not empty 253 Fig 13 18 Master receiver Stop bit of IC_DATA_CMD set Tx FIFO no...

Page 20: ...395 Fig 19 2 SPI Serial Format SCPH 0 397 Fig 19 3 SPI Serial Format Continuous Transfers SCPH 0 and SS toggling 397 Fig 19 4 SPI Serial Format Continuous Transfers SCPH 0 and SS not toggling 397 Fig...

Page 21: ...INV 1 position counter reset on PHA PHB 1 0 457 Fig 21 11 Auto index mechanism when IDX_INV 0 458 Fig 21 12 Auto index mechanism when IDX_INV 1 458 Fig 21 13 Rotation count when RC_MOD 1 459 Fig 21 14...

Page 22: ...t reading this bit returns the reset value R W EC EC external clear Software can read and write to this bit hardware can also clear this bit R W ES ES external set Software can read and write to this...

Page 23: ...peline The KM0 coprocessor is an energy efficient and easy to use 32 bit core which is code compatible and tool compatible with the KM4 core The KM0 coprocessor offers up to 20MHz performance with a s...

Page 24: ...taneously A multilayer AXI bus matrix connects the CPU buses and other bus masters to peripherals in a flexible manner which can optimize performance because it allows peripherals on different slave p...

Page 25: ...MB External PSRAM 224MB External Memory Address 0x0800_0000 0x0FFF_FFFF 128MB External FLASH 0x1000_0000 0x1007_FFFF 512KB KM4 SRAM 256MB KM4 Memory Address 0x1008_0000 0x100D_FFFF 384KB RSVD 0x100E_0...

Page 26: ..._0000 0x400A_FFFF 192KB KM0 BRG Non Secure 0x0008_0000 0x0008_FFFF 64KB 0x000C_0000 0x000C_3FFF 16KB 0x4800_0000 0x4803_FFFF 256KB Flash Controller Non Secure 0x4808_0000 0x4808_0FFF 4KB Flash Memory...

Page 27: ...ceeding on to a second buffer The CPU then tends to access the data while the DMA is using the other RAM In power domains the entire SRAM is also divided into three blocks SRAM_PD1 up to 256KB SRAM_PD...

Page 28: ...o possible to define a default background memory Table 3 1 MPU entries CPU Secure Region Number KM4 Non Secure MPU x8 Secure MPU x4 KM0 Non Secure MPU x4 3 1 Register Map Table 3 2 provides the detail...

Page 29: ...for HardFaults NMIs and exception handlers when FAULTMASK is set to 1 Usage constraints Privileged access is permitted only Unprivileged access generates a BusFault This register is word accessible on...

Page 30: ...xecuting in Non Secure state and the debugger This register is banked between security states 31 30 29 10 9 8 7 6 5 2 1 0 RSVD REGION R W Bit Name Access Description 31 8 RSVD N A Reserved 7 0 REGION...

Page 31: ...ess to the limit address of the currently selected MPU region for the selected security state Usage constraints Privileged access is permitted only Unprivileged access generates a BusFault This regist...

Page 32: ...egion This value is zero extended to provide the base address to be checked against This field resets to an unknown value on a Warm reset 4 3 SH R W Shareability Defines the shareable domain of this r...

Page 33: ...nable 0 Region is disabled 1 Region is enabled This bit resets to 0 on a Warm reset 3 2 8 MPU_MAIR0 The MPU_MAIR0 characteristics are Purpose Along with MPU_MAIR1 provides the memory attribute encodin...

Page 34: ...ing in Non Secure state and the debugger This register is banked between security states Preface This register is reserved if no MPU regions are implemented in the corresponding security state 31 30 2...

Page 35: ...W Reserved 3 3 2 Inner When Outer 0000 Bit Name Access Description 7 4 Outer R W Outer attributes Specifies the Outer memory attributes The possible values of this field are 0000 Device memory 00RW N...

Page 36: ...d to KM4 NVIC at the same interrupt number like LOGUART and other KM0 interrupt signals are not linked to KM4 NVIC such as WDG RXI300 and IPC This mechanism enables KM4 to use KM0 s peripheral as it i...

Page 37: ...WDG_ISR_L KM4 KM0 watchdog warning interrupt 2 RXI300_IRQ_H RXI300_IRQ_L KM4 KM0 RXI300 platform interrupt 3 UART log UART log KM4 KM0 LP_UART0 LOGUART interrupt 4 GPIOA GPIOA KM4 KM0 GPIO PortA Inte...

Page 38: ...GDMA0_Channel4 N A KM4 HS_GDMA0_Channel4 interrupt 46 GDMA0_Channel5 N A KM4 HS_GDMA0_Channel5 interrupt 47 RSVD N A Reserved 48 RSVD N A Reserved 49 RSVD N A Reserved 50 IPSEC_S N A KM4 HS_IPSEC Trus...

Page 39: ...t Priority Register 6 This register contains the 3 bit priority fields for interrupt 24 to 27 IPR7 0x41C R W 0 Interrupt Priority Register 7 This register contains the 3 bit priority fields for interr...

Page 40: ...register The pending state of the interrupts can be set through the ISPR0 and ISPR1 registers The operation of read write to this register means that Write Writing 0 has no effect writing 1 changes th...

Page 41: ...gal disclaimers REALTEK 2019 All rights reserved 41 0xE000_EF00 31 9 RSVD Reserved Read value is undefined only 0 should be written 8 0 INTID Writing a value to this field generates an interrupt for t...

Page 42: ...at a programmable rate for example 1000Hz and invokes a SysTick routine A high speed alarm timer using the core clock A simple counter Software can use this to measure time completed and used An inter...

Page 43: ...ounter enable 1 The counter is enabled 0 The counter is disabled 5 3 2 SYST_RVR Name System Timer Reload Value Register Size 32 bits Address offset 0x014 Read write access read write This register is...

Page 44: ...s Reset Description 31 NOREF R 0 Indicates whether an external reference clock is available This bit is loaded from the SYST_CALIB register in SYSCON 0 A separate reference clock is available 1 A sepa...

Page 45: ...function and characteristics Each I O pin has a unique set of functional capabilities Not all pin characteristics are selectable on each pin For instance pins that have an I2C function can be configu...

Page 46: ...LS_DIO 2 2 4mA 4 8mA 50k 50k PB 4 PB 5 PB 6 PB 7 I2C HCZ816LFS_4P7K10K 15 4 8mA 8 16mA 4 7k 10k 4 7k 10k PA 29 PA 30 PA 31 PB 0 I2C PB 26 I2C PB 27 I2C PB 1 ADC PB 2 ADC PB 3 ADC RWDS HCZ816LFS_10K50K...

Page 47: ...n use this function to conserve power 6 2 6 I2 C Open drain Mode Pins that support I2C with specialized pad electronics have additional configuration bits These bits have multiple configurations to su...

Page 48: ...dec Register 0x03 bit 5 bit 7 to enable LINE IN mute by setting register 0x40010000 to 0x08A00301 Mute MIC IN and LINE IN Sets Audio Codec Register 0x03 bit 7 4 to enable MIC IN and LINE IN mute by se...

Page 49: ...GPIO If the column default pull is empty the state of GPIO is High Z after system power on If the column default pull isn t empty the GPIO pulls up down according to the default pull setting after sys...

Page 50: ...pad bit 11 bit 10 to control pad driving strength 00 2mA 01 4mA 10 8mA 11 16mA For PDC F G drives pad bit 11 bit 10 to control pull resistor value 1 select the small resistance and driving strength 0...

Page 51: ...cause up to 32 user defined interrupts to another core So there are five 32 bit registers for each processor IPCx_IER IPCx_IDR IPCx_IRR IPCx_ICR IPCx_ISR Each of the 32 bits of these registers repres...

Page 52: ...Free R W write 0 no effect 0 Free hardware will set CPUID when write 1 1 Occupied hardware will clear Free CPUID when owner CPU write 1 CPUID RO 1 KM4 0 KM0 F0 O0 Free 0 CPUID 0 Free 1 CPUID 1 Free F...

Page 53: ...t caused by this bit 0 Writing a 0 has no effect IPC0_CPUID 0x0010 RO KM0 CPUID Just IPC0 has this register 0 KM0 has got the lock 1 KM4 has got the lock IPCx_ISR 0x0014 RO KM0 KM4 Interrupt Status Re...

Page 54: ...send interrupt requests to the peer CPU This is intended to allow communication between CPUs For example one CPU can be handling certain peripherals and signaling another CPU when data is available Th...

Page 55: ...ault Description 31 0 IPC_ISRx RO 0 0 The corresponding interrupt source is not asserting the interrupt output currently 1 The corresponding interrupt source is asserting the interrupt output currentl...

Page 56: ...to the description of the IPC_SEM_FREE0 bit 11 IPC_SEM_CPUID5 R W 0 Refer to the description of the IPC_SEM_CPUID0 bit 10 IPC_SEM_FREE5 R W 0 Refer to the description of the IPC_SEM_FREE0 bit 9 IPC_S...

Page 57: ...ze 32 bits Address offset 0x0020 0x004C Read write access read write These are user defined register and can be used for H2L L2H command defined by user 31 30 29 28 27 4 3 2 1 0 User defined R W Bit N...

Page 58: ...from I O pads Auxiliary hardware data interface to or from auxiliary data sink or source Interrupt interface to or from interrupt controller Fig 8 1 Block diagram 8 1 2 Features GPIO supports the fol...

Page 59: ...g to a control register for the corresponding signal Also the device can be configured so that you can individually switch between hardware and software modes for each bit of each signal provided that...

Page 60: ...rdware mode is selected the value on aux_port_in output signal is equal to the value on the gpio_ext_portx input signal When software mode is selected the aux_portx_in output signal is always driven l...

Page 61: ...called raw status and after masking The interrupts are also combined into a single interrupt output signal which has the same polarity as the individual interrupts Either individual interrupts gpio_i...

Page 62: ...write to the gpio_intmask register to mask the interrupt before exiting the ISR If the ISR exits without masking or disabling the interrupt prior to exiting then the level sensitive interrupt repeated...

Page 63: ...The use of the debounce circuitry increases interrupt latency by two clock cycles of the debounce clock The debounce circuitry works with only asynchronous reset flip flops 8 2 2 2 Synchronization of...

Page 64: ..._PA_SYNC_INTERRUPTS If this parameter is a 1 the registers are included Fig 8 8 shows a timing diagram in which an interrupt is generated on the rising edge of an input on Port A this is where the deb...

Page 65: ...is cleared by a write to the interrupt clear register Fig 8 9 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS 0 metastability removed Note Since the Metastability regi...

Page 66: ...ling edge is available only when GPIO_INT_BOTH_EDGE 1 and this logic detects the interrupt on both the rising edge and the falling edge when the gpio_int_bothedge register is programmed to 1 Fig 8 11...

Page 67: ...grammed to detect both edges In this scenario debounce logic is disabled and metastability registers are included This figure also shows how an interrupt is cleared by a write to the interrupt clear r...

Page 68: ...iming when GPIO_SYNC_PA_INTERRPUTS 0 and GPIO_INT_BOTH_EDGE 1 metastability Removed 8 2 2 4 Level Sensitive Interrupts Fig 8 14 shows the generation of level sensitive interrupts As for edge detect in...

Page 69: ...troller block The gpio_intrclk_en output signal is asserted when level sensitive interrupts that are to be synchronized to pclk_intr are selected The gpio_intrclk_en signal can be used in the clock ge...

Page 70: ...ted GPIO_PWIDTH_B times if PIO_PORTB_SINGLE_CTL 0 gpio_swportc_dr 0x18 R W Port C data register Width GPIO_PWIDTH_C Reset Value GPIO_SWPORTC_RESET gpio_swportc_ddr 0x1c R W Port C data direction regis...

Page 71: ...x0 gpio_ext_portd 0x5c R Port D external port register Width GPIO_PWIDTH_D Reset Value 0x0 gpio_ls_sync 0x60 R W Level sensitive synchronization enable register Reset Value 0x0 gpio_id_code 0x64 R ID...

Page 72: ...served Read as zero Reserved GPIO_PWIDTH_A 1 0 Port A Data Direction Register R W Values written to this register independently control the direction of the corresponding data bit in Port A The defaul...

Page 73: ...cess Description 31 GPIO_PWIDTH_B Reserved Read as zero Reserved GPIO_PWIDTHB 1 0 Port B Data Register R W Values written to this register are output on the I O signals for Port B if the corresponding...

Page 74: ...bit of the signal can subsequently be changed by writing to the corresponding bit of this register This register is not available unless GPIO_HW_PORTB 1 Reset Value If GPIO_PORTB_SINGLE_CTL 1 then the...

Page 75: ...and control source for a signal can come from either software or hardware this bit selects between them The default source is configurable through the GPIO_DFLT_SRC_C configuration parameter 0 Softwa...

Page 76: ...d_ddr Name Port D Data Direction Size GPIO_PWIDTH_D Address offset 0x28 Read write access read write Bit Name Access Description 31 GPIO_PWIDTH_D Reserved Read as zero Reserved GPIO_PWIDTH_D 1 0 Port...

Page 77: ...GPIO_PWIDTH_D GPIO_DFLT_SRC_D in each bit 8 3 3 13 gpio_inten Name Interrupt enable Size GPIO_PWIDTH_A Address offset 0x30 Read write access read write This register is available only if Port A is co...

Page 78: ...rate interrupts GPIO_PORTA_INTR Include 1 Bit Name Access Description 31 GPIO_PWIDTH_A Reserved Read as zero Reserved GPIO_PWIDTH_A 1 0 Interrupt level R W Controls the type of interrupt that can occu...

Page 79: ...0x0 8 3 3 18 gpio_raw_intstatus Name Raw interrupt status Size GPIO_PWIDTH_A Address offset 0x44 Read write access read This register is available only if Port A is configured to generate interrupts...

Page 80: ...interrupt Size GPIO_PWIDTH_A Address offset 0x4C Read write access write This register is available only if Port A is configured to generate interrupts GPIO_PORTA_INTR Include 1 Bit Name Access Descr...

Page 81: ...ng this location reads the values on the signal When the data direction of Port B is set as Output reading this location reads the data register for Port B Reset Value 0x0 8 3 3 23 gpio_ext_portc Name...

Page 82: ...ntr 0 No synchronization to pclk_intr default 1 Synchronize to pclk_intr Reset Value 0x0 8 3 3 26 gpio_id_code Name GPIO ID code Size GPIO_ID_PWIDTH Address offset 0x64 Read write access read Bit Name...

Page 83: ...32_30_31_2A represents the version 2 01 Reset Value See the releases table in the Release Notes 8 3 3 29 gpio_config_reg1 Name GPIO Configuration Register 1 Size 32 bits Address offset 0x74 Read writ...

Page 84: ...of this register is derived from the GPIO_HW_PORTA configuration parameter 0 Exclude 1 Include 7 PORTD_SINGLE_CTL R The value of this register is derived from the GPIO_PORTD_SINGLE_CTL configuration p...

Page 85: ...ftware Registers The software registers are described in more details in Registers 8 4 2 Programming Considerations Reading from an unused location or unused bit sin a particular register always retur...

Page 86: ...e channel of the DMAC is required for each source destination pair In the most basic configurations as illustrated in Fig 9 2 the DMAC has one master interface and one channel The master interface rea...

Page 87: ...nation peripherals are on different AHB layers In this case you must configure the DMAC to have more than one master interface one per layer Fig 9 3 illustrates a DMAC with two master interfaces and a...

Page 88: ...data A memory peripheral can also generate SPLIT RETRY responses Channel Read write data path between a source peripheral on one configured AHB layer and a destination peripheral on the same or differ...

Page 89: ...ermines the length of a DMA block transfer and terminates it If you know the length of a block before enabling the channel then you should program the DMAC as the flow controller If the length of a bl...

Page 90: ...the end of each block to the value when the channel was first enabled Contiguous blocks Address between successive blocks is selected to be a continuation from the end of the previous block Scatter Re...

Page 91: ...tter Gather 9 1 3 3 Channel Buffering Single FIFO per channel for source and destination Configurable FIFO depth D flip flop based FIFO Automatic data packing or unpacking to fit FIFO width 9 1 3 4 Ch...

Page 92: ...plexers Pause mode not enabled Default master number changed to1 Number of masters is changed to1 9 2 1 Setup Operation of DMA Transfers Programming a Channel describes how to program the DMAC in orde...

Page 93: ...accomplished through memory mapped registers while hardware handshaking is accomplished using a dedicated handshaking interface Note Throughout the remainder of this document references to both sourc...

Page 94: ...t transactions and where possible fill or empty the channel FIFO in single bursts provided that the software has not limited the burst length The DMAC can also lock the arbitration for the master bus...

Page 95: ...eripheral that is the source or destination signals the last transaction in the block and when the amount of data left to be transferred in the destination source block is less than that which is spec...

Page 96: ...Input Burst transaction request from peripheral The DMAC always interprets the dma_req signal as a burst transaction request regardless of the level of dma_single This is a level sensitive signal onc...

Page 97: ...cle later as it senses that there is space in its FIFO The issue here is that there could be space for only a single entry that the first buffered write will consume The initiation of the second trans...

Page 98: ...a_finish 0 is asserted to indicate block completion Fig 9 10 Burst followed by Back to Back single transactions In the Single Transaction Region if an active level on dma_req and dma_single occur on t...

Page 99: ...d method of generating dma_req and dma_single for a source peripheral when the peripheral is not the flow controller The single_flag signal in Fig 9 13 is asserted when the source FIFO has at least on...

Page 100: ...triggering a destination burst request If it is guaranteed that data at some point will be extracted from the destination FIFO in the Single Transaction Region in order to trigger a dma_req then in th...

Page 101: ...k transfer is complete after this transaction is complete If dma_single is high in the same cycle then the last transaction is a single transaction If dma_single is low in the same cycle then the last...

Page 102: ...integer 11 9 2 8 Setting up Transfers Transfers are set up by programming fields of the CTLx and CFGx registers for that channel As shown in Fig 9 4 a single block is made up of numerous transactions...

Page 103: ...on peripheral is the flow controller and data pre fetching from the source is enabled CFGx FCMODE 0 Example 8 Block transfer when the destination peripheral is the flow controller and data pre fetchin...

Page 104: ...Transaction Region at any stage throughout the DMA transfer and the block transfer from the source and to the destination consists of burst transactions only 9 2 8 1 2 Example 2 Scenario Effect of DM...

Page 105: ...per block than Example 1 Recommendation To allow a burst transaction to complete in a single burst the DMAC channel FIFO depth should be large enough to accept an amount of data equal to an entire bu...

Page 106: ...until the block transfer has completed this is illustrated in Fig 9 21 Fig 9 21 Channel FIFO contents at times indicated in Fig 9 20 In this example block transfer each source or destination burst tra...

Page 107: ...us utilization and lower latency for block transfers Limiting a burst to a maximum length prevents the DMAC from saturating the AHB bus when the AHB system arbiter is configured to only allow changing...

Page 108: ..._burst_size_bytes In this example the block size is a multiple of the destination burst transaction length blk_size_bytes_dma dst_burst_size_bytes 48 16 integer The destination block is made up of thr...

Page 109: ...e source block transfer has completed In this example the DMAC completes the source block transfer using four single transactions from the source Now consider Case B in Fig 9 26 where the source perip...

Page 110: ...transfer to the destination the amount of data left to be transferred is less than dst_burst_size_bytes and the destination enters the Single Transaction Region Fig 9 27 shows one way in which the bl...

Page 111: ...data item of the four requested decoded value of DEST_MIZE 4 would be transferred to the destination in the burst transaction This is referred to as an Early Terminated Burst Transaction If a burst re...

Page 112: ...ceed like that shown in Fig 9 28 Fig 9 28 Block transfer up to time t4 At time t4 the src channel and destination FIFOs might look like that shown in Fig 9 29 Fig 9 29 Source DMAC channel and destinat...

Page 113: ...herefore system bus occupancy and usage can be improved by delaying the servicing of multiple requests until there is sufficient data space available in the FIFO to generate a burst rather than multip...

Page 114: ...source side 2 When the destination peripheral signals a last transaction there is not enough data in the channel FIFO to complete the last transaction to the destination The DMAC fetches just enough d...

Page 115: ...Y response is received over the hresp AHB bus to do otherwise would be a violation of the AMBA protocol This additional word that is fetched is effectively lost since it is not transferred to the dest...

Page 116: ...e the transfer parameters are as given in Table 9 10 Table 9 10 Transfer parameters Parameter Description CTLx TT_FC 3 b111 Peripheral to peripheral transfer with DMAC as flow controller CTLx BLOCK_TS...

Page 117: ...The DMAC asserts dma_finish 0 to the source peripheral at time T8 this has the same timing as dma_ack 0 The destination block transfer completes as previously described No data loss occurs Case 2b Dat...

Page 118: ...s one exception to this as outlined in Example 8 Enabling data pre fetching may reduce the latency of the DMA transfer when the destination is the flow controller Observation For a source peripheral t...

Page 119: ...nitiates a single transaction from the source The DMAC fetches a single source data item from the source peripheral and stores the eight bytes in the channel FIFO This single transaction completes at...

Page 120: ...peripheral the handshaking loop is as follows 1 Peripheral generates an interrupt that asserts dma_req 2 DMAC completes the burst transaction and generates an end of burst transaction interrupt IntSr...

Page 121: ...destination FIFO drops below some watermark level This section investigates the optimal settings of these watermark levels on the source and destination peripherals and their relationship to respectiv...

Page 122: ...d active edge of dma_req triggered when the number of valid data entries in the SSI transmit FIFO is equal to or below this field value In this situation the number of data items to be transferred in...

Page 123: ...watermark level is to minimize the number of transactions per block while at the same time keeping the probability of an underflow condition to an acceptable level In practice this is a function of t...

Page 124: ...receive FIFO fills with data overflow To prevent this condition the user must correctly set the watermark level 9 2 10 5 Choosing the Receive Watermark level Similar to choosing the transmit watermar...

Page 125: ...qual tohalf full Exceptions to this readiness occur During these exceptions a value of CTLx FIFO_MODE 0 is assumed The following are theexceptions Near the end of a burst transaction or block transfer...

Page 126: ...e DMA transfer level 9 2 11 1 3 Locking Levels If locking is enabled for a channel then locking of the AHB master bus interface at a programmed locking transfer level is activated when the channel is...

Page 127: ...cking may lead to deadlock where multiple channels are concurrently enabled and no channel can proceed with the DMA transfer This occurs only for configurations where DMAH_NUM_MASTER_INT 1 and DMAH_NU...

Page 128: ...o a destination transfer The destination address is incremented or decremented by a programmed amount the scatter increment when a scatter boundary is reached Fig 9 43 shows an example destination sca...

Page 129: ...ation scatter transfer As an example of gather increment consider the following SRC_TR_WIDTH 3 b 010 32 bit SGR SGC 0x04 source gather count CTLx SRC_GATHER_EN 1 source gather enabled SARx A0 starting...

Page 130: ...le if you were to drive dmah_big_endian_mN to 0 where N is the master number the AMBA layer to which that master interface is attached will be little endian Conversely if you were to drive dmah_big_en...

Page 131: ...Address Register Reg Exist Yes DAR0 0x008 R W 0x0 Channel 0 Destination Address Register Reg Exist Yes LLP0 0x010 R W 0x0 Channel 0 Linked List Pointer Register Reg Exist llp0_hc False llp0_hc DMAH_C...

Page 132: ...ource Status Register Reg Exist dnc 3 and sstat2 True DSTAT2 0x0d8 R W 0x0 Channel 2 Destination Status Register Reg Exist dnc 3 and dstat2 True SSTATAR2 0x0e0 R W 0x0 Channel 2 Source Status Address...

Page 133: ...x1b0 R W 0x0 Channel 4 Destination Scatter Register Reg Exist dnc 5 and dsr4 True SAR5 0x1b8 R W 0x0 Channel 5 Source Address Register Reg Exist dnc 6 DAR5 0x1c0 R W 0x0 Channel 5 Destination Address...

Page 134: ...atus Register Reg Exist dnc 8 and sstat7 True DSTAT7 0x290 R W 0x0 Channel 7 Destination Status Register Reg Exist dnc 8 and dstat7 True SSTATAR7 0x298 R W 0x0 Channel 7 Source Status Address Register...

Page 135: ...pe Reg Exist Yes Miscellaneous Registers DmaCfgReg 0x398 R W 0x0 DMA Configuration Register Reg Exist Yes ChEnReg 0x3a0 R W 0x0 DMA Channel Enable Register Reg Exist Yes DmaIdReg 0x3a8 R 0x0 DMA ID Re...

Page 136: ...descriptions for the individual registers 9 3 2 1 Configuration and Channel Enable Registers The channel registers consist of the following where x 0 to 7 DmaCfgReg Configuration Register ChEnReg Chan...

Page 137: ...er register for channel x SSTATx Source status register for channel x SSTATARx Source status address register for channelx The SARx DARx LLPx CTLx and CFGx channel registers should be programmed prior...

Page 138: ...ery destination transfer throughout the block transfer 9 3 2 2 3 Hardware Realignment of SAR DAR Registers In a particular circumstance during contiguous multi block DMA transfers the destination addr...

Page 139: ...hat stores the next linked list item resides 00 AHB master 1 01 AHB master 2 10 AHB master 3 11 AHB master 4 This field does not exist if the configuration parameter DMAH_CHx_LMS is not set to NO_HARD...

Page 140: ...k transfer asingle transaction is mapped to a single AMBA beat Width The width of the single transaction is determined by CTLx SRC_TR_WIDTH Once the transfer starts the read back value is the total nu...

Page 141: ...eset Value Configuration dependent TT_FC 0 1 b1 TT_FC 1 DMAH_CHx_FC 1 DMAH_CHx_FC 0 TT_FC 2 DMAH_CHx_FC 1 DMAH_CHx_FC 0 Dependencies If the configuration parameter DMAH_CHx_FC page 107 is set to DMA_F...

Page 142: ...eripheral FIFO with a fixed address then set this field to No change 00 Increment 01 Decrement 1x No change Note Incrementing or decrementing is done for alignment to the next CTLx SRC_TR_WIDTH bounda...

Page 143: ...DST_TR_WIDTH 000 1 001 4 010 8 011 16 100 32 101 64 110 128 111 256 Table 9 16 CTLx SRC_TR_WIDTH and CTLx DST_TR_WIDTH decoding CTLx SRC_TR_WIDTH TLx DST_TR_WIDTH Size bits 000 8 001 16 010 32 011 64...

Page 144: ...rved Address offset for x 0 to 7 DSTAT0 0x028 DSTAT1 0x080 DSTAT2 0x0d8 DSTAT3 0x130 DSTAT4 0x188 DSTAT5 0x1e0 DSTAT6 0x238 DSTAT7 0x290 Read write access read write After the completion of each block...

Page 145: ...2 9 DSTATARx Name Destination Status Address Register for Channel x Size 64 bits upper 32 bits are reserved Address offset for x 0 to 7 DSTATAR0 0x038 DSTATAR1 0x090 DSTATAR2 0x0e8 DSTATAR3 0x140 DST...

Page 146: ...9 See notes SRC_PER R W 0x0 Assigns a hardware handshaking interface 0 DMAH_NUM_HS_INT 1 to the source of channel x if the CFGx HS_SEL_SRC field is 0 otherwise this field is ignored The channel can th...

Page 147: ...amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination Data pre fetching is disabled 31 RELOA...

Page 148: ...re is active for source requests on this channel 0 Hardware handshaking interface Software initiated transaction requests are ignored 1 Software handshaking interface Hardware initiated transaction re...

Page 149: ...l register access which includes accessing registers that have been removed during DMAC configuration If DMAH_RETURN_ERR_RESP is set to False DMAC always returns an OK response The CTLx SINC field con...

Page 150: ...n Transaction Complete Interrupt This interrupt is generated after completion of the last AHB transfer of the requested single burst transaction from the handshaking interface on the destination side...

Page 151: ...n ClearDstTran ClearErr registers Note Write access is available to these registers for software testing purposes only Under normal operation writes to these registers are not recommended Bit Name Acc...

Page 152: ...1x1 to the MaskTfr register writes a 1 into MaskTfr 0 while MaskTfr 7 1 remains unchanged Writing hex 00xx leaves MaskTfr 7 0 unchanged Writing a 1 to any bit in these registers unmasks the correspond...

Page 153: ...tusTfr register 9 3 2 4 Miscellaneous DMAC Registers This section describes the following registers of the DMAC DmaIdReg DMAC ID DmaTestReg DMAC Test DMA Component ID Register DMAC Version ID 9 3 2 4...

Page 154: ...rs that have been removed during DMAC configuration If DMAH_RETURN_ERR_RESP is set to False DMAC always returns an OK response Bit Name Access Description 63 RSVD N A Reserved 62 60 CH7_FIFO_DEPTH R T...

Page 155: ...the DMAH_CH7_LOCK_EN coreConsultant parameter 0x0 FALSE 0x1 TRUE 41 CH7_SRC_GAT_EN R The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant parameter 0x0 FALSE 0x1 TRUE 40 C...

Page 156: ...parameters for Channel 5 Bits 31 0 include configuration parameters for Channel 6 Bit Name Access Description 63 RSVD N A Reserved 62 60 CH5_FIFO_DEPTH R The value of this register is derived from the...

Page 157: ...Consultant parameter 0x0 FALSE 0x1 TRUE 41 CH5_SRC_GAT_EN R The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant parameter 0x0 FALSE 0x1 TRUE 40 CH5_DST_SCA_EN R The value...

Page 158: ...R_1 0x1 MASTER_2 0x2 MASTER_3 0x3 MASTER_4 0x4 NO_HARDCODE 18 16 CH6_MAX_MULT_SIZE R The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant parameter 0x0 4 0x1 8 0x2 16 0x3 3...

Page 159: ...ived from the DMAH_CH6_DTW coreConsultant parameter 0x0 NO_HARDCODE 0x1 8 0x2 16 0x3 32 0x4 64 0x5 128 0x6 256 0x7 reserved 9 3 2 4 5 DMA_COMP_PA RAMS_4 Name DMAC Component Parameters Register 4 Size...

Page 160: ...x3 32 0x4 64 0x5 128 0x6 256 0x7 reserved 47 46 CH3_FC R The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter 0x0 DMA 0x1 SRC 0x2 DST 0x3 ANY 45 CH3_HC_LLP R The value o...

Page 161: ...6 0x3 32 0x4 64 0x5 128 0x6 256 0x7 reserved 31 RSVD N A Reserved 30 28 CH4_FIFO_DEPTH R The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant parameter 0x0 8 0x1 16 0x2 32...

Page 162: ...he DMAH_CH4_LOCK_EN coreConsultant parameter 0x0 FALSE 0x1 TRUE 9 CH4_SRC_GAT_EN R The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant parameter 0x0 FALSE 0x1 TRUE 8 CH4_...

Page 163: ...annel 1 Bits 31 0 include configuration parameters for Channel 2 Bit Name Access Description 63 RSVD N A Reserved 62 60 CH1_FIFO_DEPTH R The value of this register is derived from the DMAH_CH1_FIFO_DE...

Page 164: ...is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant parameter 0x0 FALSE 0x1 TRUE 40 CH1_DST_SCA_EN R The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant parameter 0x0...

Page 165: ...rom the DMAH_CH2_MULT_SIZE coreConsultant parameter 0x0 4 0x1 8 0x2 16 0x3 32 0x4 64 0x5 128 0x6 256 0x7 reserved 15 14 CH2_FC R The value of this register is derived from the DMAH_CH2_FC coreConsulta...

Page 166: ...s Address offset 0x3e8 Read write access read This is a constant read only register that contains encoded information about the component parameter settings The reset value depends on coreConsultant p...

Page 167: ...of this register is derived from the DMAH_CH0_DMS coreConsultant parameter 0x0 MASTER_1 0x1 MASTER_2 0x2 MASTER_3 0x3 MASTER_4 0x4 NO_HARDCODE 18 16 CH0_MAX_MULT_SIZE R The value of this register is...

Page 168: ...0_STW coreConsultant parameter 0x0 NO_HARDCODE 0x1 8 0x2 16 0x3 32 0x4 64 0x5 128 0x6 256 0x7 reserved 2 0 CH0_DTW R The value of this register is derived from the DMAH_CH0_DTW coreConsultant paramete...

Page 169: ...he value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant parameter 0x0 32 bits 0x1 64 bits 0x2 128 bits 0x3 256 bits 50 49 M2_HDATA_WIDTH R The value of this register is derive...

Page 170: ...Offset 0x3f8 Read Write Access Read This is the DMAC Component Version register which is a read only register that specifies the version of the packaged component in the upper 32 bits and the componen...

Page 171: ...aIdReg or DMA Component ID Register register isattempted The response to an illegal access is configured using the configurationparameter DMAH_RETURN_ERR_RESP When DMAH_RETURN_ERR_RESP is set to True...

Page 172: ...mory LLI accesses are always 32 bit accesses Hsize 2 aligned to 32 bit boundaries and cannot be changed or programmed to anything other than 32 bit even if the AHB master interface of the LLI supports...

Page 173: ...or Fig 9 47 Mapping of block descriptor LLI in memory to channel registers when DMAH_CHx_STAT_SRC set to true Fig 9 48 Mapping of block descriptor LLI in memory to channel registers when DMAH_CHx_STAT...

Page 174: ...nked List Linked List Yes Note Throughout this databook there are descriptions about fetching the LLI CTLx register from the location pointed to by the LLPx register This exact location is the LLI bas...

Page 175: ...are disabled CTLx INT_EN 0 or The channel block interrupt is masked MaskBlock n 0 where n is the channelnumber Channel suspension between blocks is used to ensure that the end of block ISR interrupt...

Page 176: ...the DMS field where the destinationresides ctlx 24 23 2 b00 v Incrementing address for the source in the SINC field ctlx 10 9 2 b00 vi Incrementing address for the destination in the DINC field ctlx...

Page 177: ...rue and CTLx SRC_GATHER_ENis enabled program the SGRx register for Channel1 5 If Scatter is enabled DMAH_CHx_DST_SCA_EN True and CTLx DST_SCATTER_EN is enabled program the DSRx register for Channel 1...

Page 178: ...lock transfer 1 Read the Channel Enable register to choose a free disabled channel 2 Clear any pending interrupts on the channel from the previous DMA transfer by writing tothe Interrupt Clear registe...

Page 179: ...e source in the SRC_TR_WIDTH field Table 9 16 liststhe decoding for this field Transfer width for the destination in the DST_TR_WIDTH field Table 9 16 lists the decoding for this field Source master l...

Page 180: ...rue then the CTLx 63 32 register is written out to system memory For conditions under which the CTLx 63 32 register is written out to system memory refer to the Write Back column of Table 9 19 The CTL...

Page 181: ...source and destination address are contiguous but where the amount of data to be transferred is greater than the maximum block size CTLx BLOCK_TS then this can be achieved using the type of multi bloc...

Page 182: ...have been cleared 3 Program the following channel registers a Write the starting source address in the SARx register for channelx b Write the starting destination address in the DARx register for cha...

Page 183: ...Hardware sets the block complete interrupt The DMAC then samples the row number as shown in Table 9 19 If the DMAC is in Row 1 then the DMA transfer has completed Hardware sets the transfer complete...

Page 184: ...ontrol device by programming the TT_FC of the CTLx register Table 9 17 lists the decoding for this field b Set up the transfer characteristics suchas i Transfer width for the source in the SRC_TR_WIDT...

Page 185: ...I LLPx and LLI CTLx registers are fetched The LLI SARx register although fetched is not used 18 Source and destination request single and burst DMAC transactions in order to transfer the block of data...

Page 186: ...reload bit This puts the DMAC into Row 1 as shown in Table 9 19 If the next block is not the last block in the DMA transfer then the source reload bit should remain enabled to keep the DMAC in Row 7 a...

Page 187: ...Clear any pending interrupts on the channel from the previous DMA transfer by writing tothe Interrupt Clear registers ClearTfr ClearBlock ClearSrcTran ClearDstTran andClearErr Reading the Interrupt Ra...

Page 188: ...ions to transfer the block of data assuming non memory peripherals The DMAC acknowledges on completion of each burst single transaction and carries out the blocktransfer 6 When the block transfer has...

Page 189: ...sfer flow is shown in Fig 9 58 Fig 9 58 DMA transfer flow for source address auto reloaded and contiguous destination address 9 4 5 6 Multi Block DMA Transfer with Linked List for Source and Contiguou...

Page 190: ...the LLI CTLx register locations of all LLIs in memory arecleared 9 If source status fetching is enabled DMAH_CHx_CTL_WB_EN True DMAH_CHx_STAT_SRC True and CFGx SS_UPD_EN is enabled program the SSTATAR...

Page 191: ...EN is enabled It is written to the SSTATx register location of the LLI pointed to by the previously saved LLPx LOCregister The DSTATx register is now written out to system memory if DMAH_CHx_CTL_WB_EN...

Page 192: ...l the CFGx FIFO_EMPTY bit until it indicates that the channel FIFO is empty 3 The ChEnReg CH_EN bit can then be cleared by software once the channel FIFO is empty When CTLx SRC_TR_WIDTH CTLx DST_TR_WI...

Page 193: ...his as a request to disable all channels You must poll ChEnReg and confirm that all channels are disabled by reading back 0 Note If the channel enable bit is cleared while there is data in the channel...

Page 194: ...ame KM4 TIM0 TIM1 TIM2 TIM3 KM0 TIM00 TIM01 TIM02 TIM03 Channels 1 1 Clock source 32kHz 32kHz Resolution 32 bit 32 bit Prescaler Counter mode Up Up One pulse mode PWM mode with polarity selection Stat...

Page 195: ...er No update event occurs until the UDIS bit has been written to 0 However the counter restarts from 0 In addition if the URS bit in the TIMx_CR register is set setting the UG bit generates an update...

Page 196: ...t each update event depending on the ARPE bit in the TIMx_CR register The update event is sent when the counter reaches the overflow and if the UDIS bit equals to 0 in the TIMx_CR register it can also...

Page 197: ...cally When the TRGI is transferred to inactive level from active level the counter is disabled automatically the CC0IF is set and the current counter value is copied to CCR0 field of the TIMx_CCR0 reg...

Page 198: ...a 8 bit programmable prescaler It can be used for a variety of purposes including measuring the pulse lengths of input signals input capture or generating output waveforms PWM Pulse lengths and wavef...

Page 199: ...e Compare Register 5 OC4 OC5 Capture Compare Register 17 OC17 Fig 10 5 PWM timer block diagram 10 3 4 Functional Description 10 3 4 1 Upcounting Mode This timer is a 16 bit counter with its related au...

Page 200: ...scaler can divide the counter clock frequency by any factor between 1 and 256 It is based on a 8 bit counter controlled through a 8 bit register in the TIMx_PSC register It can be changed on the fly a...

Page 201: ...ile writing new values to the preload registers No update event occurs until the UDIS bit has been written to 0 However the counter restarts from 0 as well as the counter of the prescaler but the pres...

Page 202: ...ming diagram internal clock divided by 1 CK_PSC Timer clock CK_CNT CEN 0034 0035 Counter register Updateinterrupt flag UIF 0036 0000 Counter overflow Updateevent UEV 0002 0003 0004 Fig 10 9 Counter ti...

Page 203: ...eevent UEV Fig 10 11 Counter timing diagram internal clock divided by N CK_PSC Timer clock CK_CNT CEN 31 32 33 34 Counter register Updateinterrupt flag UIF 35 36 00 04 Counter overflow Updateevent UEV...

Page 204: ...Period ARR 1 Duty cycle Where XTAL PSC 1 The PWM mode can be selected independently on each channel one PWM per OCx output by setting 0 in the OCxM bits in the TIMx_CCRx register You must enable the...

Page 205: ...mmable length after a programmable delay Starting the counter can be controlled through the active edge of TRGI Generating the waveform can be done in PWM mode You select One pulse mode by setting the...

Page 206: ...register TIMx_DIER 0x08 R W TIMx interrupt enable register TIMx_SR 0x0C R W TIMx status register TIMx_EGR 0x10 W TIMx event generation register TIMx_CNT 0x14 R W TIMx counter register RSVD 0x18 N A R...

Page 207: ...1 5 RSVD N A Reserved 4 ARPE R W 0 Auto reload preload enable 0 The TIMx_ARR register isn t buffered 1 The TIMx_ARR register isn t buffered 3 RSVD N A Reserved 2 URS R W 0 Update request source 0 Upda...

Page 208: ...Mx Event Generation Register TIMx_EGR Name TIMx event generation register x 0 1 2 3 Address offset 0x10 Reset value 0x00000000 Read write access write 31 30 29 28 27 5 4 3 2 1 0 RSVD UG W Bit Name Acc...

Page 209: ...er TIMx_EGR 0x10 W TIM4 event generation register TIMx_CNT 0x14 R W TIM4 counter register TIMx_PSC 0x18 R W TIM4 prescaler register TIMx_ARR 0x1C R W TIM4 auto reload register TIMx_CCR0 0x20 R W TIM4...

Page 210: ...IMx_ARR register isn t buffered 1 The TIMx_ARR register is buffered 3 RSVD N A Reserved 2 URS R W 0 Update request source 0 Update events can be Counter overflow Setting the UG bit 1 Counter overflow...

Page 211: ...ounter overflows It is cleared by software 0 UIF R W1C 0 Update interrupt flag 10 4 2 5 TIMx Event Generation Register TIMx_EGR Name TIM4 event generation register Address offset 0x10 Reset value 0x00...

Page 212: ...qual to fCK_PSC PSC 7 0 1 PSC contains the value to be loaded in the actual prescaler register at each update event including when the counter is cleared through the UG bit in the TIMx_EGR register 10...

Page 213: ...counter counts from 0 to ARR 10 4 3 TIM5 Registers The details of TIM5 registers are listed in Table 10 7 Table 10 7 TIM5 memory map Name Address Offset Access Description TIMx_EN 0x00 R W TIM5 enabl...

Page 214: ...T_STOP CNT_START R W W Bit Name Access Reset Description 31 17 RSVD N A Reserved 16 CNT_STS R 0 Counter working status 0 Counter is stopped 1 Counter is working 15 9 RSVD N A Reserved 8 CNT_RUN R 0 Co...

Page 215: ...ress offset 0x08 Reset value 0x00000000 Read write access read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD CC17IE CC16IE CC15IE R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC14IE...

Page 216: ...interrupt is disabled 1 CC4 interrupt is enabled 4 CC3IE R W 0 Capture compare 3 interrupt enable 0 CC3 interrupt is disabled 1 CC3 interrupt is enabled 3 CC2IE R W 0 Capture compare 2 interrupt enab...

Page 217: ...o CC0IF description 1 CC0IF R W1C 0 Capture compare 0 interrupt flag If channel CC0 is configured as output This flag is set by hardware when the counter matches the compare value It is cleared by sof...

Page 218: ...channel CC0 is configured as output CC0IF flag is set corresponding interrupt is sent if enabled If channel CC0 is configured as input The current value of the counter is captured in the CCR0 field o...

Page 219: ...me Access Reset Description 31 16 RSVD N A Reserved 15 0 ARR R W 0 ARR is the value to be loaded in the actual auto reload register It can be preloaded by setting the ARPE bit in the TIMx_CR register...

Page 220: ...on OC0 output If channel CC0 is configured as input CCR0 is the counter value transferred by the last input capture event TRGI Note Value must be 0 100 including 0 100 10 4 3 10 TIMx Capture Compare R...

Page 221: ...A Reserved 27 CC3M R W 0 Refer to CC0M description in TIMx_CCR0 26 CC3P R W 0 Refer to CC0P description in TIMx_CCR0 25 OC3PE R W 0 Refer to OC0PE description in TIMx_CCR0 24 CC3E R W 0 Refer to CC0E...

Page 222: ...TIMx_CCR0 10 4 3 15 TIMx Capture Compare Register 6 TIMx_CCR6 Name TIM5 capture compare register 6 Address offset 0x38 Reset value 0x00000000 Read write access read write 31 30 29 28 27 26 25 24 23 2...

Page 223: ...C8PE CC8E RSVD R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR8 R W Bit Name Access Reset Description 31 28 RSVD N A Reserved 27 CC8M R W 0 Refer to CC0M description in TIMx_CCR0 26 CC8P R W...

Page 224: ...to OC0PE description in TIMx_CCR0 24 CC10E R W 0 Refer to CC0E description in TIMx_CCR0 23 16 RSVD N A Reserved 15 0 CCR10 R W 0 Refer to CCR0 description in TIMx_CCR0 10 4 3 20 TIMx Capture Compare R...

Page 225: ...ister 13 Address offset 0x54 Reset value 0x00000000 Read write access read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD CC13M CC13P OC13PE CC13E RSVD R W R W R W R W 15 14 13 12 11 10 9...

Page 226: ...A Reserved 27 CC15M R W 0 Refer to CC0M description in TIMx_CCR0 26 CC15P R W 0 Refer to CC0P description in TIMx_CCR0 25 OC15PE R W 0 Refer to OC0PE description in TIMx_CCR0 24 CC15E R W 0 Refer to C...

Page 227: ...C0PE description in TIMx_CCR0 24 CC17E R W 0 Refer to CC0E description in TIMx_CCR0 23 16 RSVD N A Reserved 15 0 CCR17 R W 0 Refer to CCR0 description in TIMx_CCR0 10 5 Design Implementation 10 5 1 In...

Page 228: ...Operation Flow 10 6 1 Upcounting Mode Upcounting mode support TIM0 TIM5 The configuration flow is listed in Table 10 8 Table 10 8 Timers upcounting configuration flow Step What to do How to do Comment...

Page 229: ...ER 9 Clear CCxIF Write TIMx_SR The statistic process is repeated unless OPM bit is set in TIMx_CR 10 6 2 2 Pulse Mode 1 Pulse Number The pulse mode 1 configuration flow is shown in Table 10 10 Table 1...

Page 230: ...in TIMx_CCRx Configure the edge polarity of OCx CCxP in TIMx_CCRx 5 Set CCRx Configure CCRx in TIMx_CCRx 6 Initialize the counter Write 0x01 to TIMx_EGR set UG bit Generate UEV by software 7 Clear eve...

Page 231: ...eset all RTC registers are protected against possible parasitic write accesses As long as the supply voltage remains in the operating range the RTC never stops regardless of the device status that is...

Page 232: ...a for XTAL32K output is from XTAL40MHz When setting 0x4800_0004 13 12 01 and 0x4800_0004 8 0 the RTC clock source shall be 131kHz This channel can be selected when testing for the precision of 131kHz...

Page 233: ...the SDM module receives a xtal_valid signal from PMC and begins to do calibration When calibration has finished SDM gives a cal_done_100k signal to inform RTC to pull down the xtal_req_32k xtal_req_o...

Page 234: ...sitive calibration or masking negative calibration clock cycles at the output of the asynchronous prescaler clk_apre Positive and negative calibrations are selected by setting the DCS bit to 0 and 1 i...

Page 235: ...ALR 0x20 R W RTC 32K auto calibration register 11 3 1 RTC Time Register RTC_TR Name RTC time register Size 32 bits Address offset 0x00 Reset value 0x0000 0000 This register is the calendar time shadow...

Page 236: ...enabled 7 FMT R W 0 Hour format 0 24 hour day format 1 AM PM hour format 6 5 OSEL 1 0 R W 0 Output selection These bits are used to select the flag to be routed to RTC_OUT output 00 Output is disable...

Page 237: ...7 INIT R W 0 Initialization mode 0 Free running mode 1 Initialization mode used to program time and date register RTC_TR and prescaler register RTC_PRER Counters stop and start counting from the new...

Page 238: ...division factor fclk_spre fclk_apre PREDIV_S 1 11 3 5 RTC Calibration Register RTC_CALIBR Name RTC calibration register Size 32 bits Address offset 0x10 Reset value 0x0000 0000 This register is write...

Page 239: ...1 PM 21 20 HT 1 0 R W 0 Hour tens in BCD format 19 16 HU 3 0 R W 0 Hour units in BCD format 15 MSK1 R W 0 Alarm minute mask 0 Alarm set if the minute matches 1 Minutes don t care in alarm comparison...

Page 240: ...tialization mode only The ACAL_CNT 5 0 counter is cleared after exiting the initialization mode and waiting until RSF 1 in RTC_ISR register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD ACAL_CN...

Page 241: ...calendar counter is automatically loaded and the counting restarts after 4 RTCCLK cycles 8 Enable the RTC registers Write protection Write 0xFF into the RTC_WPR register RTC registers can no longer b...

Page 242: ...and BKP of the RTC_CR register Using SUB1H or ADD1H the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure In addition the...

Page 243: ...ammed time period unless the program refreshes the watchdog Interrupt mode The watchdog circuit generates a WDG interrupt on the expiry of a programmed time period unless the program refreshes the wat...

Page 244: ...fresh watchdog 23 17 RSVD N A 0 Reserved 16 WDT_EN_BIT R W 0 1 Enable watchdog timer 0 Disable watchdog timer 15 0 BIT_VNDR_DIVFACTOR R W 1 Dividing factor Watchdog timer counts with 32 768kHz DivFact...

Page 245: ...ctional Description This chapter describes the functional behavior of Ameba D I2C in more details 13 2 1 Overview The I2C bus is a two wire serial interface consisting of a serial data line SDA and a...

Page 246: ...s when I2C receives data from the bus Control Register Sync Module FIFO APB Interface DMA Interface DMA Parser Master Slave Filter Bus Monitor CLKRST Generator Detector Shift Register Address Match AP...

Page 247: ...master is responsible for generating the clock and controlling the transfer of data The slave is responsible for either transmitting or receiving data to from the master The acknowledgement of data is...

Page 248: ...ba D I2C or the Ameba D I2C slave is disabled by writing a 0 to bit0 of the REG_IC_ENABLE 13 2 3 2 Combined Formats The Ameba D I2C supports mixed read and write combined format transactions in both 7...

Page 249: ...2 10 bit Address Format During 10 bit addressing two bytes are transferred to set the 10 bit address The transfer of the first byte contains the following bit definition The first five bits bits 7 3...

Page 250: ...OP condition The slave must leave the SDA line high so that the master can abort the transfer If the master transmitter is transmitting data as shown in Fig 9 13 then the slave receiver responds to th...

Page 251: ...e master Fig 13 9 START BYTE transfer The START BYTE procedure is as follows 1 Master generates a START condition 2 Master transmits the START byte 0000 0001 3 Master transmits the ACK clock pulse Pre...

Page 252: ...D register Fig 13 12 shows the fields in IC_DATA_CMD Please refer to the register description for more detail information RESTART STOP CMD DATA REG_IC_DATA_CMD 7 0 8 9 10 Reserved 15 11 NULL_DAT 12 Fi...

Page 253: ...L FIFO EMPTY Data written into Tx FIFO S Data availability makes START condition A6 A5 A4 A3 A2 A1 A0 ACK W D6 D7 SR Master issues RESTART condition and generates new transmission This byte in Tx FIFO...

Page 254: ...trol until the first master sends a STOP condition and places the bus in an idle state Arbitration takes place on the SDA line while the SCL line is 1 The master which transmits a 1 while the other ma...

Page 255: ...neously This is achieved by ensuring that bit 6 IC_SLAVE_DISABLE and bit 0 IC_MASTER_MODE of the IC_CON register are never set to 0 and 1 respectively 13 2 8 1 Slave Mode Operation This section discus...

Page 256: ...gister If the RX_FULL interrupt has been masked due to setting IC_INTR_MASK 2 register to 0 or setting IC_TX_TL to a value larger than 0 then it is recommended that a timing routine be implemented for...

Page 257: ...R_MASTER bit field bit 12 4 Enable the I2C by writing a 1 in the IC_ENABLE register 5 Now write transfer direction and data to be sent to the IC_DATA_CMD register If the IC_DATA_CMD register is writte...

Page 258: ...e minimum ic_clk frequencies that the I2C supports for each speed mode and the associated high and low count values It should be noted that these limits apply to the I2C in both master and slave modes...

Page 259: ...tional built in DMA capability it has a handshaking interface to a DMA Controller to request and control transfers The APB bus is used to perform the data transfer to or from the DMA 13 2 11 1 1Enabli...

Page 260: ...set a correct value to DMA mode field before any further setup Both Master and Slave mode can use this DMA mode In 8 bit FIFO with DMA transfer control register mode transfer process is controlled by...

Page 261: ...TR_STAT 0x34 R I2C Raw Interrupt Status Register IC_RX_TL 0x38 R W I2C Receive FIFO Threshold Register IC_TX_TL 0x3C R W I2C Transmit FIFO Threshold Register IC_CLR_INTR 0x40 R Clear Combined and Indi...

Page 262: ...configuration parameter IC_SLAVE_DISABLE You have the choice of having the slave enabled or disabled after reset is applied which means software does not have to configure the slave By default the sla...

Page 263: ...is NOT engaged in any master tx rx operation IC_STATUS 5 0 AND I2C is enabled to operate in master mode IC_CON 0 1 AND there are NO entries in the Tx FIFO IC_STATUS 2 1 31 30 14 13 12 11 10 9 8 1 0 RS...

Page 264: ...fset 0x0C Read write access read write 31 30 29 5 4 3 2 1 0 RSVD IC_HS_MAR R W Bit Name Access Reset Description 31 3 RSVD N A Reserved 2 0 IC_HS_MAR R W 0x0 This bit field holds the value of the I2C...

Page 265: ...ansfer by sending receiving data bytes according to the value of the CMD bit If the Tx FIFO is empty the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIF...

Page 266: ...IC_FS_SCL_HCNT R W 0x3C This register must be set before any I2C bus transaction can take place to ensure proper I O timing This register sets the SCL clock high period count for fast speed It is used...

Page 267: ...ead write 31 30 29 18 17 16 15 14 13 2 1 0 RSVD IC_HS_SCL_LCNT R W Bit Name Access Reset Description 31 16 RSVD N A Reserved 15 0 IC_HS_SCL_LCNT R W 0x10 This register must be set before any I2C bus t...

Page 268: ...ize 32 bits Address offset 0x30 Read write access read write These bits mask their corresponding interrupt status bits This register is active low a value of 0 masks the interrupt whereas a value of 1...

Page 269: ...either by disabling I2C or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register I2C stores the received data in the Rx buffer 10 START_DET R 0x0 Indicates whether a START or RESTART condition has...

Page 270: ...goes to 0 this interrupt is cleared 2 RX_FULL R 0x0 Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register It is automatically cleared by hardware when buffer l...

Page 271: ...for 0 entry and a value of 255 sets the threshold for 255 entries 13 3 2 17 IC_CLR_INTR Name Clear Combined and Individual InterruptRegister Size 32 bits Address offset 0x40 Read write access read onl...

Page 272: ...egister to clear the TX_OVER interrupt bit 3 of the IC_RAW_INTR_STAT register 13 3 2 21 IC_CLR_RD_REQ Name Clear RD_REQ InterruptRegister Size 32 bits Address offset 0x50 Read write access read only 3...

Page 273: ...RSVD CLR_ACTIVITY R Bit Name Access Reset Description 31 1 RSVD N A Reserved 0 CLR_ACTIVITY R 0x0 Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore If the I2C modul...

Page 274: ...IC_RAW_INTR_STAT register 13 3 2 28 IC_ENABLE Name I2C Enable Register Size 32 bits Address offset 0x6C Read write access read write 31 30 29 4 3 2 1 0 RSVD ABORT ENABLE R W R W Bit Name Access Reset...

Page 275: ...is completely full this bit is set When the receive FIFO contains one or more empty location this bit is cleared 0 Receive FIFO is not full 1 Receive FIFO is full 3 RFNE R 0x0 Receive FIFO Not Empty T...

Page 276: ...VD N A Reserved 4 0 RXFLR R 0x0 Receive FIFO Level Contains the number of valid data entries in the receive FIFO 13 3 2 32 IC_SDA_HOLD Name I2C SDA Hold Time Length Register Size 32 bits Address offse...

Page 277: ...send a START Byte Master 8 ABRT_HS_NORSTRT R 0x0 1 The restart is disabled IC_RESTART_EN bit IC_CON 5 0 and the user is trying to use the master to transfer data in High Speed mode Master Transmitter...

Page 278: ...r data byte received 0 Generate NACK ACK normally 13 3 2 35 IC_DMA_CR Name DMA Control Register Size 32 bits Address offset 0x88 Read write access read write There is a separate bit for transmit and r...

Page 279: ...38 IC_SDA_SETUP Name I2C SDA Setup Register Size 32 bits Address offset 0x94 Read write access read write This register controls the amount of time delay in terms of number of ic_clk clock periods int...

Page 280: ...e 2 SLV_RX_DATA_LOST R 0x0 Slave Received Data Lost This bit indicates if a Slave Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC...

Page 281: ...I2C acts as a slave It controls only the direction when it acts as a master 1 Read 0 Write 4 1 RSVD N A Reserved 0 DMODE_ENABLE R W 0x0 1 Set to enable DMA mode clear when transfer is done 13 3 2 42...

Page 282: ...31 30 29 3 2 1 0 RSVD IC_CLR_ADDR_MATCH R Bit Name Access Reset Description 31 1 RSVD N A Reserved 0 IC_CLR_ADDR_MATCH R 0x0 Read this register to clear the slave mode address match interrupt bit 12 o...

Page 283: ...efine frequency range of filter A greater value of DIG_FLTR_DEG results in a slower transfer speed and hardware would be able to filter a lower frequency 13 3 2 48 IC_COMP_VER Name I2C Component Versi...

Page 284: ...it 7 8 data bits 0 1 parity bit and 1 2 stop bits Very wide range of baud rate APB3 bus interface Auto flow control Interrupt control Infrared data association IrDA Loop back mode for test Separated c...

Page 285: ...0_E000 Table 14 1 Register map of UART Name Address Offset Access Description IER 0x0004 R W Enable Interrupt Register IIR 0x0008 RO Interrupt Identification Register LCR 0x000C R W Line Control Regis...

Page 286: ...rved 5 ETOI R W 0 Enable Rx Timeout Interrupt 0 Disabled 1 Enabled 4 EMDI R W 0 Enable Rx Path Monitor Done Interrupt 0 Disabled 1 Enabled 3 EDSSI R W 0 Enable Modem Status Interrupt EDSSI modem statu...

Page 287: ...t Source Tx FIFO empty Interrupt Reset Control Writing to the Tx FIFO THR or reading the IIR if source of interrupt 3 b000 Interrupt Priority 4th priority Interrupt Type Modem Status Interrupt Source...

Page 288: ...ion 0 Data is 7 bits word length 1 Data is 8 bits word length 14 2 4 MCR Name Modem Control Register Size 32 bits Address offset 0x0010 Read write access read write 31 30 7 6 5 4 3 2 1 0 RSVD AUTOFLOW...

Page 289: ...4 BREAK_ERR_INT R 0 Break Interrupt BI indicator 0 No break condition in the current character 1 Sets to logic 1 whenever the received data input is held in the spacing logic 0 state for a longer than...

Page 290: ...Set Ready DDSR indicator 1 The DSR line has changed its state 0 Otherwise 0 D_CTS R 0 Delta Clear to Send DCTS indicator 1 The CTS line has changed its state 0 Otherwise 14 2 7 SCR Name Scratch Pad R...

Page 291: ...ly 31 30 29 10 9 8 RSVD 7 6 5 4 3 2 1 0 RXDATABIT7 RXDATABIT6 RXDATABIT5 RXDATABIT4 RXDATABIT3 RXDATABIT2 RXDATABIT1 RXDATABIT0 R R R R R R W R Bit Name Access Reset Description 31 8 RSVD N A Reserved...

Page 292: ...ription 31 25 RSVD N A Reserved 24 DUMMY_FLAG R W1C 0 This bit is set when master reads dummy data from UART Rx FIFO it can be cleared by software by writing the bit 23 16 DUMMY_DATA R W 0 When UART i...

Page 293: ...ulse change the value 15 LOWBOUND_SHIFTRIGHT R W 0 0 Shift left minus offset value of txplsr 14 0 1 Shift right plus offset value txplsr 14 0 14 0 TXPULSE_LOWBOUND_SHIFTVAL R W 0 The shift value of SI...

Page 294: ...s Address offset 0x003C Read write access read only 31 30 29 28 3 2 1 0 DBG_UART R Bit Name Access Reset Description 31 0 DBG_UART R 32 he40000dc Debug port output value 14 2 16 REG_RX_PATH_CTRL Name...

Page 295: ...one monitor period to get the average clock cycles of one bit the max value is 127 0 R_MON_BAUD_EN R W 0 Function enable of monitoring Rx baud 14 2 18 REG_MON_BAUD_STS Name Baud Rate Monitor Status Re...

Page 296: ...FO Control Register Size 32 bits Address offset 0x0054 Read write access read write 31 30 29 10 9 8 RSVD 7 6 5 4 3 2 1 0 RXFIFO_TRIGGER_LEVEL RSVD DMA_MODE CLEAR_TXFIFO CLEAR_RXFIFO RPT_ERR R W R W W1...

Page 297: ...less than 2 Rx path with XTAL 40MHz clock can be selected and it can support higher baud rate If maximum sum of E1 and E2 is large 2 4 Rx path with OSC 2MHz clock shall be selected baud rate that it s...

Page 298: ...382400 1384083 0 1217 1444400 1444043 0 0247 1500000 1598127 0 1249 1843200 1843318 0 0064 2000000 2000000 0 2100000 2105263 0 2506 2764800 2758621 0 2235 3000000 3007519 0 2506 3250000 3252033 0 0626...

Page 299: ...cifications Signaling Rate Modulation Rate Tolerance Pulse Duration Pulse Duration Pulse Duration 2 4kbit s RZI 0 87 1 41us 78 13us 88 85us 9 6kbit s RZI 0 87 1 41us 19 53us 22 13us 19 2kbit s RZI 0 8...

Page 300: ...he current transmission is completed before the transmitter stops When Rx FIFO is almost full nRTS is deasserted to inform peer device to stop transmission at the end of current transmission 14 3 5 In...

Page 301: ...aracter comes in for rx_timeout_thres time after the last Rx character Fig 14 7 gives the DMA interface timing diagram on condition that block size isn t multiple of burst transaction size T1 and T2 a...

Page 302: ...r module the carrier is filtered by the IR receiver module So there isn t carrier on the IR Rx input signal To simplify the IR signal model a serial of IR signals is divided into several symbols A sym...

Page 303: ...shown in Fig 15 3 Space symbol IR signal Software de modulation OR IR signal Fig 15 3 IR Rx flow 15 1 2 Features Wide range of carrier frequency from 25kHz to 500kHz Customizable duty by users Option...

Page 304: ...R_INT When Rx FIFO is empty reading data from Rx FIFO triggers this interrupt IR_RX_CNT_THR_INT When given input level duration exceeds Rx counter threshold this interrupt is triggered IR_RX_FIFO_OF_I...

Page 305: ...sample clock 1 For example sample clock 100MHz IR_DIV_NUM 0 sample clock 50MHz IR_DIV_NUM 1 15 3 2 IR Tx Registers 15 3 2 1 IR_TX_CONFIG Name IR Tx configuration register Size 32 bits Address offset 0...

Page 306: ...upt 0 Disable 1 Enable 3 IR_TX_FIFO_LEVEL_INT_MASK R W 0x0 Tx FIFO level interrupt 0 Unmask 1 Mask 2 IR_TX_FIFO_EMPTY_INT_MASK R W 0x0 Tx FIFO empty interrupt 0 Unmask 1 Mask 1 IR_TX_FIFO_LEVEL_INT_EN...

Page 307: ...cess read write 31 30 29 28 15 14 13 12 11 10 9 2 1 0 RSVD TX_COMPE_DIV R W Bit Name Access Reset Description 31 12 RSVD N A 0 Reserved 11 0 TX_COMPE_DIV R W 0 IR_TX_CLK_Period SCLK TX_COMPE_DIV 1 15...

Page 308: ...read write 31 30 29 28 27 26 25 24 RSVD IR_RX_START IR_RX_START_M ODE IR_RX_MAN_STA RT IR_RX_TRIGGER_MODE R W R W R W R W 23 22 21 20 19 18 17 16 IR_RX_FILTER_STAGETX RSVD IR_RX_FIFO_ERR OR_INT_MASK I...

Page 309: ...O full interrupt 0 Unmask 1 Mask 13 IR_RX_FIFO_DISCARD_SET R W 0x0 When FIFO is full new data is send to FIFO 0 Discard oldest data in FIFO 1 Reject new data sending to FIFO 12 8 IR_RX_FIFO_LEVEL_TH R...

Page 310: ...SVD N A 0 Reserved 5 IR_RX_FIFO_ERROR_INT_STATUS R 0x0 Rx FIFO error read interrupt status When Rx FIFO is empty reading the Rx FIFO triggers this interrupt 0 Interrupt is inactive 1 Interrupt is acti...

Page 311: ...R_RX_FIFO_LEVEL_INT_CLR WC Rx FIFO level interrupt Write 1 to clear 0 IR_RX_FIFO_FULL_INT_CLR WC Rx FIFO full interrupt Write 1 to clear 15 3 3 4 IR_RX_CNT_INT_SEL Name IR clock division register Size...

Page 312: ...receiver application For RCU application except for sending IR signals Ameba D also supports IR learning function For receiver application Ameba D supports IR diode input and module input 15 4 1 RCU...

Page 313: ...configure register 2 Disable all interrupt 3 Set sample clock use IR_CLK_DIV 4 Set IR Rx work in auto mode and configure IR_RX_TRIGGER_MODE 5 Set Rx FIFO threshold if needed 6 Clear all interrupt 7 Se...

Page 314: ...ble rows and columns of keypad array Hardware debounce with configurable time at each scan Configurable Scan Clock Scan Interval and Release Time Interrupts interrupts mask interrupts clear interrupts...

Page 315: ...ine then scans all rows to determine which keys are being pressed and then second column is output low until the last column Firstly scan circuit waits for a first debounce time and does first scan Th...

Page 316: ...ce Timer Any Key Pressed Yes No The Second Scan Full Scan Valid Key Scan Interval Timer Send Key Data to FIFO Release Timer Any Key Pressed No AllReleaseInterrupt No Valid Key Key Values of theFirst S...

Page 317: ...event is stored in the key event FIFO only once in each key press and release operation 16 2 2 2 Regular Scan Mode In Regular Scan Mode at each full scan any key press event is stored in the key even...

Page 318: ...is pushed into the FIFO an overflow interrupt is triggered When FIFO is empty and is read an overread interrupt is triggered The key value assignment is listed in Table 16 1 Table 16 1 Key value assi...

Page 319: ...y combinations such as Ctrl Alt Del or any other combinations must ensure that the three keys are wired in appropriate key positions to avoid shadow key or appearing like a 4th key has been pressed To...

Page 320: ...a low signal at both Row0 and Row1 This falsely triggers key 22 as being pressed the key highlighted as yellow The reason for this is that keypad matrices short the columns to the rows connected toget...

Page 321: ...KS_COL_CFG 0x14 R W Configure keypad columns KS_ROW_CFG 0x18 R W Configure keypad rows KS_DATA_NUM 0x1C R Number of data in FIFO KS_DATA 0x20 R Indicate key and key event KS_IMR 0x24 R W Configure mas...

Page 322: ...for key column pre guard time scan_clk KS_PRE_GUARD_TIMER 15 12 RSVD N A Reserved 11 0 KS_DEB_TIMER R W 0x0 Debounce timer debounce timer scan_clk KS_DEB_TIMER 1 Debounce timer ranges from 100ns to 1...

Page 323: ...cess read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD KS_FIFO_LIMIT_LEVEL RSVD KS_FIFO_TH_LEVEL R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD KS_FIFO_ OV_CTRL KS_FIFO _CLR R W W1C...

Page 324: ...access read write 31 30 29 28 27 26 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD KS_ROW_SEL R W Bit Name Access Reset Description 31 8 RSVD N A Reserved 7 0 KS_ROW_SEL R W 0x0 Define which row is used 0b00000...

Page 325: ...eas a value of 1 unmasks the interrupt 31 30 29 9 8 7 RSVD 6 5 4 3 2 1 0 KS_SCAN_EVENT_I NT_MASK KS_FIFO_LIMIT_IN T_MASK KS_FIFO_OV_INT_ MASK KS_FIFO_FULL_INT _MASK KS_SCAN_FINISH_INT _MASK KS_FIFO_NO...

Page 326: ...because this interrupt is automaticlly cleared by hardware 0 KS_ALL_RELEASE_INT_CLR W1C Clear all release interrupt flag Write 1 to clear 16 3 12 KS_ISR Name Key Scan Masked Interrupt Status Register...

Page 327: ...raw interrupt status KS_FIFO_OV_RAW_INT_STATUS is triggered when FIFO is completely full 16 entries and there is another event is sent into it At this time whether to reject the new scan data or disca...

Page 328: ...RSVD N A Reserved 15 8 DUMMY_H R W 0xFF Dummy_h 7 2 DUMMY_L R W 0x0 Dummy_l 1 KS_DISCHARGE R W 0x0 Discharge the column spurious capacitance 0x1 Enable the discharge of the column spurious capacitance...

Page 329: ...er etc Ameba D audio codec supports the highest 96kHz sampling frequency and 24 bit resolution while transmits record data to or receives playback data from platform through I2S bus Ameba D platform c...

Page 330: ...stereo single ended line input 1 stereo single ended output or 1 stereo cap less output or 1 stereo differential output ADC SNR 88dB for line input to ADC path AVCC 2 8V THD N 80dB for line input to A...

Page 331: ...programmable gain DAC Path ASRC Asynchronous Sampling Rate Converter is required if acting as a I2S PCM slave device 5 band bi quad EQ for speaker frequency response compensation DC remover HPF Dithe...

Page 332: ...V 1 7 2 8 3 0 V Digital supply voltage DVDD 0 99 1 1 1 21 V 17 4 2 ADC Path The ADC path electrical characteristics are illustrated in Table 17 4 Table 17 4 ADC path electrical characteristics Item Co...

Page 333: ...mode the N end of L R channel outputs common level voltage while P end drives the available analog audio signal When earphone inserts into the jack the ground must short with N end output for audio si...

Page 334: ...The single end mode connection with a headphone jack is shown in Fig 17 4 Ameba D g m g s s g ground m mic s ear speaker MICBIAS MIC_P LOUT_P ROUT_P Fig 17 4 Single end mode connection with headphone...

Page 335: ...CBIAS provides the mic phone bias voltage Ameba D MIC_P Analog MIC OUTPUT GND MICBIAS Fig 17 6 Analog MIC single end mode connection Ameba D MIC_P Analog MIC OUTPUT MICBIAS MIC_N OUTPUT Fig 17 7 Analo...

Page 336: ...to rising falling edge Ameba D DMIC_CLK VDD Digital MIC CLOCK GND DMIC_DATA DATA L R VDD Fig 17 8 Digital MIC mono mode connection Ameba D DMIC_CLK VDD Digital MIC CLOCK GND DMIC_DATA DATA L R VDD Dig...

Page 337: ...a 1MHz PDM clock is used AmebaD I2S_BCLK 0 1uF VDD Digital MIC CLOCK GND MICBIAS I2S_DI DATA L R External I2S Fig 17 12 I2S acting as PDM 17 6 Registers 17 6 1 Analog Part 17 6 1 1 0x00 Address Bit Na...

Page 338: ...dphone right channel cap less negative depop mode control 1 b0 No depop 1 b1 Depop 15 HPO_CLPDPL R W 1 b0 Headphone left channel cap less positive depop mode control 1 b0 No depop 1 b1 Depop 17 6 1 2...

Page 339: ...depop mode control 1 b0 No depop 1 b1 Depop 17 6 1 3 0x02 Address Bit Name Access Reset Description 0x02 1 0 HPO_ML R W 2 b00 Headphone left channel mute control mute 0 DAC mute 1 Analog in 1 b0 Un m...

Page 340: ...s Reset Description 0x03 1 0 MICBST_GSELL R W 2 b00 MICBST left channel gain select 2 b00 0dB 2 b01 20dB 2 b10 30dB 2 b11 40dB 3 2 MICBST_GSELR R W 2 b00 MICBST right channel gain select 2 b00 0dB 2 b...

Page 341: ...5 RSVD N A 11 h0 Reserved 17 6 2 2 0x0F Address Bit Name Access Reset Description 0x0F 0 SIDETONE_HPF_EN R W 1 b0 Sidetone processing enable control 1 b1 Enable sidetone HPF processing 1 b0 Disable s...

Page 342: ...2S 3 b010 Left Justified 3 b100 PCM mode A 3 b110 PCM mode B 3 b101 PCM mode A N 3 b111 PCM mode B N 3 2 I2S_DATA_FORMAT_SEL R W 2 b00 5 4 I2S_DATA_LEN_SEL R W 2 b00 2 b00 16 bits 2 b10 24 bits 2 b11...

Page 343: ...b1 analog ADC input path mute control Left Channel 1 b0 Un Mute 1 b1 Mute 13 ADC_L_DMIC_MIX_MUTE R W 1 b1 DMIC input path mute control Left Channel 1 b0 Un Mute 1 b1 Mute 14 ADC_L_AD_DCHPF_EN R W 1 b1...

Page 344: ...C_L_ADJ_HPF_COEF_NUM R W 6 h00 coefficient fine select 0 63 12 6 ADC_L_AD_GAIN R W 7 h2F ADC digital volume 17 625dB 30dB in 0 375dB step 7 h00 17 625dB 7 h2f 0dB 7 h30 0 375dB 7 h7f 30dB 15 13 RSVD N...

Page 345: ...s filter enable control 1 b0 Disable 1 b1 Enable 5 3 ADC_R_ADJ_HPF_COEF_SEL R W 3 b000 Coefficient coarse select fc range num 0 num 63 3 b000 fs 8k or 16k corresponding fc 20 2000Hz 40 4000Hz 3 b001 f...

Page 346: ...ATE R W 4 h0 Set DAC sample rate 4 h0 48K 4 h1 96K 4 h2 Reserved 4 h3 32K 4 h4 Reserved 4 h5 16K 4 h6 Reserved 4 h7 8K 4 h8 44 1K 4 h9 88 2K 4 hA 4 hF Reserved 7 4 ADC_SAMPLE_RATE R W 4 h0 Set ADC sam...

Page 347: ...b1 Turn on clock 6 ST_EN R W 1 b0 Set sidetone clock 1 b0 TURN off clock and reset 1 b1 turn on clock 7 AD_L_EN R W 1 b0 Set ADC filter left channel clock 1 b0 Turn off clock and reset 1 b1 Turn on cl...

Page 348: ...EN R W 1 b1 Set 48k 128 clock 1 b0 Disable 1 b1 Enable 12 GEN_SRC_8K128_EN R W 1 b1 Set 8k 128 clock 1 b0 Disable 1 b1 Enable 13 AD_ANA_CLK_SEL R W 1 b0 Set clk_ad_ana phase reference clk_da_ana 1 b0...

Page 349: ...32us 5 h12 21 85s 15 11 ALC_ATK_SPEED_UP_RATE R W 5 h0 ALC attack time for speed up mode attack time 2 2 n 48k n alc_atk_rate 4 0 5 h00 42us 5 h01 83us 5 h02 166us 5 h13 21 85s 17 6 2 16 0x1D Address...

Page 350: ...R W 1 b0 ALC force fast recovery control 1 b0 Disable force fast recovery 1 b1 Enable force fast recovery 8 ALC_FORCE_FAST_RC_EN R W 1 b1 ALC force fast recovery control for special cases zero data m...

Page 351: ...atio select control when noise gate is enabled 2 b00 1 1 2 b01 2 1 2 b10 4 1 2 b11 8 1 15 RSVD N A 1 b0 Reserved 17 6 2 19 0x20 Address Bit Name Access Reset Description 0x20 1 0 ALC_NOISE_RANGE R W 2...

Page 352: ...625dB 0 375dB step 17 6 2 21 0x22 Address Bit Name Access Reset Description 0x22 7 0 ALC_RC_WD_MAX R W 8 h74 Set upper bound of fast recovery window 8 h01 5 33ms 8 h02 10 67ms 8 hff 1360ms 15 8 ALC_RC...

Page 353: ...0 1 4 3 b001 1 8 3 b010 1 16 3 b011 1 32 3 b100 1 64 3 b101 1 128 3 b110 1 256 3 b111 hard limiter 8 ALC_ZERO_DATA_SEL R W 1 b1 ALC zero data mode selection control 1 b0 Decide zero data mode by root...

Page 354: ...W 1 b0 enable control for minimum gain control in ALC 1 b0 ALC minimum gain is disabled 1 b1 ALC minimum gain is disabled 15 14 RSVD N A 2 b00 Reserved 17 6 2 25 0x27 Address Bit Name Access Reset De...

Page 355: ..._BK_RMS_LOV_R R 1 b0 Status of back end R channel 1 b0 Energy of back end alc_thmax alc_min_range 1 b1 Energy of back end alc_thmax alc_min_range 4 ALC_FORCE_FAST_RC_M ODE R 1 b0 Status of fast recove...

Page 356: ...3 b011 Debounce 640ms at sample rate 48kHz 3 b100 Debounce 1 28s at sample rate 48kHz 3 b101 Debounce 2 56s at sample rate 48kHz 3 b110 Debounce 5 12s at sample rate 48kHz 3 b111 Debounce 0 16ms at sa...

Page 357: ...d 11 DAC_R_SILENECE_DET _MONO_STATUS R 1 b0 Ongoing status of dac_r_silence detection 1 b0 dac_r_silence detection is resting clock is gating 1 b1 dac_r_silence detection is working 15 12 RSVD N A 4 h...

Page 358: ...a threshold is register controlled 1 b1 adc_r_silence data threshold is automatically controlled 3 2 ADC_R_SILENCE_MONO_ DATA_BIT R W 2 h0 adc_r_silence detection input data word length 2 b00 16 bit 2...

Page 359: ...6 samples 2 b01 1024 32 samples 2 b10 1024 64 samples 2 b11 256 samples 15 DAC_L_DMIX_IN_SEL R W 1 b0 Mon DAC Lch upsample filter input select 1 b0 ALC output 1 b1 Mono DAC volume output 17 6 2 33 0xF...

Page 360: ...D 0 DAC_R_DA_MUTE R W 1 b0 Mon DAC Rch DVOL mute enable 1 b0 Un mute 1 b1 Mute 1 RSVD N A 1 b0 Reserved 2 DAC_R_DMIX_MUTE_128FS_DA R W 1 b0 Mon DAC Rch 128fs domain mixer da path mute enable 1 b0 Un m...

Page 361: ...ient b2 2 s complement in 4 25 format which means that the range is from 8 7 99 0x30 12 0 DAC_L_BIQUAD_B2_1 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 3 5 0x31 0x32 Address Bit Name Access Re...

Page 362: ..._B2_2 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 3 10 0x3B 0x3C Address Bit Name Access Reset Description 0x3B 15 0 DAC_L_BIQUAD_A1_2 15 0 R W 16 h0 DAC Lch EQ 2nd band coefficient a1 2 s com...

Page 363: ...3 15 0 R W 16 h0 DAC Lch EQ 3rd band coefficient a1 2 s complement in 4 25 format which means that the range is from 8 7 99 0x46 12 0 DAC_L_BIQUAD_A1_3 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 1...

Page 364: ...QUAD_A1_4 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 3 21 0x51 0x52 Address Bit Name Access Reset Description 0x51 15 0 DAC_L_BIQUAD_A2_4 15 0 R W 16 h0 DAC Lch EQ 4th band coefficient a2 2 s...

Page 365: ...tion 0x5B 15 0 DAC_L_BIQUAD_A2_5 15 0 R W 16 h0 DAC Lch EQ 5th band coefficient a2 2 s complement in 4 25 format which means that the range is from 8 7 99 0x5C 12 0 DAC_L_BIQUAD_A2_5 28 16 R W 13 h0 1...

Page 366: ...st band coefficient b2 2 s complement in 4 25 format which means that the range is from 8 7 99 0x63 12 0 DAC_R_BIQUAD_B2_1 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 3 31 0x64 0x65 Address Bi...

Page 367: ...BIQUAD_B2_2 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 3 36 0x6E 0x6F Address Bit Name Access Reset Description 0x6E 15 0 DAC_R_BIQUAD_A1_2 15 0 R W 16 h0 DAC Rch EQ 2nd band coefficient a1 2...

Page 368: ...A1_3 15 0 R W 16 h0 DAC Rch EQ 3rd band coefficient a1 2 s complement in 4 25 format which means that the range is from 8 7 99 0x79 12 0 DAC_R_BIQUAD_A1_3 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserve...

Page 369: ...D_A1_4 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 3 47 0x84 0x85 Address Bit Name Access Reset Description 0x84 15 0 DAC_R_BIQUAD_A2_4 15 0 R W 16 h0 DAC Rch EQ 4th band coefficient a2 2 s co...

Page 370: ...x8E 0x8F Address Bit Name Access Reset Description 0x8E 15 0 DAC_R_BIQUAD_A2_5 15 0 R W 16 h0 DAC Rch EQ 5th band coefficient a2 2 s complement in 4 25 format which means that the range is from 8 7 99...

Page 371: ...t Description 0x95 15 0 ADC_L_BIQUAD_B2_1 15 0 R W 16 h0 ADC Lch EQ 1st band coefficient b2 2 s complement in 4 25 format which means that the range is from 8 7 99 0x96 12 0 ADC_L_BIQUAD_B2_1 28 16 R...

Page 372: ...complement in 4 25 format which means that the range is from 8 7 99 0xA0 12 0 ADC_L_BIQUAD_B2_2 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 4 10 0xA1 0xA2 Address Bit Name Access Reset Descri...

Page 373: ...BIQUAD_B2_3 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 4 15 0xAB 0xAC Address Bit Name Access Reset Description 0xAB 15 0 ADC_L_BIQUAD_A1_3 15 0 R W 16 h0 ADC Lch EQ 3rd band coefficient a1 2...

Page 374: ...A1_4 15 0 R W 16 h0 ADC Lch EQ 4th band coefficient a1 2 s complement in 4 25 format which means that the range is from 8 7 99 0xB6 12 0 ADC_L_BIQUAD_A1_4 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserve...

Page 375: ...7 99 0xC0 12 0 ADC_L_BIQUAD_A1_5 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 4 26 0xC1 0xC2 Address Bit Name Access Reset Description 0xC1 15 0 ADC_L_BIQUAD_A2_5 15 0 R W 16 h0 ADC Lch EQ 5th...

Page 376: ...N A 3 b000 Reserved 17 6 4 30 0xC8 0xC9 Address Bit Name Access Reset Description 0xC8 15 0 ADC_R_BIQUAD_B2_1 15 0 R W 16 h0 ADC Rch EQ 1st band coefficient b2 2 s complement in 4 25 format which mean...

Page 377: ...5 0 R W 16 h0 ADC Rch EQ 2nd band coefficient b2 2 s complement in 4 25 format which means that the range is from 8 7 99 0xD3 12 0 ADC_R_BIQUAD_B2_2 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6...

Page 378: ...R_BIQUAD_B2_3 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 17 6 4 41 0xDE 0xDF Address Bit Name Access Reset Description 0xDE 15 0 ADC_R_BIQUAD_A1_3 15 0 R W 16 h0 ADC Rch EQ 3rd band coefficient a1...

Page 379: ...4 15 0 R W 16 h0 ADC Rch EQ 4th band coefficient a1 2 s complement in 4 25 format which means that the range is from 8 7 99 0xE9 12 0 ADC_R_BIQUAD_A1_4 28 16 R W 13 h0 15 13 RSVD N A 3 b000 Reserved 1...

Page 380: ...0xF3 Address Bit Name Access Reset Description 0xF2 15 0 ADC_R_BIQUAD_A1_5 15 0 R W 16 h0 ADC Rch EQ 5th band coefficient a1 2 s complement in 4 25 format which means that the range is from 8 7 99 0x...

Page 381: ...ns of ACC which is implemented via SI bus 18 2 Features Mandatory or optional sample rate which audio codec module declares to support 8 bit 16 bit 24 bit sampling resolution Mono stereo audio I2S lef...

Page 382: ...ACC block diagram 18 3 2 Data Part Memory GDMA SPORT 18 3 2 1 FIFO Layout 18 3 2 1 1 16 bit Sampling Resolution 16 bit stereo data and mono data without lr_swap byte_swap are listed in Table 18 1 and...

Page 383: ...bit stereo data and mono data with byte_swap are listed in Table 18 5 and Table 18 6 Table 18 5 16 bit stereo data with byte_swap Address Offset 31 24 23 16 15 8 7 0 0x0000 R0 7 0 R0 15 8 L0 7 0 L0 1...

Page 384: ...RX 0x0004 L1 23 0 X TX or 8 h0 RX 0x0008 L2 23 0 X TX or 8 h0 RX 0x000C L3 23 0 X TX or 8 h0 RX 0x0010 L4 23 0 X TX or 8 h0 RX 0x0014 L5 23 0 X TX or 8 h0 RX 24 bit stereo data and mono data with byte...

Page 385: ...n configuration Data Format I2S Left Justified PCM Long Frame Sync Mode A Mode B Mode A_N Mode B_N PCM Short Frame Sync Mode A Mode B Mode A_N Mode B_N Resolution 8 bit 16 bit default 24 bit Channel S...

Page 386: ...ified data format 23 22 21 2 1 0 23 22 21 2 1 0 1 fs Right Channel Left Channel SD_I or SD_O SCK WS Fig 18 5 PCM mode B data format 23 22 21 2 1 0 23 22 21 2 1 0 1 fs Right Channel Left Channel SD_I o...

Page 387: ...lock source etc Refer to SPORT control registers for details 18 3 3 2 SI Control Before transferring audio data you also need to configure the related parameters on audio codec side In other words it...

Page 388: ...ock Module CLK_98P304 CLK_45P158 SYSPLL_400M clk_is_40M _ clk_is_128 fs 0x218 29 0x218 26 20 0x218 28 0 0 1 1 Fig 18 11 ACC clock architecture 18 4 Registers 18 4 1 SPORT Control Registers The physica...

Page 389: ...P_TX_DISABLE R W R W R W R W R W R W 15 14 13 12 11 10 9 8 SP_I2S_SELF_LPB K_EN SP_INV_I2S_SCLK SP_DATA_LEN_SEL SP_EN_I2S_MON O SP_EN_PCM_N_M ODE SP_DATA_FORMAT_SEL R W R W R W R W R W R W 7 6 5 4 3 2...

Page 390: ...mode A 3 b011 PCM mode B 3 b110 PCM mode A N 3 b111 PCM mode B N 7 DSP_CTL_MODE R W 1 b0 1 b1 DSP and SPORT handshaking is enabled 1 b0 GDMA and SPORT handshaking is enabled 6 SP_LOOPBACK R W 1 b0 1 b...

Page 391: ...Rx error counter 12 CLEAR_TX_ERR_CNT R W 1 b0 Write 1 b1 and then write 1 b0 to clear Tx error counter 11 RSVD N A 1 b0 Reserved 10 8 DEBUG_BUS_SEL R W 3 h0 3 b000 debug_bus_a 3 b001 debug_bus_b 3 b1...

Page 392: ...16 RX0_RCNT_BUS R 8 h0 Rx0 FIFO read counter status MIC path 15 8 TX1_WCNT_BUS R 8 h0 Tx1 FIFO write counter status SPK path 7 0 TX0_WCNT_BUS R 8 h0 Tx0 FIFO write counter status SPK path 18 4 1 7 SP...

Page 393: ...SI control 0 register SI_CLK_EN 0x0004 R W Audio codec clock control register 18 4 2 1 SI_CTRLR0 Name SI control 0 register Size 32 bits Address offset 0x0000 Read write access read write 31 30 29 28...

Page 394: ...set 0x0004 Read write access read write 31 30 29 28 27 26 25 7 6 5 4 3 2 1 0 RSVD REG_CLK_EN R W Bit Field Access Reset Description 31 1 RSVD N A 0 Reserved 0 REG_CLK_EN R W 1 1 b1 Turn on the clock o...

Page 395: ...s Ameba D SPI has the following features Support Motorola SPI Serial interface operation Support master or slave operation mode Provide two SPI ports SPI0 High speed configured as master or slave with...

Page 396: ...more than one slave be selected at any time In this mode it is assumed that the serial master has only a single slave select output 19 2 1 1 Motorola Serial Peripheral Interface SPI There are four po...

Page 397: ...The timing diagram of SS not toggling is illustrated in Fig 19 4 Fig 19 3 SPI Serial Format Continuous Transfers SCPH 0 and SS toggling Fig 19 4 SPI Serial Format Continuous Transfers SCPH 0 and SS no...

Page 398: ...Ratios When SPI is configured as a master device the maximum frequency of the bit rate clock sclk_out is one half the frequency of ssi_clk This allows the shift control logic to capture data on one c...

Page 399: ...e SPI data register DR The receive FIFO is loaded from the receive shift register by the shift control logic The receive FIFO generates a FIFO full interrupt request ssi_rxf_intr when the number of en...

Page 400: ...e transfer mode TMOD is set by writing to control register 0 CTRLR0 When transferring data on the serial bus the SPI slave can only operate in transmit and receive mode That is TMOD field in CTRLR0 re...

Page 401: ...the SPI is configured as a master additional logic can be included in the design in order to delay the default sample time of the rxd signal This additional logic can help to increase the maximum ach...

Page 402: ...data level DMATDLR can be used to early request dma_tx_req the DMA Controller indicating that the transmit FIFO is nearly empty The FIFO can then be refilled with data to continue the serial transfer...

Page 403: ...not selected its txd output is buffered resulting in a high impedance drive onto the serial master rxd line The serial clock that regulates the data transfer is generated by the serial master device a...

Page 404: ...FO requests are made to the DMA Controller whenever the number of entries in the transmit FIFO is less than or equal to the DMA Transmit Data Level Register DMATDLR value this is known as the watermar...

Page 405: ...ister RXOICR 0x3C R 1 bits 0x0 Receive FIFO Overflow Interrupt Clear Register RXUICR 0x40 R 1 bits 0x0 Receive FIFO Underflow Interrupt ClearRegister MSTICR FA EICR 0x44 R 1 bits 0x0 Multi Master Inte...

Page 406: ...red as a serial master device 0 ss_n_out doesn t toggle between successive frames 1 ss_n_out does toggle between successive frames 30 25 RSVD N A Reserved 24 RXBITSWAP R W 0 0 Order of receive bit doe...

Page 407: ...orola SPI The serial clock phase selects the relationship of the serial clock with the slave select signal When SCPH 0 data are captured on the first edge of the serial clock When SCPH 1 the serial cl...

Page 408: ...is equal to this register value plus 1 which enables you to receive up to 64 KB of data in a continuous transfer When the SPI is configured as a serial slave the transfer continues for as long as the...

Page 409: ...n the SPI is configured as a master device When the SPI is configured as a serial slave writing to this location has no effect reading from this location returns 0 The register derives the frequency o...

Page 410: ...tries are present in transmit FIFO 1111_1111 ssi_txe_intr is asserted when 255 data entries are present in transmit FIFO 19 3 2 7 RXFTLR Name Receive FIFO Threshold Level Size 6 bits Address offset 0x...

Page 411: ...r of valid data entries in the transmit FIFO 19 3 2 9 RXFLR Name Receive FIFO Level Register Size 7 bits Address offset 0x24 Read write access read This register contains the number of valid data entr...

Page 412: ...ftware to completely empty the receive FIFO 0 Receive FIFO is empty 1 Receive FIFO is not empty 2 TFE R 1 Transmit FIFO Empty When the transmit FIFO is completely empty this bit is set When the transm...

Page 413: ...derflow Interrupt Mask 0 ssi_rxu_intr interrupt is masked 1 ssi_rxu_intr interrupt is not masked 1 TXOIM R W 1 Transmit FIFO Overflow Interrupt Mask 0 ssi_txo_intr interrupt is masked 1 ssi_txo_intr i...

Page 414: ...g 0 TXEIS R 0 Transmit FIFO Empty Interrupt Status 0 ssi_txe_intr interrupt is not active after masking 1 ssi_txe_intr interrupt is active after masking 19 3 2 13 RISR Name Raw Interrupt StatusRegiste...

Page 415: ...pt Status 0 ssi_txe_intr interrupt is not active prior to masking 1 ssi_txe_intr interrupt is active prior to masking 19 3 2 14 TXOICR Name Transmit FIFO Overflow Interrupt ClearRegister Size 1 bit Ad...

Page 416: ...ption 31 1 RSVD N A Reserved 0 MSTICR FAEICR R 0 When SPI is configured as serial master this bit field is used to Clear Multi Master Contention Interrupt A read from this register clears the ssi_mst_...

Page 417: ...equest is made by the transmit logic It is equal to the watermark level that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this...

Page 418: ...erted when 253 or more data entries are present in transmit FIFO 1111_1101 dma_rx_req is asserted when 254 or more data entries are present in transmit FIFO 1111_1110 dma_rx_req is asserted when 255 o...

Page 419: ...e SPI are not addressable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR R W Bit Name Access Reset Description 31 16 RSVD N A Reserved 15 0 DR R W 0x0 Da...

Page 420: ...Description 31 0 N A N A N A 19 3 2 27 RSVD_1 Name Reserved location for future use Size 32 bits Address offset 0xF8 Read write access N A This register is reserved for future use Bit Name Access Res...

Page 421: ...20 1 2 Features Thin Film Transistor TFT color display LCD refresh rate 30Hz Max data rate 4 6MB s 8 16 bit MCU I8080 parallel interface Resolution of 8 16 bit mode 1024x1024 for still picture displa...

Page 422: ...out GRAM 20 2 Architecture 20 2 1 Block Diagram The block diagram of LCDC is show in Fig 20 3 Data Signal SYS_CLK 100MHz AXI_CLK 100MHz APB_CLK 100MHz AXI Master I F Config Register Timing Generator A...

Page 423: ...The application scenario is shown in Fig 20 5 Frame Buffer Ameba D LCM Display Glass Display Control LCDC I8080 Control DATA Fig 20 5 MCU I O mode application scenario When you use LCM Liquid Crystal...

Page 424: ...master gets frame from frame buffer automatically based on synchronous timings Trigger mode DMA master gets frame from frame buffer manually based on register trigger one frame one trigger This mode i...

Page 425: ...D you can read the data line Fig 20 10 MCU I F read command timing parameters 20 2 2 3 MCU System with VSYNC Interface LCDC VSYNC interface starts synchronization to display the moving picture with MC...

Page 426: ...output data is synchronized with LCD TE output signal LCD TE signal is used to synchronize frame memory writing for displaying video images The MCU TE mode timing is shown in Fig 20 12 tvdh The LCD di...

Page 427: ...The RGB interface is shown in Fig 20 16 Count 0 1 2 3 4 RS 0 1 1 1 1 D7 C7 P1R4 P1G2 P2R4 P2G2 D6 C6 P1R3 P1G1 P2R3 P2G1 D5 C5 P1R2 P1G0 P2R2 P2G0 D4 C4 P1R1 P1B4 P2R1 P2B4 D3 C3 P1R0 P1B3 P2R0 P2B3 D...

Page 428: ...erface 20 2 3 1 RGB Timing The RGB timing is shown in Fig 20 17 HSYNC width HBP HFP Activewindow width VSYNC width VBP Active window Height VFP Total plane height TotalPlane width Fig 20 17 RGB timing...

Page 429: ...settings of HSYNC signal and VSW VBP VFP settings of VSYNC This mode doesn t need ENABLE signal 20 2 3 4 RGB I F 6 bit Output The RGB I F 6 bit output is shown in Fig 20 19 with RGB565 bits output Fig...

Page 430: ...uration such that by switching on or off selected lights text or graphics can be displayed A dot matrix controller converts instructions from a processor into signals which turns on or off lights in t...

Page 431: ...SHCP STCP Q7S Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 16x8 LED 74HC595_1 DS SHCP STCP Q7S Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 16x8 LED 74HC595_7 DS SHCP STCP Q7S Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 16x8 LED R1 G1 R2 G2 LAT CLK OE A B C D A...

Page 432: ...N OE LATW 1 2 3 4 5 6 LED 0 N LED 0 N 1 LED 0 N 2 LED 0 0 LAT CLK R1 Line_Sel D A Y 0 LED 1 N LED 1 N 1 LED 0 N LED 0 N 1 LED 0 N 2 LED 0 0 G1 LED 1 N LED 1 N 1 LED 16 N LED 16 N 1 LED 16 N 2 LED 15 0...

Page 433: ...ol diagram 20 2 4 3 LED Color Mapping 20 2 4 3 1 Single Color and Single Channel The single color and single channel of LED color mapping is shown in Fig 20 24 LED 08 12 I F Control R1 D0 D1 D2 D3 DMA...

Page 434: ...d two channels 20 2 4 3 3 Two Colors and Single Channel The two colors and single channel of LED color mapping is shown in Fig 20 26 LED 08 12 I F Control R1 G1 D0 D1 D2 D3 DMA Control Timing Register...

Page 435: ...and two channels 20 2 4 3 5 Three Colors and Single Channel The three colors and single channel of LED color mapping is shown in Fig 20 28 R1 G1 B1 LED 08 12 I F Control R1 G1 B1 D0 D1 D2 D3 DMA Contr...

Page 436: ...Table 20 2 LCDC pinmux MCU System RGB Interface LED Interface D 15 0 I O D 15 0 I O D 5 0 Line_Sel 9 0 I O WR I DCLK O DCLK O RD I HSYNC O LAT O RS I CS I ENABLE I OE O TE VSYNC O I VSYNC I 20 2 6 Su...

Page 437: ...s Mode Maximum Support Resolution Common Support Resolution Refresh Frequency 8 bit mode 645 645 120 240 240 320 320 480 etc 30Hz 16 bit mode 912 912 120 240 240 320 320 480 640 480 etc 30Hz 20 2 6 4...

Page 438: ...DC raw interrupt register LCDC_LINE_INT_POS 0x002C R W The position of the line interrupt LCDC_CUR_POS_STATUS 0x0030 RO The position of current display LCDC_ STATUS 0x0034 RO Underflow times for debug...

Page 439: ...is only terminated with this bit This bit can t be set when LCDCDIS is active or at the same time of setting LCDCDIS 1 LCDCDIS R W1only 0 During the period of valid line VTIMING valid data this disabl...

Page 440: ...ta drops There is an underflow pixel counter to realize this 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD DMAUNMODE RSVD R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERROUTDATA R W Bit Name Acces...

Page 441: ...write This register is just for RGB and LED screen 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKDIV R W Bit Name Access Reset Description 31 16 RSVD N...

Page 442: ...W1C Bit Name Access Reset Description 31 6 RSVD N A 0 Reserved 5 FRM_START_INTS R W1C 0 DMA frame start interrupt status Write 1 to clear it 0 No DMA frame start interrupt generated 1 A DMA frame star...

Page 443: ...rupt raw status No matter the line interrupt is enabled or disabled this bit is set when line interrupt happens Write 1 to the LCD_LIN_INTS field in register LCDC_IRQ_STATUS to clear this bit 2 LCDFRD...

Page 444: ...urn the current X position 20 3 2 6 LCDC_STATUS Size 32 bits Address offset 0x0034 Read write access read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 445: ...R W 0 The HSYNC pulse polarity 0 Low level synchronous clock 1 High level synchronous clock 17 VSPL R W 0 The VSYNC pulse polarity 0 Low level synchronous clock 1 High level synchronous clock 16 DCLK...

Page 446: ...nization signal width 1 Unit DCLK HSW s minimum value is 1 20 3 3 4 LCDC_RGB_SYNC_STATUS Name LCDC RGB synchronization status register Size 32 bits Address offset 0x004C Read write access read only Th...

Page 447: ...ring effect line on Mode1 VSYNC Others Reserved 8 MCUIFUPDATE R W1S 0 Force Hardware to update MCU I F Timing shadow register at specific timing CPU writes 1 to force Hardware updating After Hardware...

Page 448: ...t WR pulse width MCUIFMODE 2 Invalid usage The maximum value is 1048571 11 8 RSVD N A 0 Reserved 7 0 MCUVSW R W SHW 0 VSYNC signal width 1 Unit WR pulse width only for MCU VSYNC mode 20 3 4 3 LCDC_MCU...

Page 449: ...ead from LCM through MCU I O mode I F Note Not until the I O TX FIFO is empty can this register be read To ensure a correct value is read from this register the bit IO_TIMEOUT_INTRS in LCDC_IRQ_RAW mu...

Page 450: ...rent LED refresh frame done CPU writes 1 to force Hardware updating parameters After updating this bit is cleared When the LCDC is running if the following values related with LED I F mode are modifie...

Page 451: ...0x0090 Read write access read write 31 30 29 28 27 26 25 6 5 4 3 2 1 0 IMG_BASE_ADDR R W Bit Name Access Reset Description 31 0 IMG_BASE_ADDR R W 0 Image DMA source address After a frame refresh done...

Page 452: ...LCDC_MCU_TIMING_CFG register for MCU timings c Set LCDC_MCU_CFG register to enable MCU I O mode 6 Start transfer by writing 1 to the LCDCEN bit of LCDC_CTRL register 7 Send CMD CMD parameters to LCD t...

Page 453: ...related functions are used 21 1 3 Application Scenario Fig 21 1 shows typical quadrature signals from a rotary encoder The signals named PHA and PHB are two quadrature signals The figure shows how ph...

Page 454: ...lock diagram of the Q Decoder is show in Fig 21 3 Quadrature Decoder Interrupt Control Phase A Phase B Index Reset SCLK 32KHz APB PCLK Compare Dir Index Debounce V Counter Capture V Timer V Reload Vel...

Page 455: ...g 21 6 the maximum position counter MPC is set to 199 If the movement direction is forward and the position counter is equal to MPC the PC is reset to 0 on the next state If the movement direction is...

Page 456: ...and the position counter is reset on the index pulse signal with the PHA PHB state is 0 0 Besides the maximum position counter is set to 199 0 1 2 3 PHA PHB IDX 7 6 5 4 5 4 3 2 1 0 199 Fig 21 7 Positi...

Page 457: ...1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 198 197 196 7 6 5 4 3 2 1 0 199 198 197 196 PHA PHB IDX PC Index pulse detection RC 5 6 1 1 5 Direction 0 195 195 Fig 21 10 IDX_INV 1 position counter reset on PHA PHB 1...

Page 458: ...sampling clock time Note You should insert a time delay operation between a subsequent reset operation and a disable Q decoder operation The delay time period should be larger than 2 divided sampling...

Page 459: ...nter increases or decreases by 1 for every position counter overflow 1 or underflow 1 occurred Fig 21 13 illustrates this case 1 1 1 1 199 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 198 199 0 1 2 198 197 1...

Page 460: ...r Index Signal Configuration Register Velocity Measurement Registers REG_VCTRL 0x0018 R W Q Decoder Velocity Control Register REG_VC 0x001c RO Q Decoder Velocity Counter Register REG_VCCAP 0x0020 RO Q...

Page 461: ...is gated Clear all interrupt status 30 PC_RST R W 0 Position counter reset 0 Position counter is not in reset state normal active 1 Writing 1 to this bit resets the position counter to 0 The position...

Page 462: ...interrupt This interrupt is asserted when the position counter is equal to the value of PCC 18 DR_INT_EN R W 0 Movement direction changed interrupt enable control 1 Enable interrupt 0 Disable interrup...

Page 463: ...ss offset 0x0008 Read write access read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCC R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPC R W Bit Name Access Default Description 31 16 PCC R W 0...

Page 464: ...ounter overflow or underflow occurs a corresponding interrupt is asserted 19 18 STA R 0 The Q decoder phase state current state of A B phase 17 ALS R 0 The status of auto load to set initial phase 1 A...

Page 465: ...gnal only 10 Reset the position counter on every index pulse signal 11 Reserved 2 RSVD N A Reserved 1 POS_RST_PHA R W 0 To assign the state of the phase_A signal for the accumulation position counter...

Page 466: ...INT_EN R W 0 Velocity counter capture interrupt enable control 0 Disable interrupt 1 Enable interrupt The velocity counter register and the position counter are captured in capture registers when the...

Page 467: ...VD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VC_CAP R Bit Name Access Default Description 31 16 RSVD N A Reserved 15 0 VC_CAP R 0 When the velocity timer reaches zero the velocity counter register is capt...

Page 468: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 VT R Bit Name Access Default Description 31 16 RSVD N A Reserved 15 0 VT R 0x0 This is the velocity timer value of the down counter 21 3 3 7 REG_VCOMP Name Q Decoder V...

Page 469: ...e velocity counter capture is less than the velocity low limit this interrupt is asserted 11 RSVD N A Reserved 10 VCCAP_INT_M R W 0 Velocity counter capture interrupt mask 0 Unmask 1 Mask When the vel...

Page 470: ...sition counter underflow is occurred 1 OF_INT_M R W 0 Position counter overflow interrupt mask 0 Unmask 1 Mask This interrupt is asserted when the position counter overflow is occurred 0 CT_INT_M R W...

Page 471: ...ROF_INT_S R WC 0 Rotation counter overflow interrupt status 0 No interrupt 1 Interrupt pending Writing 1 to this bit clears this interrupt status 5 PC_INT_S R WC 0 Position counter comparing interrupt...

Page 472: ...tereo 5 1 channel Sample bit for mono 16 bit 32 bit Sample bit for stereo 5 1 channel 16 bit 24 bit 32 bit Integrated DMA engine to minimize the software efforts Master or slave mode Mono and stereo T...

Page 473: ...2 sample rate sample bit 22 4 1 2 Word Select Word Select WS indicates the channel being transmitted WS 0 Channel 1 left WS 1 Channel 2 right There is no need to be symmetrical it changes either on a...

Page 474: ...OW or the leading LOW to HIGH edge of the clock signal SD must be latched into the receiver on the leading edge of SCK 22 4 2 Operation Mode 22 4 2 1 Transmitter as the Master In this operation mode a...

Page 475: ...stereo the left channel is transmitted when WS 0 and the right channel is transmitted when WS 1 The transmitter and the receiver may have different word length SCK WS SD Left Right MSB LSB MSB LSB Fig...

Page 476: ...ed when WS 1 and the right channel is transmitted when WS 0 The transmitter and the receiver must have the same word length WS SD Left Right MSB LSB MSB LSB SCK Fig 22 9 Right justified standard 22 4...

Page 477: ...25kHz 7 35kHz 50PPM Table 1 1 shows the details of clock configuration Table 22 1 Clock configuration Sample Rate WS SCK 16 bit SCK 24 bit 32 bit MCK 384kHz 384kHz 12 288MHz 24 576MHz 98 304MHz 192kHz...

Page 478: ...Register Tx Rx pagepointer Memory Block Pagesize Pagesize Pagesize Pagesize Pagenumber pagepointer Fig 22 11 Memory block 22 4 6 FIFO Allocation Asynchronous FIFO is used to buffer data from memory t...

Page 479: ...nel 14 Mono channel 13 Mono channel 12 MSB LSB 31 0 Fig 22 12 FIFO allocation of mono channel sample bit 16 bit Mono channel 1 Samplebit 32 bit Mono channel 2 Mono channel 3 Mono channel 6 Mono channe...

Page 480: ...channel Right channel Right channel Left channel Right channel Left channel Right channel MSB LSB 31 0 Fig 22 14 FIFO allocation of stereo channel sample bit 16 bit Left channel Samplebit 24 bit Right...

Page 481: ...nel FIFO When the sample bit is 16 bit or 24 bit or 32 bit the FIFO allocation of the 5 1 channel are illustrated in Fig 22 17 to Fig 22 19 Left channel A Samplebit 16 bit Right channel A Left channel...

Page 482: ...0 8 b0 8 b0 8 b0 8 b0 Fig 22 18 FIFO allocation of 5 1 channel sample bit 24 bit Left channel A Right channel B Left channel A Left channel B Right channel C Left channel C Right channel A Samplebit 3...

Page 483: ...I2S Rx Page 0 Own Bit Register IS_RX_PAGE_OWN1 0x0034 R W I2S Rx Page 1 Own Bit Register IS_RX_PAGE_OWN2 0x0038 R W I2S Rx Page 2 Own Bit Register IS_RX_PAGE_OWN3 0x003C R W I2S Rx Page 3 Own Bit Reg...

Page 484: ...l testing 6 RSVD N A Reserved 5 EDGE_SW R W 0x0 Edge switch 0 Negative edge 1 Positive edge 4 3 AUDIO_MONO R W 0x0 Audio mono 00 Stereo audio 01 5 1 Audio 10 Mono 2 1 TX_ACT R W 0x0 Tx activity 00 Rx...

Page 485: ...TCH SR R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SR PAGE_NUM PAGE_SIZE R W R W R W Bit Name Access Reset Description 31 19 RSVD N A Reserved 18 CLK_SWITCH R W 0x0 I2S clock switch 0 CLK_I2S 98 304...

Page 486: ...OKIE_TX R W 0x0 Tx Page 3 OK Interrupt Enable 0 Disable interrupt 1 Enable interrupt 2 P2OKIE_TX R W 0x0 Tx Page 2 OK Interrupt Enable 0 Disable interrupt 1 Enable interrupt 1 P1OKIE_TX R W 0x0 Tx Pag...

Page 487: ...r 22 5 7 Rx Interrupt Enable Register IS_RX_MASK_INT Name I2S Rx Interrupt Enable Register Size 32 bits Address offset 0x0018 Read write access read write 31 30 29 28 12 11 10 9 RSVD 8 7 6 5 4 3 2 1 0...

Page 488: ...x0 Rx FIFO Full Interrupt Pending 0 No interrupt 1 Interrupt pending write 1 to clear 7 PAGEUNAVA_IP_RX3 R W 0x0 Rx Page 3 Unavailable Interrupt Pending 0 No interrupt 1 Interrupt pending write 1 to c...

Page 489: ...22 5 10 Rx Page Own Bit Register IS_RX_PAGE_OWNx Name I2S Rx Page x Own Bit Register x 0 1 2 3 Size 32 bits Address offset for x 0 to 3 IS_RX_PAGE_OWN0 0x0030 IS_RX_PAGE_OWN1 0x0034 IS_RX_PAGE_OWN2 0...

Page 490: ...e and models device pins as well as certain on chip functions See also Full Functional Model BLE Bluetooth Low Energy a wireless local area network technology BT Bluetooth BTN Button bus bridge Logic...

Page 491: ...HDL HFP Horizontal Front Porch HSW Horizontal Pulse Width HSYNC Horizontal Synchronization HV Mode Horizontal Vertical Mode HWJ Hardware judgement mode I2S Inter IC Sound INT Interrupt Interface Set o...

Page 492: ...requency division PSRAM Pseudo Static Random Access Memory QVGA Quarter VGA RC Rotation Counter RGB Red Green Blue RGB I F RGB Interface RGB Mode RGB Interface Mode RGB565 Red 5 bits Green 6 bits Blue...

Page 493: ...cument is subject to legal disclaimers REALTEK 2019 All rights reserved 493 VFP Vertical Front Porch VGA Video Graphics Array VSW VSYNC Pulse Width VSYNC Vertical Synchronization Realtek confidential...

Page 494: ...st in LCDC Add Audio Pad in Pad Control and Pinmux Update some incorrect description and delete the compensation example in IR Update features electrical characteristics DMIC AMIC connection figures i...

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